CN211428157U - Structure for improving reliability of semiconductor device - Google Patents
Structure for improving reliability of semiconductor device Download PDFInfo
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- CN211428157U CN211428157U CN202020206245.0U CN202020206245U CN211428157U CN 211428157 U CN211428157 U CN 211428157U CN 202020206245 U CN202020206245 U CN 202020206245U CN 211428157 U CN211428157 U CN 211428157U
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Abstract
The utility model discloses a structure for improving the reliability of a semiconductor device, which is provided with a metal wire layer, wherein the surface of the metal wire layer is covered with a protective layer; an adhesion layer capable of improving the adhesion between the metal wire layer and the protective layer is arranged between the side wall of the metal wire layer and the protective layer. It has the following advantages: the side wall of the metal wire layer and the protective layer have better adhesiveness and bonding tightness, and the reliability of the semiconductor device is improved.
Description
Technical Field
The utility model relates to an improve structure of semiconductor device reliability.
Background
Compound semiconductors, such as gallium arsenide, often suffer from reliability verification failures, especially in high temperature, high humidity and voltage-bearing test environments. The gallium arsenide semiconductor device has a metal wire layer, the surface of the metal wire layer 100 is covered with a protection layer 102, the current process deposits an adhesion layer 103 (such as metal titanium Ti) between the metal wire layer (such as metal gold Au) and the protection layer (such as silicon nitride SiN) to improve the adhesion between metal gold and protection layer silicon nitride, but at present, only titanium can be deposited on the upper half of the metal wire layer 100, no metal titanium is deposited on the sidewall, the area of the sidewall is much larger than that of the top wall, and is a larger area for the protection layer silicon nitride to adhere to, so metal titanium is more required to be deposited to improve the adhesion of the protection layer silicon nitride on the sidewall metal gold. If the metal gold and the protective layer silicon nitride are not well combined, moisture can easily permeate into the metal and the protective layer during high-temperature and high-humidity testing, so that reliability failure is caused.
SUMMERY OF THE UTILITY MODEL
The utility model provides an improve structure of semiconductor device reliability, it has overcome in the background art the not enough of prior art.
The utility model provides a technical scheme that its technical problem adopted is:
a structure for improving the reliability of a semiconductor device having a metal wire layer, the surface of which is covered with a protective layer; the method is characterized in that: an adhesion layer capable of improving the adhesion between the metal wire layer and the protective layer is arranged between the side wall of the metal wire layer and the protective layer.
In one embodiment: the metal wire layer is a gold layer, the protection layer is a silicon nitride layer, and the adhesion layer is a titanium layer. (please note that other possible material alternatives for the three material layers).
In one embodiment: the thickness of the adhesion layer is between 30-90 um.
In one embodiment: the cross section of the metal wire layer is in a trapezoidal structure with a narrow top and a wide bottom.
In one embodiment: the semiconductor device is any one of a gallium arsenide device, an indium phosphide device and a gallium nitride device.
Compared with the background technology, the technical scheme has the following advantages:
the adhesion layer is arranged between the side wall of the metal wire layer and the protection layer, so that the adhesion and the bonding tightness of the side wall of the metal wire layer and the protection layer can be improved, and the reliability of the semiconductor device is further improved.
Drawings
The present invention will be further explained with reference to the drawings and examples.
Fig. 1 is a schematic structural view of a conventional metal wire layer described in the background art.
Fig. 2 is a schematic structural diagram of a metal wire layer according to this embodiment.
Detailed Description
Referring to fig. 2, a structure for improving reliability of a semiconductor device having a metal wire layer 10, the surface of the metal wire layer 10 is covered with a protection layer 12; an adhesion layer 13 capable of improving adhesion between the metal wire layer 10 and the protective layer 12 is provided between the side wall of the metal wire layer 10 and the protective layer 12.
The metal wire layer 10 is a gold layer, the passivation layer 12 is a silicon nitride layer, and the adhesion layer 13 is a titanium layer. (please note that other possible material alternatives for the three material layers).
The thickness of the adhesive layer 13 is between 30-90 um.
The cross section of the metal wire layer 10 may be a rectangular structure or a trapezoidal structure with a narrow top and a wide bottom.
The semiconductor device may be any one of a gallium arsenide device, an indium phosphide device, and a gallium nitride device.
In a preferred embodiment, the process for fabricating the metal wire layer of the gaas device includes the following steps:
(1) metal deposition, in gallium arsenide process, metal gold (Au) is typically deposited, and evaporation process or electroplating process and combined with a reverse exposure development process can be used to plate gold on the metal wire layer.
(2) Depositing titanium metal, depositing titanium on the surface of the whole metal wire layer, and adopting a sputtering process to ensure that the side wall can also deposit the titanium metal.
(3) By formal developing process, the pattern (metal wire layer) after depositing metal titanium is covered by photoresist, the pattern on the photomask is positive pattern, the yellow light energy and well depth are adjusted, so that the photoresist covers the 0.2um position on the left and right sides of the pattern (metal wire layer).
(4) And removing the metal titanium without the protection of the photoresist by adopting an etching process, such as dry plasma etching.
(5) Depositing a silicon nitride protective layer on the surface of the metal wire layer, and packaging the routing test opening.
The utility model discloses a deposit adhesion layer between the lateral wall of metal wire layer and protective layer, guarantee to have better adhesion between metal wire layer and the protective layer, ensure that the protective layer closely adheres on the metal wire layer, avoid steam to permeate into easily between metal and the protective layer, and cause the reliability failure.
The above description is only a preferred embodiment of the present invention, and therefore the scope of the present invention should not be limited by this description, and all equivalent changes and modifications made within the scope and the specification of the present invention should be covered by the present invention.
Claims (5)
1. A structure for improving the reliability of a semiconductor device having a metal wire layer, the surface of which is covered with a protective layer; the method is characterized in that: an adhesion layer capable of improving the adhesion between the metal wire layer and the protective layer is arranged between the side wall of the metal wire layer and the protective layer.
2. A structure for improving reliability of a semiconductor device according to claim 1, wherein: the metal wire layer is a gold layer, the protection layer is a silicon nitride layer, and the adhesion layer is a titanium layer.
3. A structure for improving reliability of a semiconductor device according to claim 1 or 2, wherein: the thickness of the adhesion layer is between 30-90 um.
4. A structure for improving reliability of a semiconductor device according to claim 1 or 2, wherein: the cross section of the metal wire layer is in a trapezoidal structure with a narrow top and a wide bottom.
5. A structure for improving reliability of a semiconductor device according to claim 1 or 2, wherein: the semiconductor device is any one of a gallium arsenide device, an indium phosphide device and a gallium nitride device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020206245.0U CN211428157U (en) | 2020-02-25 | 2020-02-25 | Structure for improving reliability of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020206245.0U CN211428157U (en) | 2020-02-25 | 2020-02-25 | Structure for improving reliability of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211428157U true CN211428157U (en) | 2020-09-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN202020206245.0U Active CN211428157U (en) | 2020-02-25 | 2020-02-25 | Structure for improving reliability of semiconductor device |
Country Status (1)
| Country | Link |
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| CN (1) | CN211428157U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113054077A (en) * | 2021-03-16 | 2021-06-29 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof, display device and splicing display device |
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2020
- 2020-02-25 CN CN202020206245.0U patent/CN211428157U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113054077A (en) * | 2021-03-16 | 2021-06-29 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof, display device and splicing display device |
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