CN211404065U - Read operation circuit and semiconductor memory - Google Patents

Abstract

An embodiment of the present application provides a read operation circuit and a semiconductor memory, including: the DBI coding module is used for reading out read data from the storage block and determining whether the read data are inverted or not according to the high data bit number in the read data so as to output global bus data for global bus transmission and DBI data for DBI signal line transmission, and the DBI port is used for receiving the DBI data; the parallel-serial conversion circuit is used for carrying out parallel-serial conversion on the global bus data to generate output data of a DQ port; the data buffer module is connected to the storage block through a global bus; and the precharge module is connected to the precharge signal line and used for setting the initial state of the global bus to be low. According to the technical scheme of the embodiment of the application, more data of '0' can be transmitted on the global bus of the Precharge pull-down architecture, so that the turnover frequency of the internal global bus can be reduced, the current is greatly compressed, and the power consumption is reduced.

Description

Read operation circuit and semiconductor memory

Technical Field

The present disclosure relates to the field of semiconductor memory technologies, and in particular, to a read operation circuit, a semiconductor memory, and a read operation method.

Background

This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

The semiconductor Memory includes a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a Read-Only Memory (ROM), and a flash Memory.

In the DRAM protocol of Joint Electron Device Engineering Council (JEDEC), there are specific requirements for DRAM speed and power saving. How to save more power for the DRAM and ensure the integrity of the signal and the reliability of data transmission and storage is an urgent problem to be solved in the industry.

SUMMERY OF THE UTILITY MODEL

Embodiments of the present application provide a read operation circuit and a semiconductor memory to solve or alleviate one or more technical problems in the prior art.

In a first aspect, an embodiment of the present application provides a read operation circuit, which is applied to a semiconductor memory, where the semiconductor memory includes a DQ port, a DBI port, and a memory block, and the read operation circuit includes:

the DBI coding module is connected with the storage block and used for reading out the read data from the storage block and determining whether the read data is inverted or not according to the high data bit number in the read data so as to output global bus data for global bus transmission and DBI data for DBI signal line transmission, and the DBI port is used for receiving the DBI data;

the parallel-serial conversion circuit is connected between the DQ port and the DBI coding module through a global bus and is used for carrying out parallel-serial conversion on global bus data to generate output data of the DQ port;

the data buffer module is connected to the storage block through a global bus;

and the precharge module is connected to the precharge signal line and used for setting the initial state of the global bus to be low.

In one embodiment, the DBI encoding module is configured to output, as global bus data, inverted data of read data when a bit number of data that is high in the read data is greater than a preset value, and set the DBI data to be high; and under the condition that the bit number of the data which is high in the read data is less than or equal to a preset value, outputting the original read data as global bus data, and setting the DBI data to be low.

In one embodiment, M-bit DBI data corresponds to M groups of read data one to one, and M-bit DBI data corresponds to M groups of global bus data one to one, and the parallel-to-serial conversion circuit is further connected between the DBI encoding module and the DBI port, and configured to output the M-bit DBI data to the DBI port after parallel-to-serial conversion, where M is an integer greater than 1.

In one embodiment, each set of read data is N bits, where N is an integer greater than 1, and the DBI encoding module is configured to output, as a set of corresponding global bus data, inverted data of an input set of read data when a bit number of data that is high in the input set of read data is greater than N/2, and set a bit of DBI data corresponding to the input set of read data high; and under the condition that the bit number of data which is high in the input group of read data is less than or equal to N/2, outputting the input group of read data as a corresponding group of global bus data, and setting one bit of DBI data which corresponds to the input group of read data to be low.

In one embodiment, the DBI encoding module includes:

the DBI coding unit is used for setting the DBI data to be high under the condition that the bit number of the data which is high in the read data is greater than a preset value; setting the DBI data to be low under the condition that the digit of the data which is high in the read data is less than or equal to a preset value;

the input end of the data selector is connected with the DBI coding unit and used for receiving read data through the DBI coding unit, the input end of the data selector also receives DBI data through a DBI signal line, the output end of the data selector is connected with the parallel-serial conversion circuit through a global bus, and the data selector is used for outputting inverted data of the read data as global bus data under the condition that the DBI data are high; and outputting the original read data as global bus data if the DBI data is high.

In one embodiment, the data selector includes a plurality of data selection units, the data selection units including:

the input end of the first inverter receives DBI data through a DBI signal line;

the input end of the second inverter is connected to the DBI coding unit and used for receiving read data from the DBI coding unit;

the input end of the first transmission gate is connected to the output end of the second phase inverter, the output end of the first transmission gate is connected with the global bus and used for outputting global bus data, the inverted control end of the first transmission gate is connected to the output end of the first phase inverter, and the positive control end of the first transmission gate receives DBI data through a DBI signal line;

and the input end of the second transmission gate is connected with the DBI coding unit and used for receiving read data from the DBI coding unit, the output end of the second transmission gate is connected with the global bus and used for outputting the global bus data, the inverse control end of the second transmission gate receives the DBI data through a DBI signal line, and the positive control end of the second transmission gate is connected with the output end of the first phase inverter.

In one embodiment, the data selector includes a plurality of data selection units, the data selection units including:

the input end of the third inverter receives DBI data through a DBI signal line;

the input end of the fourth inverter is connected to the DBI coding unit and used for receiving read data from the DBI coding unit;

the first input end of the first logic AND gate is connected to the DBI coding unit and used for receiving read data from the DBI coding unit, and the second input end of the first logic AND gate is connected to the output end of the third inverter;

a first input end of the second logic AND gate receives DBI data through a DBI signal line, and a second input end of the second logic AND gate is connected to the output end of the fourth inverter;

and two input ends of the logic OR gate are respectively connected with the output end of the first logic AND gate and the output end of the second logic AND gate, and the output end of the logic OR gate is connected with the global bus and used for outputting global bus data.

In one embodiment, the data buffer module comprises a plurality of PMOS transistors, wherein the gates of the PMOS transistors are connected to the memory blocks, and the drains of the PMOS transistors are connected to the global bus; and the pre-charging module comprises a plurality of NMOS transistors and a plurality of holding circuits, wherein the gates of the NMOS transistors are connected to the pre-charging signal line, the drains of the NMOS transistors are connected to the global bus, and the input ends and the output ends of the holding circuits are connected to the global bus.

In a second aspect, embodiments of the present application provide a semiconductor memory, which includes a DQ port, a DBI port, a memory block, and a read operation circuit of any of the above.

By adopting the technical scheme, more data which are transmitted to be 0 on the global bus of the Precharge Low (pull-down) architecture can be realized, so that the turnover frequency of the internal global bus can be reduced, the current is greatly compressed, and the power consumption is reduced.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.

Fig. 1 is a block diagram schematically showing the structure of a semiconductor memory portion of one embodiment of the present embodiment;

fig. 2 is a block diagram schematically showing the structure of a semiconductor memory portion of another embodiment of the present embodiment;

FIG. 3 schematically shows a circuit diagram (corresponding to one memory block) of a data buffering module of one embodiment of the present embodiment;

FIG. 4 schematically shows a circuit diagram (corresponding to a plurality of memory blocks) of a data buffering module of one embodiment of the present embodiment;

FIG. 5 schematically illustrates a schematic diagram of the DBI function;

FIG. 6 is a block diagram schematically illustrating a DBI encoding module according to an embodiment of the present invention;

FIG. 7-1 schematically shows a block diagram of a data selection unit of an embodiment of the present embodiment;

fig. 7-2 schematically shows a block diagram of a data selection unit of another embodiment of the present embodiment.

Description of reference numerals:

10: a controller;

20: a semiconductor memory;

21: a parallel-to-serial conversion circuit;

22: a data buffer module;

23: a DBI encoding module;

24: a DQ port;

25: a DBI port;

26: a storage block;

27: a pre-charge module;

221: a PMOS tube;

222: an NMOS tube;

223: a holding circuit;

231: a DBI encoding unit;

232: a data selector;

232': a data selection unit;

232A: a first inverter;

232B: a second inverter;

232C: a first transmission gate;

232D: a second transmission gate;

232E: a third inverter;

232F: a fourth inverter;

232G: a first logical AND gate;

232F: a second logical AND gate;

232K: a logic or gate.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.

Fig. 1 schematically shows a block diagram of a structure of a semiconductor memory portion of one embodiment of the present embodiment. As shown in fig. 1, the semiconductor memory 20 includes a DQ port 24, a Data Bus Inversion (DBI) port 25, a memory block (Bank)26, and a read operation circuit. The read operation circuit includes a Global Bus (Global Bus), a DBI signal line, a parallel-to-serial conversion circuit 21, a Data Buffer module (Data Buffer)22, and a DBI encoding module (Encoder) 23. In one embodiment, the semiconductor memory 20 is a DRAM, such as a fourth generation Double Data Rate SDRAM (DDR 4).

In one example, as shown in FIG. 1, a one-time Active command opens a uniquely specified memory block 26, and a read operation can only be performed for one memory block 26. That is, when one Bank among the eight memory blocks 26 (i.e., Bank <7:0>) is active, the other banks are inactive. Through the read operation circuit, the read data D <127:0> in the memory block 26 outputs 8-bit output data DQ <7:0> through the DQ port 24. It should be noted that the number of memory blocks 26, the number of data bits per memory block 26, and the number and number of data bits of the DQ port 24 are not limited in this embodiment. For example: one DQ port 24 may be used to output 16-bit output data; the DQ ports 24 may also be two, i.e. each DQ port 24 is used to output 8 bits of output data.

For example, as shown in FIG. 2, the output data DQ <7:0> is obtained by performing a read operation on a set of memory blocks Bank <7:0> by one of the read operation circuits described above; the output data DQ <15:8> is obtained by performing a read operation on another set of memory blocks Bank <15:8> by another read operation circuit as described above. Accordingly, of the eight memory blocks 26 corresponding to DQ <15:8> (i.e., Bank <15:8>), when one Bank is active, the other Bank is inactive.

The semiconductor memory 20 has an array structure, and each unit structure may be the same, but the data output from each unit may be different due to the difference in the input data. The following describes the read operation circuit of this embodiment by taking one of the memory blocks as an example.

The DBI encoding module 23 is connected to the memory block 26, and is configured to read out read data, such as D <127:0>, from the memory block 26, and determine whether to invert the read data according to the number of bits of data that is high in the read data, so as to output global bus data for global bus transmission and DBI data for DBI signal line transmission. Where data high may be data equal to "1" and data low may be data equal to "0". The flipping of data may be understood as a change from "0" to "1", or, from "1" to "0". The inversion of the data line or the signal line may be understood as a high level to a low level, or a low level to a high level.

In one embodiment, the DBI encoding module 23 is configured to output the inverted data of the read data as global bus data and set the DBI data high when the bit number of the data that is high in the read data is greater than a preset value; and under the condition that the bit number of the data which is high in the read data is less than or equal to a preset value, outputting the original read data as global bus data, and setting the DBI data to be low.

In one example, the multi-bit read data is not grouped, i.e., the DBI data may be one bit, and the DBI data output from the DBI encoding module 23 may be directly output to the DBI port 25 without passing through the parallel-to-serial conversion circuit 21. In one example, the multi-bit read data can be grouped. For example: in one embodiment, the read data and the global bus data are both divided into M groups, the DBI data is M bits, the M bits of DBI data correspond to the M groups of read data one to one, and the M bits of DBI data correspond to the M groups of global bus data one to one, and the parallel-serial conversion circuit 21 is further connected between the DBI encoding module 23 and the DBI port 25, and configured to output the M bits of DBI data to the DBI port after parallel-serial conversion, where M is an integer greater than 1. It should be noted that the parallel-serial conversion circuit 21 may include two parallel-serial conversion modules, which are respectively used for performing parallel-serial conversion on the global bus data and the DBI data, and the embodiment is not limited.

Further, each set of read data may be N bits, where N is an integer greater than 1, and the DBI encoding module 23 is configured to output, as a corresponding set of global bus data, the inverted data of the input set of read data when the bit number of the data that is high in the input set of read data is greater than N/2, and set a bit of DBI data corresponding to the input set of read data to be high; and under the condition that the bit number of data which is high in the input group of read data is less than or equal to N/2, outputting the input group of read data as a corresponding group of global bus data, and setting one bit of DBI data which corresponds to the input group of read data to be low.

For example: the read data D <127:0> are divided into 16 groups of 8 bits, each corresponding to one bit of DBI data. Accordingly, the DBI data is 16 bits, such as DBI <15:0 >. The global bus data D' <127:0> would also be divided into 16 sets accordingly. Each bit of DBI data corresponds to a set of global bus data. For a set of read data D <127:120>, if the number of bits in D <127:120> equal to "1" is greater than 4 bits, the corresponding DBI <15> is 1, and the output set of global bus data D' <120:127> is equal to the flip data of D <127:120 >; if the number of bits in the read data equal to "1" is less than or equal to 4 bits, the corresponding DBI <15> is 0, and the output group of global bus data D' <120:127> is D <127:120 >.

Then, when DBI <15> is 1, the global bus data D' <127 output from the DBI encoding module 23: 120> is the inverse of the read data D <127:120> of memory block 26 (e.g., Bank 0); when DBI <15> -0, the global bus data D' <127 output from the DBI encoding module 23: 120> is the read data D <127:120> of the memory block 26 (e.g., Bank0), i.e., the read data D' <127:120> -D <127:120 >. Similarly, when DBI <1> is 1, the global bus data D' <15:8> output from the DBI encoding module 23 is the inverse data of the read data D <15:8> of the storage block 26 (e.g., Bank 0); when DBI <1> -0, the global bus data D '< 15:8> output from the DBI encoding module 23 is the read data D <15:8> of the storage block 26 (e.g., Bank0), i.e., the global bus data D' <15:8> -D <15:8 >. When DBI <0> -1, the global bus data D' <7:0> output from the DBI encoding module 23 is the inverse data of the read data D <7:0> of the storage block 26 (e.g., Bank 0); when DBI <0> -0, the global bus data D' <7 output from the DBI encoding module 23: i.e., 0> is the read data D <7:0> of the memory block 26 (e.g., Bank0), i.e., the global bus data D' <7:0> -D <7:0 >.

In one example, the global bus is multi-root and is divided into M groups (M is an integer greater than 1), each global bus transferring one bit of global bus data. For example: the number of the global buses is 128, and the 128 global buses are divided into 16 groups. Global bus <0> transfers global bus data D' <0 >; global bus <1> transfers global bus data D' <1 >; … …, respectively; global bus <127> transfers global bus data D' <127 >.

In one example, the number of DBI signal lines is 16, each DBI signal line transmits 1-bit DBI data, such as DBI signal line <0> transmitting DBI data DBI <0>, and corresponding to global bus data D '< 7:0>, indicating whether D' <7:0> is inverted data; the DBI signal line <1> transmits DBI data DBI <1> and represents whether D '< 15:8> is inverted data or not corresponding to global bus data D' <15:8 >; … …, respectively; the DBI signal line <15> transmits DBI data DBI <15> and, corresponding to global bus data D '< 127:120>, characterizes whether D' <127:120> is inverted data.

The parallel-serial conversion circuit 21 is connected between the DQ port 24 and the DBI encoding module 23 through a global bus, and is configured to perform parallel-serial conversion on global bus data to generate output data of the DQ port 24. For example: the parallel-serial conversion circuit 21 performs parallel-serial conversion on the 128-bit global bus data D' <127:0> of Bank0, thereby generating 8-bit output data DQ <7:0> and transmitting the output data DQ to the DQ port 24 via a data bus (data bus). Accordingly, the global bus data D' <127:0> transmitted on the global bus has more data "0". Accordingly, in the semiconductor memory 20 shown in fig. 2, of the 256-bit global bus data (including 128-bit global bus data corresponding to DQ <7:0> and 128-bit global bus data corresponding to DQ <15:8>), there is a large amount of data of "0".

The data buffer block 22 is connected to the memory block 26 through a global bus, and the Precharge block 27 is connected to a Precharge signal line (Precharge) for setting an initial state of the global bus to low. That is, in the present embodiment, the semiconductor memory 20 employs a Precharge pull-down global bus transfer structure.

Fig. 3 schematically shows a circuit diagram (corresponding to one memory block 26) of the data buffer block 22 and the precharge block 27 of one embodiment of the present embodiment. Fig. 4 schematically shows a circuit diagram (corresponding to 8 memory blocks 26) of the data buffer block 22 and the precharge block 27 of one embodiment of the present embodiment.

As shown in fig. 3 and 4, the data buffer module 22 includes a plurality of pmos (positive Channel metal oxide semiconductor) transistors 221, and the precharge module 27 includes a plurality of nmos (negative Channel metal oxide semiconductor) transistors 222 and a plurality of hold (hold) circuits 223. Wherein, the gate of the PMOS transistor 221 is connected to the memory block 26, and the drain of the PMOS transistor 221 is connected to the global bus; the gate of the NMOS transistor 222 is connected to the precharge signal line, and the drain of the NMOS transistor 222 is connected to the global bus; the input and output terminals of the hold circuit 223 are connected to the global bus, thereby forming a positive feedback circuit.

The Precharge is used for setting the initial state of each global bus to be low, specifically, the Precharge generates a pull-down pulse (pulse, about 2 ns), a certain corresponding global bus is pulled down for a while, the holding circuit 223 forms positive feedback and locks the global bus at a low level, but the pull-up and pull-down current capability of the holding circuit 223 is relatively weak; when a global bus needs to be changed to a high level, the data line corresponding to the global bus (i.e., the data line connected to the gate of the corresponding PMOS transistor 221) is pulled down (also a pulse, about 2 ns), so that the corresponding PMOS transistor 221 pulls up the global bus for a moment (the pull-up capability is greater than the pull-down capability of the holding circuit 223), and then locks the global bus to the high level through positive feedback, thereby completing the flipping operation of the data line. Since the global bus data D' <127:0> includes a large amount of data "0", the number of flip operations required is small. Therefore, IDD4R (sense current) of the semiconductor memory will be reduced, so that the power consumption of the semiconductor memory can be reduced.

The function of the DBI port 25 is described below in connection with fig. 5. The data output from the semiconductor memory 20 includes DBI data of the DBI port 25 and output data of the DQ port 24. When the DBI data of the DBI port 25 is equal to 1, the output data such as DQ <7:0> needs to be inverted and then is output to the controller 10; when the DBI data of the DBI port 25 is equal to 0, the original output data may be directly transmitted to the controller 10. An On-Die Termination (ODT) of the semiconductor memory 20 may sink current away from the DQ port 24, preventing signals from forming reflections On internal circuitry of the semiconductor memory 20. The ODT is sized to match the controller 10 during operation of the semiconductor memory 20. In one example, the ODT structure is a pull-down structure, and when the data on DQ port 24 is a "1" (i.e., high), the leakage current through the ODT is larger, which increases power consumption. In the present embodiment, since the data of "0" is more of the output data of the DQ port 24, the power consumption of the semiconductor memory can be further reduced.

Whereas in the related art, in the case where the DBI function is enabled, when the semiconductor memory is performing a read operation, the module for inverting and encoding data is disposed at a position where the data is faster out of the semiconductor memory, i.e., after the module for parallel-to-serial conversion. Therefore, in the related art, the number of data "1" transmitted by the internal global bus of the semiconductor memory is large, which results in an excessively large IDD4R and high power consumption.

According to the semiconductor memory 20 of the present embodiment, in the process of reading data from the semiconductor memory 20, when the global bus data is 256 bits, the 256-bit global bus data needs to be inverted, so that only the 32-bit DBI data is inverted, and the current of the IDD4R is greatly compressed.

In one embodiment, as shown in fig. 6, the DBI encoding module 23 includes a DBI encoding unit 231 and a data selector 232.

An input terminal of the DBI encoding unit 231 is connected to the memory block 26 through a local Bus (local Bus), and an output terminal of the DBI encoding unit 231 is connected to a DBI signal line and to an input terminal of the data selector 232. The DBI coding unit is used for setting the DBI data to be high under the condition that the bit number of the data which is high in the read data is larger than a preset value; and setting the DBI data to be low under the condition that the bit number of the data which is high in the read data is less than or equal to a preset value.

In one example, the DBI encoding unit 231 may include a plurality of DBI encoding sub-units, each for processing a set of read data to output one bit of DBI data. For example: the number of the data selection units DBI coding subunits may be 16, which respectively correspond to 16 groups of read data, and further output 16-bit DBI data, wherein each group of read data may have 8 bits.

An input terminal of the data selector 232 is connected to the DBI encoding unit 231 for receiving the read data through the DBI encoding unit 231, an input terminal of the data selector 232 also receives the DBI data through a DBI signal line, and an output terminal of the data selector 232 is connected to the parallel-to-serial conversion circuit 21 through a global bus. The data selector 232 is configured to output the inverted data of the read data as global bus data when the DBI data is high; and outputting the original read data as global bus data if the DBI data is high.

In one embodiment, the data selector 232 includes a plurality of data selection units 232 ', each data selection unit 232' for processing one bit of DBI data and a set of read data. For example: the number of the data selecting units 232' may be 16, corresponding to 16 sets of read data and one bit of DBI data, respectively, each set of read data having 8 bits.

Fig. 7-1 and 7-2 show two different implementations of the data selection unit 232'.

As shown in fig. 7-1, the data selection unit 232' includes a first inverter 232A, a second inverter 232B, a first transmission gate 232C, and a second transmission gate 232D. The input of the first inverter 232A receives DBI data through the DBI signal line; an input end of the second inverter 232B is connected to the DBI encoding unit 231 for receiving the read data from the DBI encoding unit 231; an input end of the first transmission gate 232C is connected to an output end of the second inverter 232B, an output end of the first transmission gate 232C is connected to the global bus for outputting global bus data, an inverted control end (an upper control end in fig. 7-1) of the first transmission gate 232C is connected to an output end of the first inverter 232A, and a positive control end (a lower control end in fig. 7-1) of the first transmission gate 232C receives DBI data through a DBI signal line; an input end of the second transmission gate 232D is connected to the DBI encoding unit 231, and is configured to receive read data from the DBI encoding unit 231, an output end of the second transmission gate 232D is connected to the global bus, and is configured to output global bus data, an inverted control end of the second transmission gate 232D receives DBI data through a DBI signal line, and a positive control end of the second transmission gate 232D is connected to an output end of the first inverter 232A.

Taking DBI <0> and read data D <7:0> as an example, as shown in fig. 7-1, when DBI is 1, the global bus data D' <7:0> is the flip data of the read data D <7:0 >; when DBI is equal to 0, the global bus data D' <7:0> is the read data D <7:0 >.

It should be noted that a set of the second inverter 232B, the first transmission gate 232C and the second transmission gate 232D is used for processing one bit of read data and outputting one bit of corresponding global bus data. That is, corresponding to the 8-bit read data D <7:0>, there should be 8 sets of the second inverter 232A, the first transmission gate 232C and the second transmission gate 232D, and 8 bits of global bus data D <7:0> are outputted.

As shown in fig. 7-2, the data selection unit 232' includes a third inverter 232E, a fourth inverter 232F, a first logic and gate 232G, a second logic and gate 232H, and a logic or gate 232K. The input of the third inverter 232E receives DBI data through the DBI signal line; an input end of the fourth inverter 232F is connected to the DBI encoding unit 231, and is configured to receive read data from the DBI encoding unit 231; a first input end of the first logic and gate 232G is connected to the DBI encoding unit 231 for receiving the read data from the DBI encoding unit 231, and a second input end of the first logic and gate 232G is connected to an output end of the third inverter 232E; a first input end of the second logic and gate 232H receives DBI data through a DBI signal line, and a second input end of the second logic and gate 232H is connected to an output end of the fourth inverter 232F; two input ends of the logic or gate 232K are respectively connected to the output end of the first logic and gate 232G and the output end of the second logic and gate 232H, and the output end of the logic or gate 232K is connected to the global bus for outputting global bus data.

Taking DBI <0> and read data D <7:0> as an example, as shown in fig. 7-2, when DBI is 1, the global bus data D' <7:0> is the flip data of the read data D <7:0 >; when DBI is equal to 0, the global bus data D' <7:0> is the read data D <7:0 >.

It should be noted that a group of the fourth inverter 232F, the first logic and gate 232G, the second logic and gate 232H, and the logic or gate 232K is used for processing one bit of read data and outputting one bit of corresponding global bus data. That is, corresponding to the 8 bits of read data D <7:0>, there should be 8 sets of the third inverter 232E, the fourth inverter 232F, the first and gate 232G, the second and gate 232H and the or gate 232K, and then 8 bits of global bus data D <7:0> are output.

In practical applications, the semiconductor memory 20 of the present embodiment further includes other structures such as a sense amplifier, a precharge circuit, etc., which are all the prior art and are not repeated herein.

The read operation circuit provided by the embodiment of the application is applied to a semiconductor memory with a Precharge pull-down global bus transmission structure, and the DBI coding module is arranged between the parallel-serial conversion circuit and the storage block, so that more data transmitted as '0' on the global bus can be realized, the turnover frequency of the internal global bus is reduced, the current can be greatly compressed, and the power consumption is reduced.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the application.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Furthermore, while the spirit and principles of the application have been described with reference to several particular embodiments, it is to be understood that the application is not limited to the disclosed embodiments, nor is the division of aspects, which is merely for convenience of presentation, to imply that features in these aspects cannot be combined to advantage. The application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present application, and these should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (9)

1. A read operation circuit applied to a semiconductor memory, wherein the semiconductor memory comprises a DQ port, a DBI port and a memory block, the read operation circuit comprising:

the DBI coding module is connected with the storage block and used for reading out read data from the storage block and determining whether the read data is inverted or not according to the high data bit number in the read data so as to output global bus data for global bus transmission and DBI data for DBI signal line transmission, and the DBI port is used for receiving the DBI data;

the parallel-serial conversion circuit is connected between the DQ port and the DBI coding module through the global bus and used for carrying out parallel-serial conversion on global bus data to generate output data of the DQ port;

the data buffer module is connected to the storage block through the global bus;

the pre-charging module is connected to a pre-charging signal line and used for setting the initial state of the global bus to be low, and comprises a plurality of NMOS transistors, wherein the grid electrodes of the NMOS transistors are connected to the pre-charging signal line, and the drain electrodes of the NMOS transistors are connected to the global bus.

2. The read operation circuit of claim 1, wherein the DBI encoding module is further configured to input a preset value, and output the DBI data and the global bus data according to a number of bits of data that is high in the read data and the preset value.

3. The circuit of claim 1, wherein the read data and the global bus data are divided into M groups, the DBI data are M bits, M bits of DBI data correspond to M groups of read data one to one, and M bits of DBI data correspond to M groups of global bus data one to one, the parallel-serial conversion circuit is further connected between the DBI encoding module and the DBI port, and configured to output the M bits of DBI data to the DBI port after parallel-serial conversion, where M is an integer greater than 1.

4. The circuit of claim 3, wherein each set of read data is N bits, where N is an integer greater than 1, and the DBI coding module is configured to output a corresponding one-bit DBI data and a corresponding set of global bus data according to a relationship between a number of bits of data that is high in the input set of read data and N/2.

5. The read operation circuit of claim 1, wherein the DBI encoding module comprises:

the input end of the DBI coding unit is connected to the storage block, the output end of the DBI coding unit is connected with the DBI signal line, the DBI coding unit is used for inputting a preset value and outputting DBI data according to the number of bits of high data in the read data and the preset value;

the input end of the data selector is connected to the DBI coding unit and used for receiving the read data through the DBI coding unit, the input end of the data selector also receives the DBI data through the DBI signal line, the output end of the data selector is connected to the parallel-serial conversion circuit through the global bus, and the data selector is used for outputting the global bus data according to the DBI data and the read data.

6. The read operation circuit of claim 5, wherein the data selector comprises a plurality of data selection units, the data selection units comprising:

a first inverter, an input of which receives the DBI data through the DBI signal line;

the input end of the second inverter is connected to the DBI coding unit and used for receiving the read data from the DBI coding unit;

a first transmission gate, an input end of which is connected to an output end of the second inverter, an output end of which is connected to the global bus and is configured to output the global bus data, an inverted control end of which is connected to an output end of the first inverter, and an positive control end of which receives the DBI data through the DBI signal line;

and the input end of the second transmission gate is connected to the DBI coding unit and used for receiving the read data from the DBI coding unit, the output end of the second transmission gate is connected with the global bus and used for outputting the global bus data, the inverse control end of the second transmission gate receives the DBI data through the DBI signal line, and the positive control end of the second transmission gate is connected to the output end of the first phase inverter.

7. The read operation circuit of claim 5, wherein the data selector comprises a plurality of data selection units, the data selection units comprising:

a third inverter, an input of which receives the DBI data through the DBI signal line;

the input end of the fourth inverter is connected to the DBI coding unit and used for receiving the read data from the DBI coding unit;

a first logic and gate, a first input end of which is connected to the DBI encoding unit, and configured to receive the read data from the DBI encoding unit, and a second input end of which is connected to an output end of the third inverter;

a second logic and gate, a first input end of the second logic and gate receiving the DBI data through the DBI signal line, a second input end of the second logic and gate being connected to an output end of the fourth inverter;

and two input ends of the logic OR gate are respectively connected to the output end of the first logic AND gate and the output end of the second logic AND gate, and the output end of the logic OR gate is connected with the global bus and used for outputting the global bus data.

8. The read operation circuit according to any one of claims 1 to 7, wherein the data buffer module comprises a plurality of PMOS transistors, gates of the PMOS transistors are connected to the memory blocks, and drains of the PMOS transistors are connected to the global bus; and the pre-charge module further comprises a plurality of holding circuits, the inputs and outputs of the holding circuits being connected to the global bus.

9. A semiconductor memory characterized by comprising a DQ port, a DBI port, a memory block, and the read operation circuit according to any one of claims 1 to 8.

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