CN211266757U - Power isolation circuit and intelligent door lock system - Google Patents
Power isolation circuit and intelligent door lock system Download PDFInfo
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- CN211266757U CN211266757U CN201922068933.5U CN201922068933U CN211266757U CN 211266757 U CN211266757 U CN 211266757U CN 201922068933 U CN201922068933 U CN 201922068933U CN 211266757 U CN211266757 U CN 211266757U
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Abstract
The embodiment of the application provides a power isolation circuit and an intelligent door lock system, and relates to the field of electronic equipment, wherein the power isolation circuit comprises an MOS (metal oxide semiconductor) tube switching circuit, a first end of the MOS tube switching circuit is used for being electrically connected with a first power supply, and a second end of the MOS tube switching circuit is respectively used for being connected with a second power supply and equipment to be powered; and the control circuit is electrically connected with the second power supply, is electrically connected with the MOS tube switching circuit, and is used for controlling the on/off of the MOS tube switching circuit according to the output voltage of the second power supply so as to isolate the first power supply when the second power supply supplies power to the equipment to be powered. This application can effectively keep apart first power when treating power supply unit switching second power, has prevented to appear between first power and the second power that anti-charging to the security of treating the power supply unit power supply improves.
Description
Technical Field
The application relates to the technical field of electronic equipment, in particular to a power isolation circuit and an intelligent door lock system.
Background
With the rapid development of science and technology, more and more electronic devices enter people's lives. At present, most electronic devices, especially electronic devices with low power consumption, can usually supply power by multiple power sources, so that users can use the electronic devices conveniently.
However, when the electronic device is powered by multiple power sources, the power source voltage of each power source is different, and the low-voltage power source is often charged back by the high-voltage power source, thereby causing damage to the low-voltage power source.
SUMMERY OF THE UTILITY MODEL
An object of this application is to provide a power isolation circuit and intelligent lock system, not only can avoid because the different production electric currents of multichannel power electric potential flow backward, guaranteed the security that electronic equipment charges, can also reduce the loss in the circuit.
In a first aspect, an embodiment of the present application provides a power isolation circuit, including: the power supply comprises an MOS tube switching circuit and a control circuit, wherein a first end of the MOS tube switching circuit is electrically connected with a first power supply, and a second end of the MOS tube switching circuit is respectively connected with a second power supply and equipment to be powered; the control circuit is used for being electrically connected with the second power supply, is electrically connected with the MOS tube switching circuit and is used for controlling the on-off of the MOS tube switching circuit according to the output voltage of the second power supply so as to isolate the first power supply when the second power supply supplies power to the equipment to be powered.
Further, the MOS transistor switch circuit comprises: the power supply device comprises a first MOS tube, wherein the input end of the first MOS tube is electrically connected with a first power supply, and the output end of the first MOS tube is electrically connected with a second power supply and a device to be powered respectively. In addition, the first end of the control circuit is used for connecting a second power supply, the second end of the control circuit is electrically connected with the control end of the first MOS tube and is used for controlling the first MOS tube to be switched on or switched off according to the output voltage of the second power supply so as to isolate the first power supply from the second power supply when the second power supply supplies power to the equipment to be powered.
Further, the control circuit comprises a first control unit and a first resistor for limiting current; the first end of the first resistor is used for being electrically connected with a second power supply; the second end of the first resistor is electrically connected with the control end of the first MOS tube through the first control unit.
Further, the first control unit comprises a first triode, a second resistor, a third resistor and a fourth resistor; the base electrode of the first triode is electrically connected with the second end of the first resistor; a collector of the first triode is respectively and electrically connected with a first end of the second resistor and a first end of the third resistor, a second end of the second resistor is used for being electrically connected with the first power supply, and a second end of the third resistor is electrically connected with a base of the second triode; the emitter of the first triode is grounded; an emitter of the second triode is electrically connected with the input end of the first MOS tube and the second end of the second resistor respectively; the collector of the second triode is respectively and electrically connected with the control end of the first MOS tube and the first end of the fourth resistor, and the second end of the fourth resistor is grounded.
Further, the MOS tube switching circuit also comprises a second MOS tube. The input end of the second MOS tube is electrically connected with the output end of the first MOS tube, the output end of the second MOS tube is used for respectively electrically connecting a second power supply and the equipment to be powered, and the parasitic diode of the second MOS tube is opposite to the parasitic diode of the first MOS tube in direction. In addition, the third end of the control circuit is electrically connected with the control end of the second MOS transistor and is further used for controlling the second MOS transistor to be turned on or off according to the output voltage of the second power supply so as to isolate the first power supply from the second power supply when the second power supply supplies power to the equipment to be powered.
Further, the control circuit further includes: the second control unit comprises a third triode, a fourth triode, a fifth resistor, a sixth resistor and a seventh resistor; the base of the third triode is electrically connected with the second end of the first resistor; a collector of the third triode is respectively and electrically connected with a first end of a fifth resistor and a first end of a sixth resistor, a second end of the fifth resistor is used for electrically connecting equipment to be powered, and a second end of the sixth resistor is electrically connected with a base of the fourth triode; the emitter of the third triode is grounded; an emitter of the fourth triode is electrically connected with the output end of the second MOS tube and the second end of the fifth resistor R5 respectively; and the collector of the fourth triode is respectively and electrically connected with the control end of the second MOS tube and the first end of the seventh resistor, and the second end of the seventh resistor is grounded.
Further, the power isolation circuit further includes: a delay circuit. The output end of the delay circuit is electrically connected with the second end of the MOS tube switch circuit and the equipment to be powered respectively, and the output end of the delay circuit is used for delaying electric energy output by the second power supply to the equipment to be powered when the input end of the delay circuit is connected with the second power supply.
Further, the delay circuit includes: the third MOS tube, an eighth resistor, a ninth resistor and a buffer capacitor. The output end of the third MOS tube is electrically connected with the equipment to be powered, the output end of the third MOS tube is electrically connected with the second end of the MOS tube switching circuit, and the input end of the third MOS tube is electrically connected with the first end of the buffer capacitor; the control end of the third MOS tube is electrically connected with the second end of the buffer capacitor; the first end of the buffer capacitor is also electrically connected with the first end of the eighth resistor, and the second end of the buffer capacitor is also electrically connected with the second end of the eighth resistor; the first end of the eighth resistor is further used for electrically connecting a second power supply, and the second end of the eighth resistor is further grounded through a ninth resistor.
Furthermore, the time delay circuit further comprises an anti-reverse diode, the anode of the anti-reverse diode is electrically connected with the output end of the third MOS tube, the cathode of the anti-reverse diode is electrically connected with the second end of the MOS tube switch circuit, and the cathode of the anti-reverse diode is also electrically connected with the equipment to be powered.
In a second aspect, an embodiment of the present application provides an intelligent door lock system, which includes an intelligent door lock and the power isolation circuit of the first aspect, wherein the intelligent door lock is electrically connected to the power isolation circuit.
The application provides a power isolation circuit and intelligent lock system, through setting up MOS pipe switch circuit and with MOS pipe switch circuit electric connection's control circuit, and MOS pipe switch circuit's first end is used for the first power of electric connection, the second end is used for electric connection second power respectively and treats power supply unit, thereby can utilize the characteristic of MOS pipe to keep apart first power and second power, not only have better isolation effect, produce great energy consumption when having avoided keeping apart moreover. The control circuit is used for electrically connecting the second power supply, so that the control circuit can control the on and off of the MOS tube switching circuit according to the output voltage of the second power supply, and when the second power supply supplies power to the equipment to be powered, the control circuit controls the MOS tube switching circuit to be off so as to isolate the first power supply, thereby preventing the reverse charging condition between the second power supply and the first power supply and ensuring the safety of power supply. And the power supply is isolated by controlling the MOS tube switching circuit, so that the manufacturing cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a functional block diagram of a power isolation circuit provided by one embodiment of the present application;
FIG. 2 is a circuit schematic of a power isolation circuit provided by one embodiment of the present application;
FIG. 3 is a circuit schematic of a power isolation circuit provided in another embodiment of the present application;
fig. 4 is a schematic structural diagram of an intelligent door lock system according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it is noted that the terms "first", "second", "third", and the like are used merely for distinguishing between descriptions and are not intended to indicate or imply relative importance.
In the description of the present application, it is further noted that, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Along with the development of science and technology, more and more electronic product's volume becomes littleer and more, in order to make things convenient for the user to carry and practical, these electronic product often all are low-power consumption products, in order to guarantee that low-power consumption product can charge anytime and anywhere, current low-power consumption product often has the application scene of multichannel power supply, for example, most intelligent lock all uses the battery power supply at present, need change new battery when the battery does not have the electricity at every turn, and in view of pleasing to the eye and the safety consideration to intelligent lock, the place of the change battery of intelligent lock usually can set up indoor, in order to prevent that intelligent lock can't unblank because of the battery does not have the electricity, then can set up a Universal Serial Bus (Universal Serial Bus, USB) interface that charges for intelligent lock so that intelligent lock can promptly supply power.
However, when the electronic device is powered by multiple power sources, the power source voltage of each power source is different, and the low-voltage power source is often charged back by the high-voltage power source, thereby causing damage to the low-voltage power source. For example, when the intelligent door lock uses the USB interface to supply power, if the supply voltage of the USB interface is greater than the voltage of the battery, the battery of the intelligent door lock is reversely charged, thereby damaging the battery.
The inventor finds in research that if when one of the multiple power supplies power to the electronic equipment, the other power supplies except the one power supply are isolated, the situation of reverse charging in the multiple power supplies can be prevented. The inventor finds that diodes can be respectively arranged at the output ends of the power supplies, so that the multiple power supplies can be effectively isolated, for example, the diodes are arranged at the output ends of the batteries, and the diodes are arranged at the output ends of the USB, so that the isolation between the batteries and the USB power supplies can be realized.
However, the voltage drop of the diode is very large, so that large energy loss can be caused during power supply, the diode is heated seriously and is easy to damage, and the power supply stability of the power supply is influenced.
Therefore, the inventor thinks that the isolation between the two power supplies can be controlled by a logic control circuit formed by a control Unit (MCU), two DC/DC circuits and a delay module, the MCU collects the battery voltage and the USB power supply voltage through the two DC/DC circuits, respectively, and controls the delay circuit to isolate the two power supplies according to the collected battery voltage and the USB power supply voltage, so as to implement power isolation and system restart. But the method is too high in cost and not easy to popularize.
Therefore, in view of the above problems, the inventor proposes the power isolation circuit and the intelligent door lock system in the embodiment of the present application.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 shows that the embodiment of the present application provides a power isolation circuit, where the power isolation circuit 100 may include:
the power supply device comprises a MOS transistor switch circuit 110 and a control circuit 120, wherein a first end of the MOS transistor switch circuit 110 is electrically connected to a first power source 140, and a second end of the MOS transistor switch circuit 110 is electrically connected to a second power source 150 and a device to be powered 160. The control circuit 120 is electrically connected to the second power source 150, and the control circuit 120 is electrically connected to the MOS transistor switch circuit 110, and is configured to control the MOS transistor switch circuit 110 to be turned on or off according to the output voltage of the second power source 150, so as to isolate the first power source 140 when the second power source 150 supplies power to the device to be powered 160.
The MOS switch circuit 110 may be mainly composed of one or more MOS transistors, and the on or off of the one or more MOS transistors determines the on or off of the MOS switch circuit 110. The control circuit 120 is configured to control a voltage of a control terminal (a gate of the MOS transistor) of the one or more MOS transistors according to the output voltage of the second power supply 150, so as to control the MOS transistor switch circuit 110 to be turned on or off.
As an example, a first terminal of the MOS transistor switch circuit 110 is electrically connected to the first power source 140, for example, when the MOS transistor switch circuit 110 is a MOS transistor, the first terminal (which may be a source) of the MOS transistor is connected to the first power source 140, and a second terminal (which may be a drain) of the MOS transistor switch circuit 110 is electrically connected to the second power source 150 and the device to be powered 160, respectively. The control circuit 120 is connected to the second power source 150 and the MOS transistor switch circuit 110, for example, the control circuit 120 is connected to the second power source 150 and the gate of the MOS transistor.
When the first power source 140 is used to supply power to the device to be powered 160 and the second power source 150 is not used to supply power, the control circuit 120 controls the voltage V between the gate and the source of the MOS transistor in the MOS transistor switch circuit 110 according to the voltage of the second power source 150 being 0VGSSo as to turn on the MOS transistor switch circuit 110, and allow the first power source 140 to normally supply power to the device to be powered 160.
When the second power source 150 is used to supply power to the device 160 to be powered, the control circuit 120 controls the voltage V between the gate and the source of the MOS transistor in the MOS transistor switch circuit 110 according to the voltage of the output of the second power source 150 not being 0VGSThe MOS transistor switch circuit 110 is turned off, and the MOS transistor switch circuit 110 is disposed between the first power supply 140 and the second power supply 150, so that the first power supply 140 can be isolated, and the second power supply 150 is prevented from reversely charging the first power supply 140.
It is understood that the output voltage of the second power source 150 may be greater than the output voltage of the first power source 140, or may be less than the output voltage of the first power source 140. When the output voltage of the second power supply 150 is greater than the output voltage of the first power supply 140, the reverse charging of the first power supply 140 by the second power supply 150 may be prevented. When the output voltage of the second power supply 150 is less than the output voltage of the first power supply 140, the first power supply 140 may be prevented from back-charging the second power supply 150.
Alternatively, the device to be powered may be an intelligent door lock, a motor device, an audio playing device, an LED display device, or the like.
In this embodiment, by providing the MOS transistor switch circuit 110 and the control circuit 120 electrically connected to the MOS transistor switch circuit 110, the first end of the MOS transistor switch circuit 110 is electrically connected to the first power source 140, and the second end of the MOS transistor switch circuit 110 is electrically connected to the second power source 150 and the device to be powered 160, respectively, so that the first power source 140 and the second power source 150 can be isolated by using the characteristics of the MOS transistor, which not only has a better isolation effect, but also avoids the generation of larger energy consumption during isolation. The control circuit 120 is electrically connected to the second power source 150 to control the on/off of the MOS transistor switch circuit 110 according to the output voltage of the second power source 150, and when the second power source 150 supplies power to the device to be powered 160, the control circuit 120 controls the MOS transistor switch circuit 110 to be off to isolate the first power source 140, thereby preventing reverse current from occurring between the second power source 150 and the first power source 140, and ensuring the safety of power supply. And the power supply is isolated by controlling the MOS tube switch circuit 110, so that the manufacturing cost is reduced.
In some embodiments, as shown in fig. 2, the MOS transistor switch circuit 110 may include a first MOS transistor Q1; the input end of the first MOS transistor Q1 is used for electrically connecting the first power source 140, and the output end of the first MOS transistor Q1 is used for electrically connecting the second power source 150 and the device to be powered 160, respectively.
The first end of the control circuit 120 is electrically connected to the second power source 150, and the second end is electrically connected to the control end of the first MOS transistor Q1, and is used for controlling the first MOS transistor Q1 to be turned on or off according to the output voltage of the second power source 150, so as to isolate the first power source 140 from the second power source 150 when the second power source 150 supplies power to the device to be powered 160. It can be understood that the control terminal of the first MOS transistor Q1 refers to the gate of the first MOS transistor Q1, also referred to as the G-pole.
As an example, the input terminal of the first MOS transistor Q1 is the source (also referred to as S pole) of the first MOS transistor Q1, and the output terminal of the first MOS transistor Q1 is the drain (also referred to as D pole) of the first MOS transistor Q1. The S pole of the first MOS transistor Q1 is electrically connected to the first power source 140, and the D pole is electrically connected to the second power source 150 and the device to be powered 160, respectively. The first terminal of the control circuit 120 is connected to the second power supply 150 for receiving the output voltage of the second power supply 150, and the second terminal of the control circuit 120 is connected to the G-pole of the first MOS transistor Q1. The first MOS transistor Q1 may be a P-channel MOS transistor.
When the first power source 140 supplies power to the device to be powered 160, and the second power source150 does not supply power to the device to be powered 160, the control circuit 120 controls the voltage V of the G pole and the S pole of the first MOS transistor Q1 according to the voltage output by the second power supply 150 being 0VGSNot 0V, since the first MOS transistor Q1 is a P-channel MOS transistor, the first MOS transistor Q1 is turned on at this time, and the first power supply 140 can supply power to the power supply device normally.
When the second power supply 150 supplies power to the device to be powered 160, the control circuit 120 controls the voltage V of the G pole and the S pole of the first MOS transistor Q1 according to the fact that the voltage output by the second power supply 150 is not 0VGSAt 0V, the first MOS transistor Q1 is turned off due to the characteristics of the P-channel MOS transistor, thereby isolating the first power supply 140 from the second power supply 150.
In this embodiment, the first MOS transistor Q1 is used as the MOS transistor switch circuit 110, and the S pole and the D pole of the first MOS transistor Q1 are respectively connected to the first power supply 140 and the second power supply 150, so that not only can the stable power supply of the first power supply 140 to the device to be powered be ensured, but also the first power supply 140 and the second power supply 150 can be effectively isolated by controlling the cutoff of the first MOS transistor Q1, thereby simplifying the structure of the MOS transistor switch circuit 110 and reducing the manufacturing cost.
In some embodiments, the control circuit 120 includes a first control unit 121 and a first resistor R1 for limiting current; a first end of the first resistor R1 is electrically connected to the second power source 150; a second end of the first resistor R1 is electrically connected to the control end of the first MOS transistor Q1 through the first control unit 121.
In practical applications, when the first power source 140 supplies power to the device to be powered 160, no current enters the second power source 150, at this time, the input terminal of the first control unit 121 may be pulled down to ground through the first resistor R1 to obtain a control signal at the input terminal of the first control unit 121, and according to the control signal, the control terminal voltage of the first MOS transistor Q1 may be controlled not to be 0V, so as to control the first MOS transistor Q1 to be turned on, so as to ensure stable power supply of the device to be powered 160 by the first power source 140. When the second power supply 150 supplies power to the device to be powered 160, a current of the second power supply 150 may enter the device to be powered 160 on one hand, and may enter the input terminal of the first control unit 121 through the first resistor R1 on the other hand, so that the first control unit 121 controls the first MOS transistor Q1 to be turned off, thereby isolating the first power supply 140. In the isolation process, the first resistor R1 may limit the current entering the input terminal of the first control unit 121, so as to protect the first control unit 121 and prevent the first control unit 121 from being damaged due to the excessive current entering the first control unit 121.
In some embodiments, the first control unit 121 includes a first transistor Q3, a second transistor Q4, a second resistor R2, a third resistor R3, and a fourth resistor R4.
The base of the first transistor Q3 is electrically connected to the second end of the first resistor R1. The collector of the first transistor Q3 is electrically connected to the first end of the second resistor R2 and the first end of the third resistor R3, respectively, the second end of the second resistor R2 is electrically connected to the input end of the first MOS transistor Q1 and is used for electrically connecting the first power source 140, and the second end of the third resistor R3 is electrically connected to the base of the second transistor Q4. The emitter of the first transistor Q3 is grounded.
The emitter of the second transistor Q4 is electrically connected to the input of the first MOS transistor Q1. The collector of the second transistor Q4 is electrically connected to the control terminal of the first MOS transistor Q1 and the first terminal of the fourth resistor R4, respectively, and the second terminal of the fourth resistor R4 is grounded.
Optionally, the first transistor Q3 is an NPN type transistor, and the second transistor Q4 is a PNP type transistor.
As an example, assume that the device to be powered 160 is a smart door lock, the first power source 140 is a battery, and the second power source 150 is a USB power source. When the intelligent door lock normally works, the battery supplies power to the intelligent door lock, and the USB interface of the intelligent door lock is not connected with a USB power supply. At this time, the base of the first triode Q3 is pulled down to ground through the first resistor R1, so that the collector and emitter of the first triode Q3 are not conducted. The base of the second transistor Q4 is then pulled up to the first power source 140 through the third resistor R3 and the second resistor R2, so that the collector and emitter of the second transistor Q4 are also not connected. Therefore, the G pole of the first MOS transistor Q1 is pulled down to the ground through the fourth resistor R4, which causes the first MOS transistor Q1 to be turned on, and the current of the first power source 140 can normally enter the device to be powered 160 to normally power the smart door lock.
When the battery is powered abnormally, the second power supply 150, namely the USB power supply, can be connected to the USB interface of the intelligent door lock, at this time, the current of the USB power supply enters the base of the first triode Q3 through the first resistor R1, so that the collector and the emitter of the first triode Q3 are connected, and the base of the second triode Q4 is pulled down to the ground through the third resistor R3, thereby realizing the connection of the second triode Q4, after the second triode Q4 is connected, the S pole and the G pole of the first MOS tube Q1 are equivalent to a short circuit, at this time, the first MOS tube Q1 is cut off, the first power supply 140 is isolated from the belt power supply device and the second power supply 150, and the USB power supply is used for supplying power to the device to be powered independently.
In this embodiment, the first control unit 121 is formed by the first transistor Q3, the second transistor Q4, the second resistor R2, the third resistor R3 and the fourth resistor R4, and the first transistor Q3 and the second transistor Q4 are turned on and off to control the on and off of the first MOS transistor, so that the first power supply 140 can be effectively prevented from generating a large leakage current when the second power supply 150 supplies power in an emergency.
In some embodiments, as shown in fig. 3, the MOS transistor switch circuit 110 further includes a second MOS transistor Q2.
The input end of the second MOS transistor Q2 is electrically connected to the output end of the first MOS transistor Q1, and the output end of the second MOS transistor Q2 is electrically connected to the second power source 150 and the device to be powered 160, respectively, wherein the parasitic diode of the second MOS transistor Q2 is opposite to the parasitic diode of the first MOS transistor Q1.
The third terminal of the control circuit 120 is electrically connected to the control terminal of the second MOS transistor Q2, and is further configured to control the second MOS transistor Q2 to be turned on or off according to the output voltage of the second power source 150, so as to isolate the first power source 140 from the second power source 150 when the second power source 150 supplies power to the device to be powered 160.
In practical applications, an input terminal of the first MOS transistor Q1 is connected to the first power supply 140, an output terminal of the first MOS transistor Q1 is connected to an input terminal of the second MOS transistor Q2, and an output terminal of the second MOS transistor Q2 is connected to the device to be powered 160. The control circuit 120 is respectively connected to the control terminal of the first MOS transistor Q1 and the control terminal of the second MOS transistor Q2, wherein the second terminal of the control circuit 120 is connected to the control terminal of the first MOS transistor Q1, and the third terminal of the control circuit 120 is connected to the control terminal of the second MOS transistor Q2. Therefore, the control circuit 120 may simultaneously control the first MOS transistor Q1 and the second MOS transistor Q2 to be turned on or off according to whether the second power source 150 supplies power. When the second power source 150 supplies power, the control circuit 120 controls the first MOS transistor Q1 and the second MOS transistor Q2 to be turned off simultaneously, so that the isolation effect between the first power source 140 and the second power source 150 can be enhanced.
In this embodiment, the MOS switch circuit 110 is formed by the first MOS transistor Q1 and the second MOS transistor Q2, and when the first MOS transistor Q1 and the second MOS transistor Q2 are turned off at the same time, the isolation effect between the first power source 140 and the second power source 150 can be effectively enhanced, so as to ensure the power supply safety of the device to be powered 160. In addition, by arranging the parasitic diode of the second MOS transistor Q2 to be opposite to the parasitic diode of the first MOS transistor Q1, the reverse current between the first power source 140 and the second power source 150 can be further prevented.
In some embodiments, the control circuit 120 further comprises:
the second control unit 122, the second control unit 122 includes a third transistor Q5, a fourth transistor Q6, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7; the base of the third triode Q5 is electrically connected with the second end of the first resistor R1; a collector of the third triode Q5 is electrically connected to a first end of the fifth resistor R5 and a first end of the sixth resistor R6, respectively, a second end of the fifth resistor R5 is electrically connected to an output end of the second MOS transistor Q2, and is used for electrically connecting the second power supply 150 and the device to be powered 160, respectively, and a second end of the sixth resistor R6 is electrically connected to a base of the fourth triode Q6; the emitter of the third transistor Q5 is grounded.
An emitter of the fourth triode Q6 is electrically connected with the output end of the second MOS transistor Q2; a collector of the fourth transistor Q6 is electrically connected to the control terminal of the second MOS transistor Q2 and the first terminal of the seventh resistor R7, respectively, and the second terminal of the seventh resistor R7 is grounded.
Optionally, the third transistor Q5 is an NPN type transistor, and the fourth transistor Q6 is a PNP type transistor.
As an example, assume that the device to be powered 160 is a smart door lock, the first power source 140 is a battery, and the second power source 150 is a USB power source. When the intelligent door lock normally works, the battery supplies power to the intelligent door lock, and the USB interface of the intelligent door lock is not connected with a USB power supply. At this time, the base of the third triode Q5 is pulled down to ground through the first resistor R1, so that the collector and the emitter of the third triode Q5 are not conducted. The base of the fourth transistor Q6 is then pulled up to the first power source 140 through the sixth resistor R6 and the fifth resistor R5, so that the collector and emitter of the fourth transistor Q6 are also not connected. Therefore, the G pole of the second MOS transistor Q2 is pulled down to the ground through the seventh resistor R7, which causes the second MOS transistor Q2 to be turned on, and at this time, the current of the first power source 140 can normally enter the device to be powered 160 to normally power the smart door lock.
When the battery is powered abnormally, the second power supply 150, namely the USB power supply, can be connected to the USB interface of the intelligent door lock, at this time, the current of the USB power supply enters the base of the third triode Q5 through the first resistor R1, so that the collector and the emitter of the third triode Q5 are connected, and the base of the fourth triode Q6 is pulled down to the ground through the seventh resistor R7, thereby realizing the connection of the fourth triode Q6, after the fourth triode Q6 is connected, the S pole and the G pole of the second MOS transistor Q2 are equivalent to a short circuit, at this time, the second MOS transistor Q2 is disconnected, the first power supply 140 is isolated from the belt power supply device and the second power supply 150, and the USB power supply is used for supplying power to the equipment to be powered independently.
In this embodiment, the second control unit 122 is formed by the third transistor Q5, the fourth transistor Q6, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7, and the on/off of the second MOS transistor Q2 is controlled by the on/off of the third transistor Q5 and the fourth transistor Q6, so that the first power supply 140 can be effectively prevented from generating a large leakage current when the second power supply 150 supplies power in an emergency.
In some embodiments, as shown in fig. 3, the power isolation circuit further comprises:
the output end of the delay circuit 130 is electrically connected to the second end of the MOS switch circuit 110 and the device to be powered 160, respectively, and is configured to delay the electric energy output by the second power source 150 to the device to be powered 160 when the input end of the delay circuit 130 is connected to the second power source 150.
Generally, the output terminal of the delay circuit 130 and the second terminal of the MOS transistor switch circuit 110 are connected to the device to be powered 160 through a DC/DC converter to supply power to the device to be powered 160, and an MCU (micro control unit) is disposed in the device to be powered 160. A period of time is set between the time when the second power source 150 is connected to the delay circuit 130 and the time when the power supply device 160 receives the electric energy, and during the period of time, the MCU in the power supply device 160 is powered down, so that the MCU is automatically powered up again after the power down, and the power down restart is realized.
As an example, taking an intelligent door lock as an example, when the power supplied by the first power source 140 (such as a battery) of the intelligent door lock is abnormal, or the system is abnormal. The second power source 150 (such as a USB power source) is connected to supply power, and at this time, the first power source 140 is isolated due to the connection of the second power source 150, and the first power source 140 cannot supply power to the intelligent door lock. The process of switching the smart door lock to the second power source 150 is equivalent to restarting the system. The delay circuit 130 delays the power supply of the second power source 150 to the intelligent door lock, and after a certain time delay, the intelligent door lock receives the current of the second power source 150. Therefore, power is supplied to the intelligent door lock after the intelligent door lock is completely powered down, and the intelligent door lock is prevented from being powered by the second power supply 150 in the moment of power failure so as to cause damage to the intelligent door lock.
In some embodiments, the delay circuit 130 includes: a third MOS transistor Q7, an eighth resistor R8, a ninth resistor R9, and a buffer capacitor C1.
The output end of the third MOS transistor Q7 is used for electrically connecting the device to be powered 160, the output end of the third MOS transistor Q7 is electrically connected to the second end of the MOS transistor switch circuit 110, and the input end of the third MOS transistor Q7 is electrically connected to the first end of the buffer capacitor C1; the control terminal of the third MOS transistor Q7 is electrically connected to the second terminal of the buffer capacitor C1.
The first end of the buffer capacitor C1 is further electrically connected to the first end of the eighth resistor R8, and the second end of the buffer capacitor C1 is further electrically connected to the second end of the eighth resistor R8.
The first end of the eighth resistor R8 is further used for electrically connecting the second power source 150, and the second end of the eighth resistor R8 is further grounded through the ninth resistor R9.
In practical applications, the second power source 150 supplies power to the to-be-powered device 160 and also supplies power to the delay circuit 130, and at the moment when the second power source 150 supplies power, the current of the second power source 150 discharges to the ground through the eighth resistor R8 and the ninth resistor R9. Since the voltage across the buffer capacitor C1 connected in parallel with the eighth resistor R8 cannot suddenly change and the input terminal and the control terminal of the third MOS transistor Q7 are respectively connected to the two terminals of the buffer capacitor C1, the third MOS transistor Q7 cannot be immediately turned on. At this time, the current of the second power source 150 charges the buffer capacitor C1 through the eighth resistor R8, and when the charging voltage across the buffer capacitor C1 slowly rises to reach the threshold voltage of the third MOS transistor Q7, the third MOS transistor Q7 is turned on, and supplies power to the device to be powered. Isolation of the first power source 140 and system restart of the device to be powered 160 are achieved at the same time.
When the second power supply 150 is not supplying power, the first transistor Q3 and the third transistor Q5 may be pulled down to ground through the first resistor R1, the eighth resistor R8, and the ninth resistor R9.
Optionally, the buffer capacitor C1 may be an adjustable capacitor, and the buffer capacitor C1 is set as the adjustable capacitor, so that the capacitance value of the buffer capacitor C1 can be adjusted to determine the time for delaying power supply, thereby improving the flexibility of the delay circuit.
In other embodiments, the delay circuit 130 further includes an anti-reverse diode D1, an anode of the anti-reverse diode D1 is electrically connected to the output terminal of the third MOS transistor Q7, a cathode of the anti-reverse diode D1 is electrically connected to the second terminal of the MOS transistor switch circuit 110, and a cathode of the anti-reverse diode D1 is electrically connected to the device to be powered 160. In this embodiment, an anti-reverse diode is disposed between the device to be powered 160 and the third MOS transistor Q7, so that the device can be effectively prevented from being damaged due to the residual current of the device to be powered 160 flowing back to the third MOS transistor Q7 at the moment of power failure of the second power supply, and the safety of use is improved.
Referring to fig. 4, fig. 4 shows that another intelligent door lock system 20 provided in the embodiment of the present application includes an intelligent door lock 20 and the power isolation circuit 100 of any one of the above embodiments, wherein the intelligent door lock 210 is electrically connected to the power isolation circuit 100.
To sum up, this application embodiment provides power isolation circuit and intelligent lock system, through setting up MOS pipe switch circuit and with MOS pipe switch circuit electric connection's control circuit, and MOS pipe switch circuit's first end is used for the first power of electric connection, the second end is used for electric connection second power respectively and treats power supply unit to the characteristic that can utilize the MOS pipe keeps apart first power and second power, not only has better isolation effect, produces great energy consumption when having avoided keeping apart moreover. The utility model provides an isolating circuit can not produce the electric leakage when first power is normally supplied power, does not have too much energy loss, does not influence the normal work consumption of first power. The control circuit is used for electrically connecting the second power supply, so that the control circuit can control the conduction and the cut-off of the MOS tube switching circuit according to the output voltage of the second power supply, when the second power supply supplies power to the equipment to be powered, the control circuit controls the MOS tube switching circuit to be cut off, so that the first power supply is isolated, the reverse charging condition between the second power supply and the first power supply is prevented, the first power supply and the second power supply are protected, and the power supply safety is guaranteed. And the power supply is isolated by controlling the MOS tube switching circuit, so that the manufacturing cost is reduced. And compared with the method that the MCU and the DC/DC circuit are used for constructing the logic control circuit to isolate the power supply, the circuit can reduce the manufacturing cost. In addition, by arranging the delay circuit, the system of the equipment to be powered can be stably restarted when the power supply is switched, the damage of the equipment caused by electrifying the equipment to be powered when residual current exists is avoided, and the use safety of the equipment is further improved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A power isolation circuit, comprising:
the power supply device comprises a MOS tube switch circuit (110), wherein a first end of the MOS tube switch circuit (110) is electrically connected with a first power supply (140), and a second end of the MOS tube switch circuit (110) is respectively connected with a second power supply (150) and equipment to be powered (160);
the control circuit (120) is electrically connected to the second power supply (150), and the control circuit (120) is electrically connected to the MOS transistor switch circuit (110), and is configured to control on/off of the MOS transistor switch circuit (110) according to an output voltage of the second power supply (150), so as to isolate the first power supply (140) when the second power supply (150) supplies power to the device to be powered (160).
2. The power isolation circuit of claim 1, wherein the MOS transistor switch circuit (110) comprises:
a first MOS transistor (Q1); the input end of the first MOS tube (Q1) is used for being electrically connected with the first power supply (140), and the output end of the first MOS tube (Q1) is used for being electrically connected with the second power supply (150) and the equipment to be powered (160) respectively;
the first end of the control circuit (120) is used for being electrically connected with the second power supply (150), and the second end of the control circuit (120) is electrically connected with the control end of the first MOS transistor (Q1) and used for controlling the first MOS transistor (Q1) to be turned on or off according to the output voltage of the second power supply (150), so that the first power supply (140) is isolated from the second power supply (150) when the second power supply (150) supplies power to the device (160) to be powered.
3. The power isolation circuit of claim 2, wherein the control circuit (120) comprises a first control unit (121) and a first resistor (R1) for limiting current;
the first end of the first resistor (R1) is electrically connected with the second power supply (150); the second end of the first resistor (R1) is electrically connected with the control end of the first MOS transistor (Q1) through a first control unit (121).
4. The power isolation circuit of claim 3, wherein the first control unit (121) comprises a first transistor (Q3), a second transistor (Q4), a second resistor (R2), a third resistor (R3), and a fourth resistor (R4);
the base of the first triode (Q3) is electrically connected with the second end of the first resistor (R1);
the collector of the first triode (Q3) is respectively and electrically connected with the first end of the second resistor (R2) and the first end of a third resistor (R3), the second end of the second resistor (R2) is used for being electrically connected with the first power supply (140), and the second end of the third resistor (R3) is electrically connected with the base of the second triode (Q4);
the emitter of the first triode (Q3) is grounded;
the emitter of the second triode (Q4) is respectively and electrically connected with the input end of the first MOS transistor (Q1) and the second end of the second resistor (R2);
the collector of the second triode (Q4) is respectively and electrically connected with the control end of the first MOS transistor (Q1) and the first end of the fourth resistor (R4), and the second end of the fourth resistor (R4) is grounded.
5. The power isolation circuit of claim 3, wherein the MOS transistor switch circuit (110) further comprises a second MOS transistor (Q2);
the input end of the second MOS tube (Q2) is electrically connected with the output end of the first MOS tube (Q1), and the output end of the second MOS tube (Q2) is used for respectively electrically connecting the second power supply (150) and the equipment (160) to be powered, wherein the parasitic diode of the second MOS tube (Q2) is opposite to the parasitic diode of the first MOS tube (Q1);
the third end of the control circuit (120) is electrically connected to the control end of the second MOS transistor (Q2), and is further configured to control the second MOS transistor (Q2) to be turned on or off according to the output voltage of the second power supply (150), so as to isolate the first power supply (140) from the second power supply (150) when the second power supply (150) supplies power to the device (160) to be powered.
6. The power isolation circuit of claim 5, wherein the control circuit (120) further comprises:
a second control unit (122), the second control unit (122) including a third transistor (Q5), a fourth transistor (Q6), a fifth resistor (R5), a sixth resistor (R6), and a seventh resistor (R7);
the base of the third triode (Q5) is electrically connected with the second end of the first resistor (R1);
a collector of the third triode (Q5) is electrically connected to a first end of the fifth resistor (R5) and a first end of a sixth resistor (R6), respectively, a second end of the fifth resistor (R5) is electrically connected to the device to be powered (160), and a second end of the sixth resistor (R6) is electrically connected to a base of the fourth triode (Q6);
the emitter of the third triode (Q5) is grounded;
an emitter of the fourth triode (Q6) is electrically connected with the output end of the second MOS transistor (Q2) and the second end of the fifth resistor (R5) respectively;
the collector of the fourth triode (Q6) is electrically connected to the control end of the second MOS transistor (Q2) and the first end of the seventh resistor (R7), respectively, and the second end of the seventh resistor (R7) is grounded.
7. The power isolation circuit of any of claims 1-6, further comprising:
and the output end of the delay circuit (130) is respectively electrically connected with the second end of the MOS tube switch circuit (110) and the equipment to be powered (160), and the delay circuit is used for delaying and transmitting the electric energy output by the second power supply (150) to the equipment to be powered (160) when the input end of the delay circuit (130) is connected to the second power supply (150).
8. The power isolation circuit of claim 7, wherein the delay circuit (130) comprises: a third MOS transistor (Q7), an eighth resistor (R8), a ninth resistor (R9) and a buffer capacitor (C1);
the output end of the third MOS transistor (Q7) is used for electrically connecting the device to be powered (160), the output end of the third MOS transistor (Q7) is electrically connected with the second end of the MOS transistor switch circuit (110), and the input end of the third MOS transistor (Q7) is electrically connected with the first end of the buffer capacitor (C1); the control end of the third MOS transistor (Q7) is electrically connected with the second end of the buffer capacitor (C1);
the first end of the buffer capacitor (C1) is electrically connected with the first end of the eighth resistor (R8), and the second end of the buffer capacitor (C1) is electrically connected with the second end of the eighth resistor (R8);
the first end of the eighth resistor (R8) is further used for electrically connecting the second power supply (150), and the second end of the eighth resistor (R8) is further grounded through a ninth resistor (R9).
9. The power isolation circuit of claim 8, wherein the delay circuit (130) further comprises an anti-reverse diode (D1), wherein the anode of the anti-reverse diode (D1) is electrically connected to the output terminal of the third MOS transistor (Q7), the cathode of the anti-reverse diode (D1) is electrically connected to the second terminal of the MOS transistor switch circuit (110), and the cathode of the anti-reverse diode (D1) is further electrically connected to the device to be powered (160).
10. An intelligent door lock system, characterized in that the intelligent door lock system (200) comprises an intelligent door lock (210) and the power isolation circuit (100) according to any one of claims 1-9, wherein the intelligent door lock (210) is electrically connected with the power isolation circuit (100).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922068933.5U CN211266757U (en) | 2019-11-26 | 2019-11-26 | Power isolation circuit and intelligent door lock system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922068933.5U CN211266757U (en) | 2019-11-26 | 2019-11-26 | Power isolation circuit and intelligent door lock system |
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| Publication Number | Publication Date |
|---|---|
| CN211266757U true CN211266757U (en) | 2020-08-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922068933.5U Active CN211266757U (en) | 2019-11-26 | 2019-11-26 | Power isolation circuit and intelligent door lock system |
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| Country | Link |
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| CN (1) | CN211266757U (en) |
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- 2019-11-26 CN CN201922068933.5U patent/CN211266757U/en active Active
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