CN211264189U - Voltage compensation unit, low dropout regulator, control signal generation unit and chip thereof - Google Patents
Voltage compensation unit, low dropout regulator, control signal generation unit and chip thereof Download PDFInfo
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Abstract
The utility model belongs to the integrated circuit field, concretely relates to voltage compensation unit, low dropout linear regulator and control signal generation unit and chip thereof, including four switch module SW11, SW12, SW21 and SW22 and two electric capacity C1, C2, electric capacity C1, C2 all connect in parallel with the power, switch module SW11 connects respectively between electric capacity C1 one end and power positive pole, switch module SW12 connects between electric capacity C1's the other end and power negative pole; the switch module SW21 is connected between one end of the capacitor C1 and one end of the capacitor C2, and the switch module SW22 is connected between the other end of the capacitor C1 and the other end of the capacitor C2. The utility model provides a line resistance consumes greatly among the current low-dropout linear voltage regulator, the technical problem that the power supply voltage difference that leads to load module is little, the utility model discloses can solve line resistance and lead to the problem that the load module voltage difference descends.
Description
Technical Field
The utility model belongs to the integrated circuit field, concretely relates to voltage compensation unit, low dropout linear regulator and control signal generate unit and chip thereof.
Background
A conventional chip internal LDO circuit (low dropout regulator) is shown in fig. 1 and is composed of a bandgap reference voltage source, an amplifier, and an N1 transistor. The N1 transistor is an NMOS transistor driven by the output of LDOThe track width is usually 100um to 1000um, and the load module is a chip internal module with high power consumption. Rvout is the line resistance between the LDO output vout to the load mode. RGNDIs the wiring resistance between the ground pad gnd and the load module.
gnd is the on-chip ground pad and vin is the on-chip input power supply pad. Vout is the output signal of the LDO. vout _ targ is the signal that vout is wired onto the load module. gnd targ is the signal that gnd goes through the wire to the load module.
The bandgap reference voltage is set near the ground pad gnd and provides a stable supply reference signal vref of 1.5V. The amplifier and N1 are disposed near the input power supply pad vin.
When the load module is far away from the ground pad gnd and the input power supply pad vin, the line resistance RGNDAnd Rvout can reach 1 Ω; if the load module consumes much power, for example, Itarg 100mA, the ground voltage gnd targ R of the load moduleGNDItarg ═ 0.1V; the power supply voltage vout _ targ-Rvout × Itarg of the load module is 1.5-1 × 0.1-1.4, so that the power supply voltage difference vout _ targ-gnd _ targ of the load module is 1.4-0.1-1.3V, which is 200mv less than 1.5V of the design standard, and the function and the characteristic of the load module will be seriously affected. As shown in fig. 2:
SUMMERY OF THE UTILITY MODEL
In order to solve the current low dropout linear regulator LDO line resistance consumption big, lead to load module's power supply pressure difference little, load module's function and characteristic receive the technical problem of influence, the utility model provides a voltage compensation unit, low dropout linear regulator and control signal generate unit and chip can solve line resistance and lead to the problem that load module voltage difference descends.
The technical solution of the utility model is as follows:
the utility model provides a voltage compensation unit, its special character lies in: the power supply comprises four switch modules SW11, SW12, SW21, SW22 and two capacitors C1 and C2, wherein the capacitors C1 and C2 are connected with a power supply in parallel, the switch module SW11 is respectively connected between one end of a capacitor C1 and the positive electrode of the power supply, and the switch module SW12 is connected between the other end of the capacitor C1 and the negative electrode of the power supply; the switch module SW21 is connected between one end of the capacitor C1 and one end of the capacitor C2, and the switch module SW22 is connected between the other end of the capacitor C1 and the other end of the capacitor C2;
the switch modules SW11 and SW12 are both controlled by a control signal S1, and the switch modules SW21 and SW22 are both controlled by a control signal S2;
the control signal S1 and the control signal S2 are reciprocal signals, have the same duty ratio and are both less than 50%, and the high levels are not overlapped.
Further, the capacitance value of the capacitor C1 is 100 times that of the capacitor C2.
The utility model provides a can eliminate linear stabiliser of low dropout that line resistance influences, including band gap reference voltage source, amplifier, NMOS pipe and load module, its difference lies in: the voltage compensation unit comprises four switch modules SW11, SW12, SW21 and SW22 and two capacitors C1 and C2, wherein the capacitors C1 and C2 are connected with the bandgap reference voltage source in parallel, the switch module SW11 is connected between one end of the capacitor C1 and the positive pole of the bandgap reference voltage source, and the switch module SW12 is connected between the other end of the capacitor C1 and the negative pole of the bandgap reference voltage source; the switch module SW21 is connected between one end of the capacitor C1 and one end of the capacitor C2, and the switch module SW22 is connected between the other end of the capacitor C1 and the other end of the capacitor C2; one end of the capacitor C2 is connected with the positive terminal of the amplifier, and the other end of the capacitor C2 is connected with the ground terminal of the load module;
the switch modules SW11 and SW12 are both controlled by a control signal S1, and the switch modules SW21 and SW22 are both controlled by a control signal S2;
the control signal S1 and the control signal S2 are reciprocal signals, have the same duty ratio and are both less than 50%, and the high levels are not overlapped. Further, the capacitance value of the capacitor C1 is 100 times that of the capacitor C2.
Furthermore, the ground end of the load module is connected with the input end of the negative end of the amplifier. This makes it possible to compensate for the wiring resistance (R) from ground (gnd targ) to ground pad (gnd) of the load moduleGND) The influence of (c).
Further, the output end of the load module is connected to the negative electrode of the bandgap reference voltage source through the switch modules SW12 and SW 22. This compensates for the effect of the line resistance (Rvout) between the LDO output vout to the load mode.
The utility model provides a control signal generating unit based on a low dropout linear regulator capable of eliminating the influence of a connecting line resistor, which comprises a differential conversion module, a differential signal edge alignment module and a signal duty ratio adjusting module;
a differential conversion module: converting a clock signal CLK with a single end input into differential signals CLK0_ T and CLK0_ C;
differential signal edge alignment module: adjusting rising and falling edges of the differential signals CLK0_ T and CLK0_ C to generate fully symmetric differential signals CLK1_ T and CLK1_ C;
the signal duty ratio adjusting module: the duty ratios of the fully symmetric differential signals CLK1_ T and CLK1_ C are adjusted so that the high level pulse width is smaller than the low level pulse width, resulting in control signals S1, S2.
The utility model provides a method for eliminating wiring resistance in low dropout regulator, comprising the following steps:
1) at time t1, when the control signal S1 is high, the control signal S2 is low, and the switch modules SW11 and SW12 are turned on, so that vref1 is vref, and gnd1 is gnd; the switching modules SW21 and SW22 are turned off, and the bandgap reference voltage source charges the capacitor C1, so that the voltage v (C1) across the capacitor C1 is vref1-gnd1 is vref; the voltage v (C2) at C2 remains unchanged.
2) At time t3, the control signal S1 is at low level, the control signal S2 is at high level, and the switch modules SW11 and SW12 are turned off; since the switch modules SW21 and SW22 are turned on, gnd1 is gnd _ targ, and vref2 is vref 1;
since the capacitance value of C1 is 100 times the capacitance value of C2, the voltage v (C1) over C1 remains at the voltage vref at time t1, while the C2 voltage v (C2) is rapidly charged to v (C1), i.e., C1
v (C2) ═ v (C1) ═ vref; since both ends of C2 are connected to vref2 and gnd _ targ, respectively, vref2 is v (C2) + gnd _ targ; since the amplification of the amplifier is large, the voltages of the positive input and the negative input of the amplifier are the same, i.e., vout _ targ is vref 2. Therefore, it is not only easy to use
vout_targ＝vref2＝v(C2)+gnd_targ＝vref+gnd_targ
The following formula can be obtained:
the voltage difference of the load module is vout _ targ-gnd _ targ which is vref, that is, the voltage difference is the same as the output voltage of the bandgap reference voltage source and is not affected by the connection resistance of the power supply and the ground.
3) At times t2 and t4, the control signals S1 and S2 are both low, the switch modules SW11, SW12, SW21 and SW22 are turned off, the voltage of the capacitor C2 is kept at v (C1) ═ vref, and the voltage difference of the load modules is consistent with t 3.
Further, the capacitance value of the capacitor C1 is 100 times that of the capacitor C2.
The utility model discloses the beneficial effect who has:
the utility model discloses an increase voltage compensation unit in low dropout linear regulator, voltage compensation unit utilizes switch module and electric capacity combination, forms the secondary voltage source that is higher than standard voltage source, compensates the produced pressure differential of line resistance, and the voltage difference that reaches load module accords with the requirement of design standard.
Drawings
FIG. 1 is a circuit diagram of a conventional chip internal LDO;
FIG. 2 is a schematic diagram of the voltage and current of a conventional LDO circuit inside a chip;
FIG. 3 is a schematic diagram of the LDO of the present invention capable of eliminating the influence of the line resistance;
fig. 4 is a timing diagram of the control signal of the switching module of the LDO of the present invention;
FIG. 5 is a schematic diagram of the S1 and S2 signal generating units of the present invention;
FIG. 6 is a diagram illustrating the generation of control signals S1 and S2;
FIG. 7 is a schematic diagram of the circuit state at time t 1;
FIG. 8 is a schematic diagram of the circuit state at time t 3;
FIG. 9 is a schematic diagram of the circuit state at time t2 and time t 4.
Detailed Description
The utility model discloses based on traditional LDO circuit, designed neotype LDO, the problem that the load module voltage difference that solution line resistance that can be perfect leads to descends.
Example 1:
as shown in fig. 3, the present invention provides a voltage compensation unit, a low dropout linear regulator, a control signal generating unit thereof and a chip, wherein 4 switch modules, respectively SW11, SW12, SW21 and SW22, are added to the conventional voltage regulator. SW11 and SW12 are controlled by control signal S1, with SW11 and SW12 being ON when S1 is HIGH and SW11 and SW12 being OFF when S1 is LOW. SW21 and SW22 are controlled by control signal S2, with SW21 and SW22 being ON when S2 is HIGH and SW21 and SW22 being OFF when S2 is LOW.
The utility model discloses two electric capacity C1 and C2 have still been increased, and the capacitance value of C1 is about 10nF, and the capacitance value of C2 is about 100pF, and the capacitance value of C1 is 100 times of C2. The negative terminal of the amplifier is additionally input to vout targ of the load module.
The voltage higher than a band-gap reference voltage source can be formed by utilizing the structure, and the wiring resistance is eliminated.
Example 2: in the present invention, S1 and S2 are high-level non-overlapping clock signals, i.e., the high levels of S1 and S2 are staggered, as shown in fig. 4:
the control signals S1, S2 are generated by the signal generator in fig. 5:
the S1 and S2 signal generators are composed of a differential conversion module, a differential signal edge alignment module and a signal duty ratio adjusting module.
The differential conversion block converts the single-ended input clock signal CLK into differential signals CLK0_ T and CLK0_ C. The differential conversion module comprises an inverter and a transmission gate, wherein the inverter is INV0, the transmission gate comprises N0 and P0, the grid of the N0 is connected with a high level VIN, and the grid of the P0 is connected with a low level GND. Due to the large difference between the delay of the transmission gate and the delay of the inverter, the rising edge of CLK0_ T and the falling edge of CLK0_ C are asymmetric, and the falling edge of CLK0_ T and the rising edge of CLK0_ C are asymmetric, as shown in FIG. 6.
The differential signal edge alignment block adjusts the rising and falling edges of the differential signals CLK0_ T and CLK0_ C to produce fully symmetric differential signals CLK1_ T and CLK1_ C, as shown in fig. 6.
The signal duty ratio adjusting module adjusts the duty ratio of the clock signal so that the high-level pulse width is smaller than the low-level pulse width, as shown in fig. 6.
The time period T of CLK is determined by the amplifier's positive input leakage current and the LDO output accuracy requirements. Assuming that the forward input leakage current of the amplifier is Ileakge100nA, LDO output accuracy requirement is Δ V1 mV, C2 capacitance is 100 pF: t ═ Δ V ═ C2/Ileakage＝1mV*100pF/100nA＝1uS。
Example 3:
when time t1 is high at S1, SW11 and SW12 are turned on; s2 is low, and SW21 and SW22 are off. At time t1, vref1 equals 1.5V vref and gnd1 equals 0V, while C1 is charged to 1.5V, as shown in fig. 7.
Example 4:
when time t3 is, S1 is low, SW11 and SW12 are disconnected; s2 is high, and SW21 and SW22 are turned on. At time t3, gnd1 is gnd _ targ 0.1V, the voltage across the C1 capacitor is 1.5V, vref1 is 0.1+1.5 is 1.6V, vref2 is vref1 is 1.6V, the amplifier positive input is 1.6V, and the amplifier amplification factor is large, so the amplifier negative input is also 1.6V, so vout _ targ is 1.6V. The voltage difference of the load module is vout _ targ-gnd _ targ 1.6-0.1-1.5V, which is consistent with 1.5V of the design standard, as shown in fig. 8.
Example 5:
when t2 and t4 are time, S1 is low, and SW11 and SW12 are disconnected; s2 is low, and SW21 and SW22 are off. Since the capacitance of C2 is large, the voltage of C2 is kept at 1.5V, and the negative terminal of C2 is connected to gnd _ targ of 0.1V, vref2 is kept at 1.6V, so that vout _ targ is 1.6V. The voltage difference of the load module is vout _ targ-gnd _ targ 1.6-0.1-1.5V, which is consistent with 1.5V of the design standard, as shown in fig. 9.
Claims (8)
1. A voltage compensation unit, characterized by: the power supply comprises four switch modules SW11, SW12, SW21, SW22 and two capacitors C1 and C2, wherein the capacitors C1 and C2 are connected with a power supply in parallel, the switch module SW11 is respectively connected between one end of a capacitor C1 and the positive electrode of the power supply, and the switch module SW12 is connected between the other end of the capacitor C1 and the negative electrode of the power supply; the switch module SW21 is connected between one end of the capacitor C1 and one end of the capacitor C2, and the switch module SW22 is connected between the other end of the capacitor C1 and the other end of the capacitor C2;
the switch modules SW11 and SW12 are both controlled by a control signal S1, and the switch modules SW21 and SW22 are both controlled by a control signal S2;
the control signal S1 and the control signal S2 are reciprocal signals, have the same duty ratio and are both less than 50%, and the high levels are not overlapped.
2. The voltage compensation unit of claim 1, wherein: the capacitance value of the capacitor C1 is 100 times that of the capacitor C2.
3. Can eliminate low dropout regulator that line resistance influences, including band gap reference voltage source, amplifier, NMOS pipe and load module, its characterized in that: the voltage compensation unit comprises four switch modules SW11, SW12, SW21 and SW22 and two capacitors C1 and C2, wherein the capacitors C1 and C2 are connected with the bandgap reference voltage source in parallel, the switch module SW11 is connected between one end of the capacitor C1 and the positive pole of the bandgap reference voltage source, and the switch module SW12 is connected between the other end of the capacitor C1 and the negative pole of the bandgap reference voltage source; the switch module SW21 is connected between one end of the capacitor C1 and one end of the capacitor C2, and the switch module SW22 is connected between the other end of the capacitor C1 and the other end of the capacitor C2; one end of the capacitor C2 is connected with the positive terminal of the amplifier, and the other end of the capacitor C2 is connected with the ground terminal of the load module;
the switch modules SW11 and SW12 are both controlled by a control signal S1, and the switch modules SW21 and SW22 are both controlled by a control signal S2;
the control signal S1 and the control signal S2 are reciprocal signals, have the same duty ratio and are both less than 50%, and the high levels are not overlapped.
4. The low dropout regulator according to claim 3, wherein the low dropout regulator is capable of eliminating the influence of line resistance: the capacitance value of the capacitor C1 is 100 times that of the capacitor C2.
5. The low dropout regulator according to claim 3, wherein the low dropout regulator is capable of eliminating the influence of line resistance: the ground end of the load module is connected with the input end of the negative end of the amplifier.
6. The low dropout regulator according to claim 5, wherein the low dropout regulator is capable of eliminating the influence of line resistance: the output end of the load module is connected with the cathode of the band-gap reference voltage source through the switch modules SW12 and SW 22.
7. A control signal generation unit based on a low dropout regulator capable of eliminating the influence of a line resistance, characterized in that: the device comprises a differential conversion module, a differential signal edge alignment module and a signal duty ratio adjusting module;
a differential conversion module: converting a clock signal CLK with a single end input into differential signals CLK0_ T and CLK0_ C;
differential signal edge alignment module: adjusting rising and falling edges of the differential signals CLK0_ T and CLK0_ C to generate fully symmetric differential signals CLK1_ T and CLK1_ C;
the signal duty ratio adjusting module: the duty ratios of the fully symmetric differential signals CLK1_ T and CLK1_ C are adjusted so that the high level pulse width is smaller than the low level pulse width, resulting in control signals S1, S2.
8. A chip, characterized by: the low dropout regulator with built-in wiring resistance elimination of claims 3 to 6.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110442179A (en) * | 2019-09-06 | 2019-11-12 | 深圳讯达微电子科技有限公司 | The low pressure difference linear voltage regulator and removing method of connection resistances influence can be eliminated |
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2019
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110442179A (en) * | 2019-09-06 | 2019-11-12 | 深圳讯达微电子科技有限公司 | The low pressure difference linear voltage regulator and removing method of connection resistances influence can be eliminated |
| CN110442179B (en) * | 2019-09-06 | 2024-04-30 | 深圳讯达微电子科技有限公司 | Low-dropout linear voltage regulator capable of eliminating influence of connecting line resistance and elimination method |
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