CN211127782U - FMC card for digital-to-analog conversion - Google Patents

Abstract

The utility model discloses a FMC card of digital-to-analog conversion relates to information processing's technical field, has solved the complicated difficulty of current FMC card wiring and has influenced transmission rate's technical problem easily. The digital signal acquisition device comprises an analog signal output end, an FMC interface, a digital-analog acquisition chip and a clock chip, wherein the clock signal output end of the clock chip is connected with a clock terminal of the FMC interface, the clock signal output end of the clock chip is also connected with a clock signal input end of the digital-analog acquisition chip, the input end of the digital-analog acquisition chip is connected with a digital terminal of the FMC interface through a high-speed serial channel, and the output end of the digital-analog acquisition chip is connected with the analog signal output end. The utility model has high data transmission rate, simple and reliable wiring in a serial transmission mode, and optimized FMC card structure; and an external clock is not required to be introduced, so that the effective utilization of the port is facilitated.

Description

FMC card for digital-to-analog conversion

Technical Field

The present invention relates to information processing, and more particularly, to an FMC card for digital-to-analog conversion.

Background

The signal processing platform takes a digital signal processing technology as a core, and is widely applied to the fields of radars, aerospace, videos, digital communication, image processing, robots and the like. The development of information technology is fast, the requirements of people on data demand and data transmission speed are continuously improved, and a data converter which can be embedded with high speed, high precision and low power consumption becomes a research hotspot in the field of analog integrated circuits.

Compared with analog signals, digital signals have the advantages of convenience in storage and transfer, high fidelity and reliability and the like. With the great progress of CMOS technology level and the gradual maturity of digital system design software, the digital system has been developed rapidly in both processing capacity and processing speed. In contrast, the design of analog and digital interface circuits has not been paid sufficient attention in the past decades, and the analog design software is not mature enough to make the development of analog and especially digital-analog interface circuits lag behind the development of digital circuits, so that in some electronic systems including digital-analog interfaces, such as digital video systems and digital communication systems, the performance of the interface circuits, such as speed and precision, becomes a bottleneck limiting the performance of the whole system.

The digital-to-analog conversion of the current FMC card still adopts the traditional parallel transmission, the wiring is complex and difficult, the whole size of the FMC card is influenced, the transmission rate is also influenced, and the requirements of people on data transmission are difficult to meet.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is not enough to prior art, provides a FMC card of digital-to-analog conversion, has solved the complicated difficulty of present FMC card wiring and has influenced transmission rate's problem easily.

The technical scheme of the utility model lies in: the FMC card comprises an analog signal output end, an FMC interface, a digital-analog acquisition chip and a clock chip, wherein the clock signal output end of the clock chip is connected with a clock terminal of the FMC interface, the clock signal output end of the clock chip is further connected with a clock signal input end of the digital-analog acquisition chip, the input end of the digital-analog acquisition chip is connected with a digital terminal of the FMC interface through a high-speed serial channel, and the output end of the digital-analog acquisition chip is connected with the analog signal output end.

The digital-analog acquisition chip is an AD9172 chip.

The high-speed serial channel is a JESD204B interface channel.

The clock chip is an HMC7044 chip.

The FMC card further comprises a temperature-controlled oscillator and a voltage-controlled clock oscillator, the temperature-controlled oscillator is connected with a first frequency input end of the clock chip, and the voltage-controlled clock oscillator is connected with a second frequency input end of the clock chip.

The FMC interface is electrically connected with a temperature sensor.

The FMC interface is electrically connected with an EEPROM.

The clock chip comprises a first clock signal output end, a second clock signal output end and a third clock signal output end, wherein the first clock signal output end is connected with a first clock input end of the FMC interface, the second clock signal output end is connected with a second clock input end of the FMC interface, and the third clock signal output end is connected with a third clock input end of the FMC interface; the first clock signal output end is also connected with a first clock input end of the digital-analog acquisition chip, and the second clock signal output end is also connected with a second clock input end of the digital-analog acquisition chip;

the clock chip also comprises a serial input port which is connected with a serial output port of the FMC interface through a serial bus.

Advantageous effects

The utility model has the advantages that: the digital-analog acquisition chip is connected with the FMC interface through the high-speed serial channel, the problem of parallel transmission in the prior art is solved, the data transmission rate is high, the serial transmission mode is simple and reliable in wiring, and the structure of the FMC card is optimized. The FMC card also provides a homologous clock for a clock terminal of the FMC interface and the digital-analog acquisition chip through the clock chip, so that the FMC card does not need to introduce an external clock, and the effective utilization of ports is facilitated.

Drawings

Fig. 1 is a schematic structural diagram of the digital-to-analog conversion FMC card of the present invention.

Detailed Description

The present invention will be further described with reference to the following examples, which are not intended to limit the scope of the present invention, but are intended to be covered by the appended claims in any way.

Referring to fig. 1, the present invention relates to a digital-to-analog conversion FMC card, which comprises an analog signal output terminal, an FMC interface, a digital-to-analog acquisition chip and a clock chip, wherein the FMC interface employs a HPC connector with four hundred pins, the HPC connector has ten pins in total, and each row has forty pins, when the FMC interface employs a L PC connector, the FMC interface only includes four pins, and the L PC connector has one hundred and sixty pins in total, so the HPC connector with high pin count is a L PC connector compatible with low pin count during design, and then can be serialized and expanded on the basis of the existing design.

The clock signal output end of the clock chip is connected with the clock terminal of the FMC interface, and the clock signal output end of the clock chip is also connected with the clock signal input end of the digital-analog acquisition chip. The clock chip provides a homologous clock for the FMC card, so that the FMC card does not need to introduce an external clock, and the effective utilization of the port is facilitated. The clock chip is an HMC7044 chip.

In addition, the HMC7044 chip has two integer modes P LL which can be selected through SPI and overlapped on-chip VCO, the tuning ranges respectively reach 2.5GHz and 3 GHz.

The clock chip also comprises a serial input port which is connected with a serial output port of the FMC interface through a serial bus SPI. Namely, the HMC7044 chip is also connected to the FMC interface through the serial bus SPI to enable writing of corresponding management and control information to the control registers of the HMC7044 chip.

The clock chip comprises a first clock signal output end, a second clock signal output end and a third clock signal output end. The first clock signal output end is connected with the first clock input end of the FMC interface, the second clock signal output end is connected with the second clock input end of the FMC interface, and the third clock signal output end is connected with the third clock input end of the FMC interface. The first clock signal output end is also connected with the first clock input end of the digital-analog acquisition chip, and the second clock signal output end is also connected with the second clock input end of the digital-analog acquisition chip.

The HMC7044 chip may configure the output signal path as a Device Clock signal or a SYSREF Clock signal, or as more reference clocks that may be independently adjusted in phase and frequency, as desired. In the HMC7044 chip of this embodiment, the first Clock signal output terminal provides a Device Clock signal to the FMC interface, the second Clock signal output terminal provides a SYSREF Clock signal to the FMC interface, and the third Clock signal output terminal provides a GTXREF Clock signal to the FMC interface. Namely, the HMC7044 chip provides three Clock signals of Device Clock, SYSREF and GTXREF to the field programmable gate array FPGA connected with the FMC interface. In addition, the first Clock signal output end of the HMC7044 chip also provides a SYSREF Clock signal, and the second Clock signal output end of the HMC7044 chip also provides a Device Clock signal to the digital-analog acquisition chip.

The FMC card of this embodiment further includes a temperature controlled oscillator TCXO and a voltage controlled clock oscillator VCXO. Wherein, the temperature controlled oscillator TCXO is a crystal oscillator which controls frequency output through temperature; the voltage controlled clock oscillator VCXO is a crystal oscillator that controls frequency output by voltage. The temperature-controlled oscillator TCXO is connected with a first frequency input end of the clock chip, and the voltage-controlled clock oscillator VCXO is connected with a second frequency input end of the clock chip and used for providing oscillation frequency for the HMC7044 chip.

Specifically, the HMC7044 chip has two phase locked loops P LL and an overlapping on-chip voltage controlled oscillator VCO the first phase locked loop P LL locks a low noise voltage controlled clock oscillator VCXO to a relatively noisy reference, while the second phase locked loop P LL multiplies the voltage controlled clock oscillator VCXO signal to the voltage controlled oscillator VCO frequency, adding only very little noise.

The input end of the digital-analog acquisition chip is connected with the digital terminal of the FMC interface through the high-speed serial channel so as to realize that the digital-analog acquisition chip acquires digital signals sent by a Field Programmable Gate Array (FPGA) connected with the FMC interface. Wherein, the digital-analog acquisition chip is an AD9172 chip.

The AD9172 chip is a high-performance, two-channel, sixteen-bit digital-to-analog converter DAC, and supports the digital-to-analog converter DAC sampling rate to reach 12.6 GSPS. The AD9172 chip has an eight channel, 15Gbps JESD204B data input port, a high performance on-chip digital-to-analog converter clock multiplier, and digital signal processing functions for single and multi-band direct-to-radio frequency RF wireless applications. Each radio frequency RF, digital-to-analog converter DAC of the AD9172 chip has three bypassable multiplexed data input channels. Each data input channel comprises a configurable gain stage, an interpolation filter and a channel numerically controlled oscillator NCO for flexible multi-band planning; and each data input channel supports a multiplexed data rate of up to 1.5GSPS and is capable of aggregating multiple input data streams. In addition, the AD9172 chip supports ultra-wideband mode, bypassing the channel selector to provide maximum data rates up to 3.08GSPS (sixteen bit resolution) and 4.1GSPS (twelve bit resolution).

The AD9172 chip is applied to an FMC card, so that the FMC card supports single-band and multi-band wireless application and can support frequency synthesis of up to 6 GHz. In addition, the ultra-wideband channel bypass mode of the AD9172 chip enables the FMC card to support data rates of up to 3.08GSPS (sixteen bit resolution) and 4.1GSPS (twelve bit resolution).

And a serial input port of the digital-analog acquisition chip is connected with a serial output port of the FMC interface through a serial bus SPI. Namely, the FMC interface is also connected with the AD9172 chip through the serial bus SPI. The serial bus SPI is used to write the corresponding management and control information into the control registers of the AD9172 chip.

Specifically, the high-speed serial channel is a JESD204B interface channel, and high-speed data transmission is realized.

The JESD204B series protocol standard is mainly used for data transmission of converters and logic devices, such as Field Programmable Gate Arrays (FPGAs) and programmable chip ASICs, and has the advantages of small packaging area, small wiring quantity, reduced system design cost, lower power consumption and the like, is more convenient for board-level PCB design, and has stronger practicability.

Compared with the conventional interfaces, such as CMOS, L VDS and the like, the JESD204B interface has the following advantages:

first, the system design is simplified. When the conventional interface is used, the number of channels of the digital-to-analog converter DAC is large, the wiring between the digital-to-analog converter DAC and the field programmable gate array FPGA is very dense, the wiring length of each channel is required to be the same, otherwise the data quality may be deteriorated, and the implementation is relatively troublesome. The wiring between the digital-to-analog converter DAC and the field programmable gate array FPGA can be greatly simplified by using the JESD204B interface.

Second, the number of pins is reduced. Compared with the traditional interface, the JESD204B interface can greatly reduce the pin number, thereby reducing the cost of the board arrangement.

Third, the use of the JESD204B interface will make the package smaller and simpler, since the wiring is simpler and the pin count is smaller.

Fourth, the data rate advantage of the JESD204B interface will result in large bandwidth.

The JESD204B interface is specific to high data rate systems. The 3.2GHz HMC7044 chip clock jitter attenuator is internally provided with a unique function which can support and enhance the standard characteristic of the JESD204B interface. The HMC7044 chip provides 50fs jitter performance and improves the signal-to-noise ratio and dynamic range of high speed data converters. The HMC7044 chip also provides fourteen low noise and configurable outputs that can flexibly interface with many different devices, allowing designers to build a complete clock design with a single device. The HMC7044 chip clock jitter attenuator may generate source-synchronous and adjustable sample and frame alignment SYSREF clocks in a data converter system, simplifying the JESD204B interface design.

In summary, the application of the JESD204B interface to the FMC card not only meets the requirement of high-speed data transmission, but also reduces the number of input/output pins between the logic device and the converter.

The output end of the digital-analog acquisition chip is connected with the analog signal output end. Specifically, the AD9172 chip converts sixteen-bit digital signals transmitted from the FMC interface through the JESD204B interface channel into analog signals, and outputs the analog signals through two signal ports, i.e., an analog signal output port CHA and an analog signal output port CHB.

The FMC interface is electrically connected with a temperature sensor. The temperature sensor is used for detecting the working temperature of the FMC card and sending the detected temperature information to the field programmable gate array FPGA through the FMC interface; the FPGA judges whether the working environment of the FMC card is proper or not according to the temperature value, and if the working environment of the FMC card is smaller than the normal working threshold temperature value of the FMC card, a heater is started; and if the temperature is higher than the normal working threshold temperature value of the FMC card, starting the fan to provide a proper working environment for the FMC card.

The FMC interface is electrically connected with an EEPROM.

The EEPROM and the temperature sensor of the embodiment are both provided with I²And the C bus module is connected with the FMC interface. I.e. EEPROM and temperature sensor both pass I²The C bus is communicated with the field programmable gate array FPGA.

The above is only the preferred embodiment of the present invention, and it should be noted that for those skilled in the art, without departing from the structure of the present invention, several modifications and improvements can be made, which will not affect the utility model and the utility of the patent.

Claims (8)

1. The FMC card for digital-to-analog conversion is characterized by comprising an analog signal output end, an FMC interface, a digital-to-analog acquisition chip and a clock chip, wherein the clock signal output end of the clock chip is connected with a clock terminal of the FMC interface, the clock signal output end of the clock chip is also connected with a clock signal input end of the digital-to-analog acquisition chip, the input end of the digital-to-analog acquisition chip is connected with a digital terminal of the FMC interface through a high-speed serial channel, and the output end of the digital-to-analog acquisition chip is connected with the analog signal output end.

2. The FMC card of claim 1, wherein said digital-to-analog capture chip is an AD9172 chip.

3. A digital to analog converted FMC card as in claim 1, wherein said high speed serial channel is a JESD204B interface channel.

4. A digital to analog converted FMC card as in claim 1, wherein said clock chip is an HMC7044 chip.

5. A digital to analogue converted FMC card as claimed in claim 1 or 4, characterised in that it further comprises a temperature controlled oscillator connected to a first frequency input of the clock chip and a voltage controlled clock oscillator connected to a second frequency input of the clock chip.

6. The digital-to-analog converted FMC card of claim 1, wherein said FMC interface is electrically connected to a temperature sensor.

7. The digital-to-analog conversion FMC card as recited in claim 1, wherein said FMC interface is electrically connected to an EEPROM.

8. A digital to analog converted FMC card as claimed in claim 1 or 4, wherein said clock chip includes a first clock signal output coupled to a first clock input of the FMC interface, a second clock signal output coupled to a second clock input of the FMC interface, and a third clock signal output coupled to a third clock input of the FMC interface; the first clock signal output end is also connected with a first clock input end of the digital-analog acquisition chip, and the second clock signal output end is also connected with a second clock input end of the digital-analog acquisition chip;

the clock chip also comprises a serial input port which is connected with a serial output port of the FMC interface through a serial bus.

Images