CN210894646U - Device for quickly aligning cable cores - Google Patents
Device for quickly aligning cable cores Download PDFInfo
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- CN210894646U CN210894646U CN201921213887.7U CN201921213887U CN210894646U CN 210894646 U CN210894646 U CN 210894646U CN 201921213887 U CN201921213887 U CN 201921213887U CN 210894646 U CN210894646 U CN 210894646U
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Abstract
A device for fast aligning cable cores comprises a signal generating module 1, a signal sending module 2, a signal receiving module 3, a signal identifying module 4 and an aligning module 5, wherein the signal generating module 1 is used for generating a plurality of detection signals with different duty ratios and transmitting the detection signals to the signal sending module 2; the signal sending module 2 is respectively connected with the signal generating module 1 and the first end of the cable core to be tested; the signal receiving module 3 is respectively connected with the signal identification module 4 and the second end of the cable core to be tested; the signal identification module 4 is connected with the signal receiving module 3; the pair line module 5 is connected with the signal identification module 4. The utility model can keep constant duty ratio and is easy to identify, thereby quickly completing alignment; the detection of the cable containing the multi-strand cable core can be completed at one time; sequencing is carried out according to the duty ratio of the detection signals, so that the detection process is more convenient and faster, and the accuracy of the detection result is enhanced.
Description
Technical Field
The utility model relates to an electric power field, more specifically relates to a device that is used for cable core to line fast.
Background
In a multi-core cable line commonly used for a distribution network in a power system, due to the existence of an intermediate joint, a branch box and the like, wire cores at two ends of the cable can be connected only by corresponding marks. For example, the phase sequence at the two ends of the cable is not corresponding, which results in incorrect phase sequence of the lines, so that two lines which are connected with each other cannot be supplied with power in a phase-to-phase manner, and the three-phase motor at the user side has problems of reverse rotation and the like. Therefore, in the new construction and the reconstruction construction of the cable line, when the cable terminal or the intermediate joint is manufactured, the wire sequence at the two ends of the cable line must be checked and marked one by one, and the wiring action is carried out after the correct wire core in the cable line is ensured.
In cable construction, a universal meter or an insulation resistance meter is often used for testing the phase sequence of a cable, and a group of testers needs to be arranged at two ends of the cable respectively. When the insulation resistance meter is used for testing, after the testing is started and the cable is fully discharged, a first end tester informs a second end tester to ground the cable through an interphone or a mobile phone, and a worker uses a testing instrument to respectively measure the resistance of a cable core to a ground wire. The resistance value of 0 Ω can be judged as the same sequence. The test is repeated according to the method, and the corresponding relation of the wire sequences at the two ends of the cable can be determined. The checking method has complicated steps and repeated wiring and communication exist. After the test is finished, ungrounded cable cores need to be fully discharged one by one, and testers need to repeatedly measure the resistance of the cable cores to the ground. Meanwhile, the probability of success of one-time test of the test method is not high. Cable construction is generally located urban area, and construction section vehicle, personnel's round trip is intensive, and the environment is noisy, and external environment has certain influence to the test result, can cause the tester can't hear clear other side's instruction, understand other side's intention, leads to the line sequence to check mistake or repeated many times and checks. The phase sequence of the cable is checked by using the insulation resistance meter, the test voltage is higher, and the electric shock risk exists. When the insulation resistance meter is used for testing the phase sequence of the cable, the 500-2500V insulation resistance meter is used for multiple purposes, and after the test is finished, if the test cable is not discharged or is not sufficiently discharged in time, the electric shock danger can be brought to testers.
The phase sequence of the cable is tested by using a universal meter, although the cable does not need to be discharged phase by phase after one-time test is finished, other steps are the same as the method for testing by using the absolute resistance meter.
SUMMERY OF THE UTILITY MODEL
The utility model discloses at least, need solve one of following problem: the problems that the steps of the alignment method are complicated and repeated detection is needed in many times in the prior art are solved; the problem that the accuracy is low due to the fact that signals detected by a line alignment method are easily interfered is solved; the problem of there is the danger of electrocution is solved.
In order to solve the technical problem, the utility model provides a device for quick alignment of cable core, wherein, including signal generation module 1, signal transmission module 2, signal receiving module 3, signal identification module 4, to line module 5, signal generation module 1 is used for generating a plurality of detection signals that have different duty cycles and transmitting to signal transmission module 2; the signal sending module 2 is provided with a plurality of first connecting ports with different marks, the first connecting ports are respectively connected with the first ends of different cable cores to be detected, and detection signals with different duty ratios are sent to the first ends of the cable cores to be detected through the first connecting ports; the signal receiving module 3 is provided with a plurality of second connecting ports with different marks, and is respectively connected with the second ends of the cable cores to be detected, and is used for receiving detection signals with different duty ratios from the second ends of the cable cores to be detected and transmitting the detection signals to the signal identifying module 4; the signal identification module 4 receives and identifies detection signals with different duty ratios borne by each cable core to be detected; the alignment module 5 is connected with the signal identification module 4, and the first end and the second end of the cable core of the detection signal with the same duty ratio are corresponding to each other according to the mark of the first connection port, the mark of the second connection port and the positions of the detection signals with different duty ratios, so that the alignment of the cable core is completed.
According to an embodiment of the present invention, the signal generating module 1 further includes a first sequencing module, and the signal identifying module 4 further includes a second sequencing module, where the first sequencing module is configured to sequentially arrange the first ends of the cable cores to be tested according to the duty ratio of the transmitted detection signal, so as to obtain a first sequence; the second sequencing module is used for sequentially sequencing the second ends of the cable cores to be tested according to the duty ratio of the received detection signals to obtain a second sequence; the aligning module 5 is used for corresponding the first sequence and the second sequence to complete the cable core aligning.
According to an embodiment of the present invention, the signal generating module 1 comprises a first power source and a first microcontroller, the signal identifying module 4 comprises a second power source and a second microcontroller, and the first power source is used for supplying power to the first microcontroller; the first microcontroller comprises output pins which are not less than the total number of the cable cores to be tested; the second power supply is used for supplying power to the second microcontroller; the second microcontroller contains and is no less than the receiving pin of the cable core total number that awaits measuring.
According to an embodiment of the present invention, the signal sending module 2 further comprises a first buffer circuit, the signal receiving module 3 further comprises a second buffer circuit, the first buffer circuit is connected between the first microcontroller and the first end of the cable core to be tested, the first buffer circuit comprises a pull-up resistor for enhancing the transmission capability of the detection signal; the second buffer circuit is connected between the second microcontroller and the second end of the cable core to be detected, and the second buffer circuit comprises a pull-up resistor and is used for enabling a passage which does not receive the detection signal to be in a stable state.
According to an embodiment of the present invention, the pair line module 5 further comprises an inquiry circuit and a display circuit, wherein the inquiry circuit is connected to the second microcontroller, and is used for inquiring the corresponding relationship between the first ends of the cable cores and the second ends of the cable cores one by one, and displaying the corresponding relationship through the display circuit; the display circuit is connected with the query circuit and used for displaying the corresponding relation between the first end of the cable core and the second end of the cable core queried by the query circuit.
According to an embodiment of the present invention, the first power supply includes: the first charging circuit is used for charging the battery and performing electric quantity indication and overheating protection; the first voltage stabilizing circuit is used for providing stable voltage for the first microcontroller; the second power supply includes: the second charging circuit is used for charging the second battery and performing electric quantity indication and overheating protection; the second voltage stabilizing circuit is used for providing stable voltage for the second microcontroller.
According to an embodiment of the present invention, the battery pack further comprises a first sampling circuit and a second sampling circuit, wherein the first sampling circuit is connected between the first battery and the first microcontroller, and is used for enabling the first microcontroller to monitor the electric quantity of the first battery in real time; the second sampling circuit is connected between the second battery and the second microcontroller and used for enabling the second microcontroller to monitor the electric quantity of the second battery in real time.
According to an embodiment of the present invention, the first microcontroller includes a first chip, and a first crystal oscillation circuit, a first indication circuit, and a first reset circuit matched with the first chip, wherein the first crystal oscillation circuit is configured to provide a clock input to the first chip, the first indication circuit is configured to indicate an electrical quantity state and an operating state of the first chip, and the first reset circuit is configured to ensure safe operation of the first chip; the second controller comprises a second chip, and a second crystal oscillation circuit, a second indicating circuit and a second reset circuit which are matched with the second chip, wherein the second crystal oscillation circuit is used for providing clock input for the second chip, the second indicating circuit is used for indicating the electric quantity state and the running state of the second chip, and the second reset circuit is used for ensuring the safe running of the second chip.
The utility model discloses an adopt the detected signal of the different duty cycles of transmission to distinguish each cable core, even make detected signal appear in transmission process phenomenons such as interference, delay, still can keep its invariable duty cycle, easy discernment to accomplish the line fast. Furthermore, detection signals with different duty ratios are adopted, and the signal sending module and the signal receiving module are provided with multiple interfaces, so that the detection of the cable containing multiple cable cores can be completed at one time. The utility model discloses set up a plurality of interfaces at signal transmission module and signal reception module, make the utility model discloses a system also can detect a plurality of cables simultaneously, and every cable all contains stranded cable core. Further, the utility model discloses a sort the cable core to sort according to the size of detected signal duty cycle, need not accurate identification signal itself, only need discern the difference of each detected signal's duty cycle, make the testing process more convenient, do not rely on signal itself, even detected signal receives the interference in transmission process, do not influence the accuracy of testing result yet. Because the utility model discloses a detected signal be the signal of different duty cycles, it is little to the demand of voltage, first power with the second power can adopt 3.3V-4.2V power. Preferably, the power supply voltage of the first power supply and the second power supply is 3.3V, the test voltage is 4.2V, and the voltage is lower than the safe voltage 36V, so that the electric shock risk of a user is eliminated. The utility model discloses a buffer circuit reinforcing awaits measuring the detected signal intensity of the first end of cable core, makes detected signal transmission ability reinforcing in the cable core, can maintain the route that does not transmit signal again be in stable state can. The utility model discloses a display circuit and inquiry circuit for the user realizes quick to the line to the inquiry convenience of cable core.
Drawings
FIG. 1 is a schematic view of an apparatus for rapid alignment of cable cores;
FIG. 2 is a schematic diagram of a first sort module and a second sort module;
FIG. 3 is a schematic diagram of a signal generation module and a signal identification module;
FIG. 4 is a schematic diagram of a signal transmitting module and a signal receiving module;
FIG. 5 is a schematic diagram of an interrogation circuit and a display circuit;
FIG. 6 is a schematic diagram of a first power supply and a second power supply;
FIG. 7 is a schematic diagram of a first sampling circuit and a second sampling circuit;
FIG. 8 is a schematic diagram of a lithium battery charging circuit;
FIG. 9 is a schematic diagram of a DC regulated power supply circuit;
FIG. 10 is a schematic diagram of an analog-to-digital conversion sampling circuit;
FIG. 11 is a schematic diagram of a reset circuit;
FIG. 12 is a schematic diagram of an LED indicating circuit;
FIG. 13 is a schematic diagram of a crystal oscillator circuit;
FIG. 14 is a schematic diagram of a microcontroller core circuit;
FIG. 15 is a schematic diagram of a nixie tube driver and display circuit;
FIG. 16 is a schematic diagram of a 4 by 4 matrix key circuit;
FIG. 17 is a schematic diagram of a sense signal input buffer circuit;
fig. 18 is a schematic diagram of a transmission signal driving circuit;
FIG. 19 is a diagram showing the connection relationship of the circuits of the present embodiment; and
fig. 20 is a schematic diagram of a timing chart of the transmission detection signal.
Detailed Description
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like elements and techniques of the present invention so that advantages and features of the present invention may be more readily understood when implemented in a suitable environment. The following description is an embodiment of the present invention, and other embodiments related to the claims that are not explicitly described also fall within the scope of the claims.
Fig. 1 shows a schematic view of an apparatus for rapid alignment of cable cores.
As shown in fig. 1, the device for fast aligning cable cores comprises a signal generating module 1, a signal sending module 2, a signal receiving module 3, a signal identifying module 4 and an aligning module 5, wherein the signal generating module 1 is used for generating a plurality of detection signals with different duty ratios and transmitting the detection signals to the signal sending module 2; the signal sending module 2 is provided with a plurality of first connecting ports with different marks, the first connecting ports are respectively connected with the first ends of different cable cores to be detected, and detection signals with different duty ratios are sent to the first ends of the cable cores to be detected through the first connecting ports; the signal receiving module 3 is provided with a plurality of second connecting ports with different marks, and is respectively connected with the second ends of the cable cores to be detected, and is used for receiving detection signals with different duty ratios from the second ends of the cable cores to be detected and transmitting the detection signals to the signal identifying module 4; the signal identification module 4 receives and identifies detection signals with different duty ratios borne by each cable core to be detected; the alignment module 5 is connected with the signal identification module 4, and the first end and the second end of the cable core of the detection signal with the same duty ratio are corresponding to each other according to the mark of the first connection port, the mark of the second connection port and the positions of the detection signals with different duty ratios, so that the alignment of the cable core is completed.
The signal generating module 1 is configured to generate a plurality of detection signals with different duty ratios, for example, generate a series of digital voltage signals with different duty ratios, and transmit the signals to the cable core through the signal transmitting module 2.
The signal transmitting module 2 and the signal receiving module 3 are respectively connected to two ends of the cable core, the signal transmitting module 2 comprises a plurality of interfaces, so that the first end of each cable core is correspondingly connected to one interface, and meanwhile, the signal receiving module 3 also comprises a plurality of interfaces, so that the second end of each cable core is connected to one interface. Since the detection signals carried by each cable core are different, the signal identification module 4 identifies the detection signals, and the detection signals with the same duty ratio at the first end and the second end of the cable core can be determined, so that the corresponding relationship of the detection signals can be determined. And the alignment module 5 finishes alignment according to the corresponding relation.
The utility model discloses an adopt the detected signal of the different duty cycles of transmission to distinguish each cable core, even make detected signal appear in transmission process phenomenons such as interference, delay, still can keep its invariable duty cycle, easy discernment to accomplish the line fast. Furthermore, detection signals with different duty ratios are adopted, so that the detection of the cable containing the multi-strand cable core can be completed at one time. The utility model discloses set up a plurality of interfaces at signaling module 2 and signal receiving module 3, make the utility model discloses a system also can detect a plurality of cables simultaneously, and every cable all contains stranded cable core.
In the present invention, the duty ratio difference of the detection signal transmitted to each cable core can be set according to the number of the cable cores to be measured at a certain time, for example, when the number of the cable cores is small, the duty ratio difference can be increased, and when the number of the cable cores is large, the duty ratio difference can be appropriately decreased; the utility model discloses can also set for according to the interference factor of environment, like strong magnetism, strong electric field etc. for example, under strong magnetism, strong electric field's interference, suitably increase the difference of duty cycle, make the difference of the detection signal that each cable core of discernment that the signal identification end can be clear bore.
Fig. 2 shows a schematic diagram of a first and a second sorting module.
As shown in fig. 2, the signal generating module 1 further includes a first sequencing module, and the signal identifying module 4 further includes a second sequencing module, where the first sequencing module is configured to sequentially sequence the first ends of the cable cores to be detected according to the duty ratio of the transmitted detection signal, so as to obtain a first sequence; the second sequencing module is used for sequentially sequencing the second ends of the cable cores to be tested according to the duty ratio of the received detection signals to obtain a second sequence; the aligning module 5 is used for corresponding the first sequence and the second sequence to complete the cable core aligning.
The first sequencing module sequences the first ends of the cable cores to obtain a first sequence, and the sequencing of the first sequence is based on the duty ratio of detection signals borne by the cable cores. The first sorting module may include an ascending or descending sorting function.
For example, the first ends of the cable cores are sequentially numbered as a, b, …, n from large to small according to the duty ratio of the carried detection signal, which is the first sequence.
The signal identification module 4 identifies the duty ratio of the detection signal transmitted from the second end of each cable core, and the second sequencing module sequentially arranges the second ends of the cable cores to be detected according to the duty ratio to obtain a second sequence. The second sorting module may include functionality to sort in ascending or descending order.
For example, the second ends of the cable cores are arranged in sequence from large to small according to the duty ratio of the transmitted detection signal, and are numbered as a, b, …, and n, which is the second sequence.
And the pair module 5 matches the cable cores with the same serial numbers in the first sequence and the second sequence, so as to finish the cable core pair.
The utility model discloses a sort the cable core to sort according to the size of detected signal duty cycle, need not accurate identification signal itself, only need discern the difference of each detected signal's duty cycle, it is more convenient to make the testing process, does not rely on signal itself, even detected signal receives the interference in transmission process, does not influence the accuracy of testing result yet.
Fig. 3 shows a schematic diagram of a signal generation module and a signal identification module.
As shown in fig. 3, the signal generating module 1 includes a first power supply and a first microcontroller, and the signal identifying module 4 includes a second power supply and a second microcontroller, where the first power supply is used to supply power to the first microcontroller; the first microcontroller comprises output pins which are not less than the total number of the cable cores to be tested; the second power supply is used for supplying power to the second microcontroller; the second microcontroller contains and is no less than the receiving pin of the cable core total number that awaits measuring.
The first and second microcontrollers may be implemented as 32-bit ARM microcontrollers, such as the microcontroller product sold by the meaning Semiconductor (ST) corporation, core Cortex-M3. The highest working frequency reaches 72MHz, and a corresponding analog-to-digital conversion module, abundant external interrupt pin resources, a multi-channel timer, a corresponding serial communication interface and the like are integrated in the high-frequency. The multi-pin arrangement of the cable core alignment device enables the alignment of a plurality of cable cores of one cable or the alignment of a plurality of cable cores of a plurality of cables to be completed at one time when the cable cores to be detected are detected at each time.
Because the utility model discloses a detected signal be the signal of different duty cycles, it is little to the demand of voltage, first power with the second power can adopt 3.3V-4.2V power. Preferably, the power supply voltage of the first power supply and the second power supply is 3.3V, the test voltage is 4.2V, and the voltage is lower than the safe voltage 36V, so that the electric shock risk of a user is eliminated.
Fig. 4 shows a schematic diagram of a signal transmitting module and a signal receiving module.
As shown in fig. 4, the signal sending module 2 further includes a first buffer circuit, the signal receiving module 3 further includes a second buffer circuit, the first buffer circuit is connected between the first microcontroller and the first end of the cable core to be detected, and the first buffer circuit includes a pull-up resistor for enhancing the transmission capability of the detection signal; the second buffer circuit is connected between the second microcontroller and the second end of the cable core to be detected, and the second buffer circuit comprises a pull-up resistor and is used for enabling a passage which does not receive the detection signal to be in a stable state.
First buffer circuit with second buffer circuit can adopt current or future utility model's buffer circuit, the utility model discloses not prescribing a limit to, as long as its detection signal intensity that satisfies the first end of reinforcing cable core that awaits measuring makes detection signal transmission ability reinforcing in the cable core, can maintain the route of not transmitting signal again and be in stable state can.
For example, the first buffer circuit can adopt a driving signal chip, belongs to a high-speed CMOS device, is an eight-way positive phase buffer/line driver, has a tri-state output function, and can be used for line buffer input and line driving output. The high-voltage cable comprises an output strong pull-up resistor, so that signals can be transmitted in a longer cable to ensure that the signals at a receiving end are not distorted; the power supply filter capacitor comprises a power supply filter capacitor corresponding to a chip, and a corresponding sending signal output terminal, wherein the sending signal output terminal is matched with the first end of the cable core to be tested, and one terminal is selected to be well grounded with the testing device.
The second buffer circuit can adopt a buffer/drive signal chip which is a high-speed CMOS device and is an eight-way positive phase buffer/line driver, has a tri-state output function, and can be used for line buffer input and line drive output. The buffer/drive signal chip also comprises a power supply filter capacitor corresponding to the chip and a corresponding detection line input terminal, the detection line input terminal is matched with the second end of the cable core to be tested, wherein one terminal can be selected to be well grounded with the test device.
FIG. 5 shows a schematic diagram of the query circuit and the display circuit.
As shown in fig. 5, the pair line module 5 further includes an inquiry circuit and a display circuit, the inquiry circuit is connected to the second microcontroller, and is configured to inquire one by one a correspondence between the first end of each cable core and the second end of the cable core, and display the correspondence through the display circuit; the display circuit is connected with the query circuit and used for displaying the corresponding relation between the first end of the cable core and the second end of the cable core queried by the query circuit.
The inquiry circuit can adopt the existing or future utility model of a key circuit or a voice recognition circuit, etc. For example, the query circuit adopts a 4 × 4 matrix key circuit, which mainly comprises 4 rows and 4 lines, and corresponding keys are placed at corresponding row-column intersections, so that input detection of 16 keys can be realized by a line inversion method in a program, and corresponding receiving and sending channel line sequence corresponding relations are displayed on the digital tube in real time by detecting corresponding key inputs.
The display circuit can adopt a nixie tube driving and display circuit: the DISPLAY part is mainly completed by a DISPLAY four-digit nixie tube, the left two digits represent a receiving channel needing to be inquired currently during work, and the right two digits represent a signal which is sent by the channel of the generation end and corresponds to the current receiving channel, so that the corresponding line sequence relation of the cable wiring terminal can be displayed.
The utility model discloses a display circuit and inquiry circuit for the user realizes quick to the line to the inquiry convenience of cable core.
Fig. 6 shows a schematic diagram of the first power supply and the second power supply.
As shown in fig. 6, the first power supply includes: the first charging circuit is used for charging the battery and performing electric quantity indication and overheating protection; the first voltage stabilizing circuit is used for providing stable voltage for the first microcontroller; the second power supply includes: the second charging circuit is used for charging the second battery and performing electric quantity indication and overheating protection; the second voltage stabilizing circuit is used for providing stable voltage for the second microcontroller.
The first battery and the second battery can adopt lithium rechargeable batteries, and the first charging circuit and the second charging circuit can adopt lithium battery charging circuits: the charging management chip is mainly used for completing the charging management, the 5V power supply is input to supply power to the charging management chip through the heat dissipation resistor, the battery is connected to the pin of the charging chip, and when the temperature of the battery is too high and too low, the charging chip can automatically reduce the charging current and even stop the charging action so as to protect the battery from being damaged.
The first voltage stabilizing circuit and the second voltage stabilizing circuit can adopt direct current voltage stabilizing power supply circuits: the lithium battery is mainly completed by a direct-current stabilized power supply chip, the lithium battery is conducted through a manual switch and then is sent to the input end of the direct-current stabilized power supply chip, and the output end of the stabilized power supply chip can stably output a 3.3V power supply to supply power to the whole system.
Fig. 7 shows a schematic diagram of a first sampling circuit and a second sampling circuit.
As shown in fig. 7, the first power supply further includes a first sampling circuit, and the second power supply further includes a second sampling circuit, where the first sampling circuit is connected between the first battery and the first microcontroller, and is used for enabling the first microcontroller to monitor the electric quantity of the first battery in real time; the second sampling circuit is connected between the second battery and the second microcontroller and used for enabling the second microcontroller to monitor the electric quantity of the second battery in real time.
According to an embodiment of the present invention, the first microcontroller includes a first chip, and a first crystal oscillation circuit, a first indication circuit, and a first reset circuit matched with the first chip, wherein the first crystal oscillation circuit is configured to provide a clock input to the first chip, the first indication circuit is configured to indicate an electrical quantity state and an operating state of the first chip, and the first reset circuit is configured to ensure safe operation of the first chip; the second controller comprises a second chip, and a second crystal oscillation circuit, a second indicating circuit and a second reset circuit which are matched with the second chip, wherein the second crystal oscillation circuit is used for providing clock input for the second chip, the second indicating circuit is used for indicating the electric quantity state and the running state of the second chip, and the second reset circuit is used for ensuring the safe running of the second chip.
The utility model discloses an adopt the detected signal of the different duty cycles of transmission to distinguish each cable core, even make detected signal appear in transmission process phenomenons such as interference, delay, still can keep its invariable duty cycle, easy discernment to accomplish the line fast. Furthermore, detection signals with different duty ratios are adopted, and the signal sending module and the signal receiving module are provided with multiple interfaces, so that the detection of the cable containing multiple cable cores can be completed at one time. The utility model discloses set up a plurality of interfaces at signal transmission module and signal reception module, make the utility model discloses a system also can detect a plurality of cables simultaneously, and every cable all contains stranded cable core. Further, the utility model discloses a sort the cable core to sort according to the size of detected signal duty cycle, need not accurate identification signal itself, only need discern the difference of each detected signal's duty cycle, make the testing process more convenient, do not rely on signal itself, even detected signal receives the interference in transmission process, do not influence the accuracy of testing result yet. Because the utility model discloses a detected signal be the signal of different duty cycles, it is little to the demand of voltage, first power with the second power can adopt 3.3V-4.2V power. Preferably, the power supply voltage of the first power supply and the second power supply is 3.3V, the test voltage is 4.2V, and the voltage is lower than the safe voltage 36V, so that the electric shock risk of a user is eliminated. The utility model discloses a buffer circuit reinforcing awaits measuring the detected signal intensity of the first end of cable core, makes detected signal transmission ability reinforcing in the cable core, can maintain the route that does not transmit signal again be in stable state can. The utility model discloses a display circuit and inquiry circuit for the user realizes quick to the line to the inquiry convenience of cable core.
Example (b):
the receiving part of the device for quickly aligning the cable core mainly comprises the following circuits:
a second power supply: the system comprises a lithium battery charging circuit, a direct current stabilized power supply circuit and an analog-to-digital conversion sampling circuit;
a second microcontroller: the circuit comprises a reset circuit, an LED indicating circuit, a crystal oscillation circuit and a microcontroller core circuit;
query circuit and display circuit: 4 by 4 matrix key circuit, digital tube drive and display circuit;
a second buffer circuit: the detection signal is input to the buffer circuit.
The circuit of each module is briefly described as follows:
fig. 8 shows a schematic diagram of a lithium battery charging circuit.
As shown in fig. 8, the lithium battery charging circuit: the power supply is mainly completed by a U1 charging management chip, a 5V power supply is input from JP1 and supplies power to the charging management chip through an R1 heat dissipation resistor, and a battery is connected to a VBAT pin; c1, C2 are input filter capacitors, C3 and C4 are output filter capacitors; the LED1 (green) is a full indicator, the LED2 (red) is an indicator when charging is carried out, and the R2 and the R3 are corresponding indicator current-limiting resistors; r4 sets a resistance for the charging current; r5 and R6 are charging battery temperature detection control circuits, and when the temperature is too high or too low, the charging current is automatically reduced or even the charging is stopped, so that the battery is protected from being damaged.
Fig. 9 shows a schematic diagram of a dc regulated power supply circuit.
As shown in fig. 9, the dc voltage-stabilized power supply circuit: the direct-current stabilized power supply is mainly completed by a U2 direct-current stabilized power supply chip, a lithium battery BATT power supply is conducted through a SW manual switch and then is sent to the input end of the direct-current stabilized power supply chip, the output end of the stabilized power supply chip can stably output a 3.3V power supply to supply power to the whole system, C5 and C6 are input filter capacitors, and C7 and C8 are output filter capacitors.
Fig. 10 shows a schematic diagram of an analog-to-digital conversion sampling circuit.
As shown in fig. 10, the analog-to-digital conversion sampling circuit: the partial circuit is used for the microcontroller to monitor the battery capacity in real time so as to indicate the current capacity, the partial circuit is mainly divided by resistors R9 and R10, the high voltage of the battery is converted into low voltage according to a fixed proportion, and the low voltage is sent to an analog-to-digital conversion input detection end of the microcontroller; c9 is a sampling holding capacitor, so that the detection result is not influenced by light and micro voltage fluctuation of the battery during operation, and the detection accuracy is improved.
Fig. 11 shows a schematic diagram of a reset circuit.
As shown in fig. 11, the reset circuit: the circuit is mainly realized by an R11 and C12 capacitor charging and discharging circuit, the circuit can provide a low-lasting reset signal for the microcontroller in the process of just electrifying, and the reset signal is automatically released after the voltage is stabilized, so that the microcontroller can reliably operate.
Fig. 12 shows a schematic diagram of an LED indication circuit.
As shown in fig. 12, the LED indication circuit: the LED lamp mainly comprises R8, LEDs 4, R7 and an LED3, wherein the LED3 (red) is an electric quantity indicator lamp which slowly flashes at low electric quantity and does not light when the electric quantity is sufficient; the LED4 (blue) is a system operation indicator light, the system slowly flashes when running normally, and the system is lighted when abnormal.
Fig. 13 shows a schematic diagram of a crystal oscillator circuit.
As shown in FIG. 13, the crystal oscillator circuit is mainly realized by a Y1 quartz crystal and corresponding C10 and C11 crystal matching capacitors, and is combined with a microcontroller internal module circuit to realize stable crystal oscillation and provide stable and reliable clock input for the microcontroller.
Fig. 14 shows a schematic diagram of a microcontroller core circuit.
As shown in fig. 14, the microcontroller core circuit: u3 is a low-end 32-bit ARM microcontroller, is a classic microcontroller product that Italian Semiconductor (ST) company promoted, and the application prospect is wide, and the kernel is Cortex-M3. The highest working frequency reaches 72MHz, corresponding integrated analog-to-digital conversion modules, abundant external interrupt pin resources, a multi-channel timer, corresponding serial communication interfaces and the like are integrated in the chip, the resources on the chip are abundant, and the running speed is high. The peripheral C13, C14, C15 and C16 are power supply filter capacitors of the microcontroller, so that external noise is prevented from interfering the power supply of the microcontroller, and the reliable operation of the microcontroller is ensured; r15 is a microcontroller normal operating mode selection resistor.
Fig. 15 shows a schematic diagram of a nixie tube driving and display circuit.
As shown in fig. 15, the nixie tube driving and displaying circuit: the DISPLAY part is mainly completed by a DISPLAY four-digit nixie tube, the left two digits represent a receiving channel (01-16) which needs to be inquired currently during work, and the right two digits represent a signal (01-16) which is sent by the channel of the generating end and corresponds to the line of the current receiving channel, so that the corresponding line sequence relation of the cable wiring terminal can be displayed. U4 and U5 are 8-bit SHIFT buffers with serial input and parallel output, the clock input is PA5_ SHIFT _ CLK, the PA6_ LATCH _ CLK control, the DATA input is PA7_ DATA, U4 controls the segment line of the nixie tube, and U5 controls the bit line of the nixie tube. C17 and C18 are power supply filter capacitors of the corresponding chips.
Fig. 16 shows a schematic diagram of a 4 x 4 matrix key circuit.
As shown in fig. 16, the 4 × 4 matrix key circuit: the digital tube is mainly composed of 4 rows and 4 lines, corresponding keys are arranged at corresponding row-column intersections, input detection of 16 keys can be realized through a line inversion method in a program, and corresponding receiving and sending channel line sequence corresponding relations are displayed on the digital tube in real time through detecting corresponding key input.
Fig. 17 shows a schematic diagram of a detection signal input buffer circuit.
As shown in fig. 17, the detection signal is input to the buffer circuit: the circuit is mainly completed by U6 and U7 buffer/drive signal chips, is a high-speed CMOS device, is an eight-way positive phase buffer/line driver, has a tri-state output function, and can be used for line buffer input and line drive output. RK1 and RK2 are input pull-up resistors and are guaranteed to be at a fixed logic potential when a sending signal is not received; c19, C20 are power filter capacitors of the corresponding chips, and JP2 are corresponding detection line input terminals, wherein the 17 th terminal needs to be well grounded to the test system.
The device transmitting part for fast cable core alignment of the embodiment mainly comprises the following circuits:
a first power supply: the system comprises a lithium battery charging circuit, a direct current stabilized power supply circuit and an analog-to-digital conversion sampling circuit;
a first microcontroller: the circuit comprises a reset circuit, an LED indicating circuit, a crystal oscillation circuit and a microcontroller core circuit;
the first buffer circuit: a transmission signal driving circuit.
The difference of the transmitting part of the device for quickly aligning the cable core in the embodiment relative to the receiving part is mainly that a nixie tube driving and displaying circuit and a corresponding 4 x 4 matrix key circuit are omitted, and meanwhile, a detection signal input buffer circuit is changed into a transmitting signal driving circuit. Circuits corresponding to the receiving section are not described one by one.
Microcontroller core circuit: the principle is consistent with that of the receiving end, and only the signal line of the functional module which is not provided by the transmitting end is removed.
Fig. 18 shows a schematic diagram of a transmission signal driving circuit.
As shown in fig. 18, the transmission signal driving circuit: the circuit is mainly completed by U4 and U5 driving signal chips, is a high-speed CMOS device, is an eight-way positive phase buffer/line driver, has a tri-state output function, and can be used for line buffering input and line driving output. RK1 and RK2 are output strong pull-up resistors, so that signals can be transmitted in a long cable to ensure that the signals at a receiving end are not distorted; c17, C18 are power filter capacitors of the corresponding chips, and JP2 are corresponding transmission signal output terminals, wherein the 17 th terminal needs to be well grounded to the test system.
Fig. 19 is a schematic diagram showing the connection relationship of the circuits of the present embodiment.
Fig. 20 shows a schematic diagram of a timing chart of the transmission detection signal.
As shown in fig. 20, the ground terminals of the transmitting and receiving terminals are each connected to the cable copper shield. At a sending end, all channels are in the same period (t16-t0), the channels are 0-15 channels, and the duration of high level sending of each channel is sequentially increased along with the increase of the channel serial number, so that the waveform of a signal sent by each channel of the sending end is unique, and based on the characteristic, the width of high level and low level of the signal received by each channel is detected one by one at a receiving end, namely, the channel line of the sending end, which is correspondingly connected to each channel line of the receiving end, can be distinguished; the digital tube can immediately display the corresponding relation between the receiving channel number and the sending channel number by inputting the corresponding receiving end channel number to be inquired through the keys.
The device is small in size, convenient to carry and flexible and convenient to operate, the sending end and the receiving end are connected once, one person can quickly operate and finish the wire sequence marking of a 16-core cable, the measurement is accurate and reliable, the manual measurement of two former personnel and the interference of human factors caused by two former communication between two places are eliminated, meanwhile, the device is powered by a low-voltage battery, and the potential safety hazard caused by the measurement of high-voltage equipment such as a megger and the like in the past can be avoided; the above example only describes the manufacture of a 16-core cable, and since the processing speed of the microcontroller is very high, if the wire sequence check of more core cables is needed, only the corresponding program needs to be modified, and the corresponding transmitting and receiving terminals are extended on the hardware based on the wire distinguishing principle, the patent is not limited to the application of only distinguishing the wire sequence of the cable below 16 cores.
The device is applied to cable construction for line sequence checking, the test result is compared with the test result of the conventional method, the test result of the device is confirmed to be correct, and a tester can complete cable line sequence test only by once wiring, so that the test steps are simplified, and the test time is greatly reduced.
The device is used for testing the cable sequence, the testing steps are few, and the working efficiency is improved. Meanwhile, the problem of repeated communication in the conventional test method is avoided, the probability of errors caused by unsmooth communication of personnel or noisy environment in the test process is reduced, and the test accuracy is improved.
The test voltage of the cable phase sequence tester is 4.2V and is less than the safe voltage of 36V, so that the risk of electric shock of a tester is eliminated.
The cable sequence checking method adopting the microprocessor can improve the testing efficiency, reduce the testing steps, reduce the error probability caused by unsmooth personnel communication or noisy environment in the testing process, eliminate the electric shock risk of the testing personnel, and has better application prospect in the power cable sequence checking work when the cable terminal or the intermediate joint is manufactured in the newly-built and modified construction of a cable line.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Claims (8)
1. A device for fast aligning cable cores is characterized by comprising a signal generating module (1), a signal sending module (2), a signal receiving module (3), a signal identifying module (4) and an aligning module (5),
the signal generating module (1) is used for generating a plurality of detection signals with different duty ratios and transmitting the detection signals to the signal sending module (2);
the signal sending module (2) is provided with a plurality of first connecting ports with different marks, the first connecting ports are respectively connected with the first ends of different cable cores to be detected, and detection signals with different duty ratios are sent to the first ends of the cable cores to be detected through the first connecting ports;
the signal receiving module (3) is provided with a plurality of second connecting ports with different marks, is respectively connected with the second ends of the cable cores to be detected, and is used for receiving detection signals with different duty ratios from the second ends of the cable cores to be detected and transmitting the detection signals to the signal identifying module (4);
the signal identification module (4) receives and identifies detection signals with different duty ratios borne by each cable core to be detected;
the alignment module (5) is connected with the signal identification module (4), and the first end and the second end of the cable core with the detection signals with the same duty ratio are corresponding to finish cable core alignment according to the mark of the first connecting port, the mark of the second connecting port and the positions of the detection signals with different duty ratios, wherein the positions of the detection signals are sent and received.
2. The device according to claim 1, characterized in that the signal generation module (1) further comprises a first ordering module, the signal identification module (4) further comprises a second ordering module,
the first sequencing module is used for sequencing the first ends of the cable cores to be tested according to the duty ratio of the sent detection signals to obtain a first sequence;
the second sequencing module is used for sequentially sequencing the second ends of the cable cores to be tested according to the duty ratio of the received detection signals to obtain a second sequence;
the alignment module (5) is used for corresponding the first sequence and the second sequence to finish cable core alignment.
3. The device according to claim 1, characterized in that the signal generation module (1) comprises a first power supply, a first microcontroller, the signal identification module (4) comprises a second power supply, a second microcontroller,
the first power supply is used for supplying power to the first microcontroller;
the first microcontroller comprises output pins which are not less than the total number of the cable cores to be tested;
the second power supply is used for supplying power to the second microcontroller;
the second microcontroller contains and is no less than the receiving pin of the cable core total number that awaits measuring.
4. The apparatus according to claim 3, wherein the signal transmission module (2) further comprises a first buffer circuit, the signal reception module (3) further comprises a second buffer circuit,
the first buffer circuit is connected between the first microcontroller and the first end of the cable core to be detected, and comprises a pull-up resistor for enhancing the transmission capability of the detection signal;
the second buffer circuit is connected between the second microcontroller and the second end of the cable core to be detected, and the second buffer circuit comprises a pull-up resistor and is used for enabling a passage which does not receive the detection signal to be in a stable state.
5. The device according to claim 3, characterized in that the pairing module (5) further comprises an inquiry circuit and a display circuit,
the query circuit is connected with the second microcontroller and is used for querying the corresponding relation between the first end of each cable core and the second end of each cable core one by one and displaying the corresponding relation through the display circuit;
the display circuit is connected with the query circuit and used for displaying the corresponding relation between the first end of the cable core and the second end of the cable core queried by the query circuit.
6. The apparatus of claim 3, wherein the first power source comprises: the first charging circuit is used for charging the battery and performing electric quantity indication and overheating protection; the first voltage stabilizing circuit is used for providing stable voltage for the first microcontroller;
the second power supply includes: the second charging circuit is used for charging the second battery and performing electric quantity indication and overheating protection; the second voltage stabilizing circuit is used for providing stable voltage for the second microcontroller.
7. The apparatus of claim 6, further comprising a first sampling circuit and a second sampling circuit,
the first sampling circuit is connected between the first battery and the first microcontroller and is used for enabling the first microcontroller to monitor the electric quantity of the first battery in real time;
the second sampling circuit is connected between the second battery and the second microcontroller and used for enabling the second microcontroller to monitor the electric quantity of the second battery in real time.
8. The apparatus of claim 3, wherein the first microcontroller comprises a first chip, and a first crystal oscillation circuit, a first indication circuit and a first reset circuit matched with the first chip, wherein the first crystal oscillation circuit is used for providing a clock input for the first chip, the first indication circuit is used for indicating the power state and the operation state of the first chip, and the first reset circuit is used for guaranteeing the safe operation of the first chip;
the second microcontroller comprises a second chip, and a second crystal oscillation circuit, a second indicating circuit and a second reset circuit which are matched with the second chip, wherein the second crystal oscillation circuit is used for providing clock input for the second chip, the second indicating circuit is used for indicating the electric quantity state and the running state of the second chip, and the second reset circuit is used for ensuring the safe running of the second chip.
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| CN201921213887.7U CN210894646U (en) | 2019-07-30 | 2019-07-30 | Device for quickly aligning cable cores |
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| CN201921213887.7U CN210894646U (en) | 2019-07-30 | 2019-07-30 | Device for quickly aligning cable cores |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112415335A (en) * | 2020-12-01 | 2021-02-26 | 广东电网有限责任公司清远供电局 | Line detection device |
| CN113466732A (en) * | 2021-06-28 | 2021-10-01 | 广西电网有限责任公司贵港供电局 | Battery measuring circuit and battery measuring instrument |
| CN115436719A (en) * | 2022-11-10 | 2022-12-06 | 国网浙江省电力有限公司台州供电公司 | High-voltage line alignment method based on signal synchronization |
| US20220407270A1 (en) * | 2021-06-16 | 2022-12-22 | Dongguan Xcoso Electronic Technology Co., Ltd. | MFi-CERTIFIED DIGITAL DATA CABLE |
-
2019
- 2019-07-30 CN CN201921213887.7U patent/CN210894646U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112415335A (en) * | 2020-12-01 | 2021-02-26 | 广东电网有限责任公司清远供电局 | Line detection device |
| US20220407270A1 (en) * | 2021-06-16 | 2022-12-22 | Dongguan Xcoso Electronic Technology Co., Ltd. | MFi-CERTIFIED DIGITAL DATA CABLE |
| US11631953B2 (en) * | 2021-06-16 | 2023-04-18 | Dongguan Xcoso Electronic Technology Co., Ltd | MFi-certified digital data cable |
| CN113466732A (en) * | 2021-06-28 | 2021-10-01 | 广西电网有限责任公司贵港供电局 | Battery measuring circuit and battery measuring instrument |
| CN115436719A (en) * | 2022-11-10 | 2022-12-06 | 国网浙江省电力有限公司台州供电公司 | High-voltage line alignment method based on signal synchronization |
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