CN210867732U

CN210867732U - SPI changes ethernet interface circuit and frequency conversion controller

Info

Publication number: CN210867732U
Application number: CN201921951285.1U
Authority: CN
Inventors: 刘�东
Original assignee: Ceristar Electric Co ltd; Capital Engineering & Research Inc Ltd
Current assignee: Ceristar Electric Co ltd; Capital Engineering & Research Inc Ltd
Priority date: 2019-11-12
Filing date: 2019-11-12
Publication date: 2020-06-26
Anticipated expiration: 2029-11-12

Abstract

The utility model discloses a SPI changes ethernet interface circuit and frequency conversion controller, this SPI changes ethernet interface circuit includes: the system comprises an ARM chip, an SPI-Ethernet protocol chip and an RJ45 interface; the RJ45 interface is communicated with external Ethernet equipment and used for receiving or sending Ethernet signals; the SPI changes the Ethernet protocol chip to connect between ARM chip and RJ45 interface for change the SPI signal of ARM chip output into the Ethernet signal that RJ45 interface can discern, perhaps, change the Ethernet signal from RJ45 interface into the SPI signal that the ARM chip can receive. The utility model discloses can convert the SPI signal of ARM chip output into ethernet signal to realize the ethernet data transmission function of ARM chip, possess extensive commonality.

Description

SPI changes ethernet interface circuit and frequency conversion controller

Technical Field

The utility model relates to a circuit field especially relates to a SPI changes ethernet interface circuit and frequency conversion controller.

Background

This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

In order to realize the bidirectional ethernet data transmission function of the ARM chip, in the prior art, a serial port RS232 signal of the ARM chip is converted into an ethernet signal, and the rapid transmission of data at different speeds is realized by adjusting the baud rate of the serial port.

The serial port RS232 can increase the voltage in the signal transmission process, so that the chip loss is increased. In addition, the serial port RS232 can only realize a limited number of baud rates, so that the application range of the ARM chip is limited.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a SPI changes ethernet interface circuit for solve the present serial ports RS232 signal that utilizes the ARM chip and realize the scheme of ethernet data transmission function, because the baud rate that RS232 provided is limited, can't provide the technical problem of the ethernet data transmission function of more speeds, this method includes: the system comprises an ARM chip, an SPI-Ethernet protocol chip and an RJ45 interface; the RJ45 interface is communicated with external Ethernet equipment and used for receiving or sending Ethernet signals; the SPI changes the Ethernet protocol chip to connect between ARM chip and RJ45 interface for change the SPI signal of ARM chip output into the Ethernet signal that RJ45 interface can discern, perhaps, change the Ethernet signal from RJ45 interface into the SPI signal that the ARM chip can receive.

The embodiment of the utility model provides a still provide a frequency conversion controller for solve the present serial ports RS232 signal that utilizes the ARM chip and realize the scheme of ethernet data transmission function, because the baud rate that RS232 provided is limited, can't provide the technical problem of the ethernet data transmission function of more speeds, this frequency conversion controller includes: the SPI is converted into the Ethernet interface circuit.

The embodiment of the utility model provides an in, change ethernet protocol chip through the SPI of connecting between ARM chip and RJ45 interface, realize the interconversion between SPI signal and the ethernet signal, can make the ARM chip realize the purpose with outside ethernet equipment communication through the RJ45 interface.

Through the embodiment of the utility model provides a, can convert the SPI signal of ARM chip output into the ethernet signal to realize the ethernet data transmission function of ARM chip, possess extensive commonality.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts. In the drawings:

fig. 1 is a schematic diagram of an SPI-to-ethernet interface circuit provided in an embodiment of the present invention;

fig. 2 is a schematic diagram of signal pin connection of an iMX6DQ chip provided in an embodiment of the present invention;

fig. 3 is a schematic diagram of the signal pin wiring of the W5500 chip provided in the embodiment of the present invention;

fig. 4 is a schematic diagram of the RJ45 interface signal pin connection provided in the embodiment of the present invention;

fig. 5 is a schematic diagram of a frequency conversion controller provided in an embodiment of the present invention.

Description of reference numerals:

an ARM chip 101; SPI-to-ethernet protocol chip 102; RJ45 interface 103; an RTC clock chip 104; a nixie tube driver chip 105; a nixie tube 106; a DDR memory 107; an MMC memory 108; a CF card interface 109; USB to TTL module 110; an FPGA chip 111.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention are described in further detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.

In the description of the present specification, the terms "comprising," "including," "having," "containing," and the like are used in an open-ended fashion, i.e., to mean including, but not limited to. Reference to the description of the terms "one embodiment," "a particular embodiment," "some embodiments," "for example," etc., means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. The sequence of steps involved in the embodiments is for illustrative purposes to illustrate the implementation of the present application, and the sequence of steps is not limited and can be adjusted as needed.

The embodiment of the utility model provides an in provide a SPI changes ethernet interface circuit, fig. 1 does the embodiment of the utility model provides an in provide a SPI changes ethernet interface circuit schematic diagram, as shown in fig. 1, this ethernet interface circuit includes: ARM chip 101, SPI-to-Ethernet protocol chip 102, and RJ45 interface 103.

The RJ45 interface 103 is in communication with an external ethernet device, and is used for receiving or sending ethernet signals; the SPI-to-ethernet protocol chip 102 is connected between the ARM chip 101 and the RJ45 interface 103, and is configured to convert an SPI signal output by the ARM chip 101 into an ethernet signal that can be recognized by the RJ45 interface 103, or convert an ethernet signal from the RJ45 interface 103 into an SPI signal that can be received by the ARM chip 101.

Note that the RJ45 interface is a current mainstream electrical port ethernet interface, and ethernet communication can be realized through the RJ45 interface.

In an optional embodiment, in the SPI-to-ethernet interface circuit provided in the embodiment of the present invention, the ARM chip 101 employs iMX6DQ chip; the SPI to ethernet protocol chip 102 employs a W5500 chip. Wherein, the iMX6DQ chip is a high-end ARM chip and can run a Linux operating system; the W5500 chip is an SPI-to-Ethernet protocol chip with a core; the pin definition of the iMX6QD chip is shown in table 1, and the pin definition of the W5500 chip is shown in table 2.

TABLE 1 pin definitions for 1 iMX6QD chip

Serial number	Pin number	Name (R)	Means of
				1	35	MOSI	Master station outputting slave station input signal
2	34	MISO	Master station input and slave station output signal
				3	32	CS#	Chip select signal
4	36	INT#	Interrupt signal
				5	33	SCK	Clock signal
6	37	RST#	Reset signal

TABLE 2 Pin definition of W5500 chip

Fig. 2 is a schematic diagram of signal pin connection of an iMX6DQ chip provided in an embodiment of the present invention; fig. 3 is a schematic diagram of the signal pin wiring of the W5500 chip provided in the embodiment of the present invention; as shown in fig. 2 and 3, the iMX6DQ chip includes: MOSI signal pin, MISO signal pin, CS # signal pin, INT signal pin, SCK signal pin and RST # signal pin; the W5500 chip includes: MOSI signal pin, MISO signal pin, CS # signal pin, INT signal pin, SCK signal pin and RST # signal pin; the MOSI signal pin, the MISO signal pin, the CS # signal pin, the INT signal pin, the SCK signal pin, and the RST # signal pin of the iMX6DQ chip are connected to the MOSI signal pin, the MISO signal pin, the CS # signal pin, the INT signal pin, the SCK signal pin, and the RST # signal pin of the W5500 chip, respectively.

As shown in fig. 2 and 3, the MOSI signal pin of the iMX6DQ chip is connected to the MOSI signal pin of the W5500 chip; iMX6 MISO signal pin of 6DQ chip is connected with MISO signal pin of W5500 chip; iMX6 CS # signal pin of 6DQ chip is connected with CS # signal pin of W5500 chip; an INT signal pin of the iMX6DQ chip is connected with an INT signal pin of the W5500 chip; the SCK signal pin of the iMX6DQ chip is connected with the SCK signal pin of the W5500 chip; the RST # signal pin of the iMX6DQ chip is connected to the RST # signal pin of the W5500 chip.

The pin definition of the RJ45 interface is shown in table 3, and for the RJ45 interface, the following 12 pins and shields must be reliably connected. Pin 1 and pin 2 are differential transmission signals; pin 3 and pin 6 are differential receive signals.

TABLE 3 Pin definitions for RJ45 interfaces

Serial number	Pin number	Name (R)	Means of
				1	1	RJ_TX+	Sending a signal
2	2	RJ_TX-	Negative sending signal
				3	3	RJ_RX+	Received signal is
4	4	VCC	Power supply positive
				5	5	VCC	Power supply positive
6	6	RJ_RX-	Negative of received signal
				7	7	NC	Unconnected signal
8	8	GND	Power ground
				9	9	VCC	Power supply positive
10	10	Link	Connection signal
				11	11	Data	Data signal
12	12	VCC	Power supply positive

Fig. 4 is the embodiment of the utility model provides an RJ45 interface signal pin wiring schematic diagram, as shown in fig. 4, the embodiment of the utility model provides an among the SPI changes ethernet interface circuit, RJ45 interface 103 includes: RJ _ TX + signal pin, RJ _ TX-signal pin, RJ _ RX + signal pin and RJ _ RX-signal pin; the W5500 chip still includes: a TXP signal pin, a TXN signal pin, an RXP signal pin and an RXN signal pin; the RJ _ TX + signal pin of the RJ45 interface 103 is connected with the TXP signal pin of the W5500 chip; an RJ _ TX-signal pin of the RJ45 interface 103 is connected with a TXN signal pin of the W5500 chip; an RJ _ RX + signal pin of the RJ45 interface 103 is connected with an RXP signal pin of the W5500 chip; the RJ _ RX-signal pin of the RJ45 interface 103 is connected with the RXN signal pin of the W5500 chip.

Optionally, the embodiment of the present invention provides an SPI-to-ethernet interface circuit that can also include: a first indicator light and a second indicator light (not shown in fig. 1); the RJ45 interface 103 also includes: a Data signal pin and a Link signal pin; the Data signal pin of the RJ45 interface 103 is connected with a first indicator light, and the first indicator light is used for indicating the Data state of the RJ45 interface; the Link signal pin of the RJ45 interface 103 is connected with a second indicator light, and the second indicator light is used for indicating the connection state of the RJ45 interface. It should be noted that the signal pin of the LED1 of the W5500 chip is connected to the first indicator light; the signal pin of the LED2 of the W5500 chip is connected with a second indicator light.

Preferably, the first indicator light and the second indicator light are both light emitting diodes.

In an optional embodiment, the SPI to ethernet interface circuit provided in the embodiments of the present invention may further include: and the RTC clock chip 104 is connected with the ARM chip 101 and is used for providing a clock signal. Optionally, the embodiment of the utility model provides an in the SPI changes ethernet interface circuit, ARM chip 101 expands out Real-time clock (RTC) chip through I2C bus, realizes the record and the storage of actual time for entire system and controller are more perfect.

In an optional embodiment, the SPI to ethernet interface circuit provided in the embodiments of the present invention may further include: a nixie tube driving chip 105 and a nixie tube 106; the nixie tube driving chip 105 is connected with the ARM chip 101 and is used for driving the nixie tube 106 to be turned on or turned off; the nixie tube 106 is used for displaying the state information of the ARM chip 101. Optionally, the nixie tube 106 is an 8-bit LED nixie tube, and is used to display the state of the ARM chip, so that a user can conveniently determine the condition of the software inside the ARM chip. Alternatively, the nixie tube driver chip 105 can be a 74HC595D serial-to-parallel chip, which converts the serial signal of the ARM chip into a parallel signal for driving the LED nixie tube.

In an optional embodiment, the SPI to ethernet interface circuit provided in the embodiments of the present invention may further include: DDR memory 107 and MMC memory 108; the DDR memory 107 is connected with the ARM chip 101 and used for storing memory data; and the MMC memory 108 is connected with the ARM chip 101 and used for storing data. Alternatively, the MMC memory may be an MMC card, through which onboard data storage is implemented, and both system check and encrypted data need to be stored in the MMC card. Because the read-write speed of the MMC card is higher than that of the CF card, the data which is held emergently can be stored in the MMC card. The embodiment of the utility model provides an among the frequency conversion controller, the ARM chip passes through DDR's mode extension RAM, has realized the storage and the operation of big batch memory data, supports current various mainstream DDR buses.

In an optional embodiment, the SPI to ethernet interface circuit provided in the embodiments of the present invention may further include: and the CF card interface 109 is connected with the ARM chip 101 and is used for storing data into an external CF card or reading data in the external CF card. The ARM chip is expanded out of the storage function of the CF card, and system data or user data are stored in the CF card, so that system and program upgrading can be conveniently carried out through the CF card.

In an optional embodiment, as shown in fig. 5, the SPI-to-ethernet interface circuit provided in the embodiment of the present invention may further include: and the USB to TTL module 110 is connected to the ARM chip 101 and is configured to convert USB data into TTL data. Through the mode of USB converting to TTL, the function of debugging ARM chip system (such as Linux system) through USB can be realized, the work of system debugging personnel is facilitated, and the hot plug function can be supported.

Optionally, the embodiment of the present invention provides an SPI-to-ethernet interface circuit that can also include: PCIe to PCI chips (e.g., XIO2001 chips), fiber ethernet chips, fiber ethernet interfaces; the optical fiber Ethernet interface is connected with the optical fiber Ethernet chip and used for transmitting Ethernet data through optical fibers; the PCIe-to-PCI chip is connected with the ARM chip and used for expanding the ARM chip out of the optical fiber Ethernet bus, so that the ARM chip is connected with the optical fiber Ethernet chip through the expanded optical fiber Ethernet bus. The optical fiber Ethernet interface is expanded by the PCIe-to-PCI chip, and the high-speed Ethernet original message can be received and transmitted.

The embodiment of the utility model provides an in still provide a frequency conversion controller, include: any of the above alternative or preferred SPI to ethernet interface circuits.

Because the alternating-current variable-frequency transmission technology has the advantages of excellent control performance, wide application range, large driving capacity, energy conservation in operation and low maintenance cost, the alternating-current variable-frequency transmission technology is developed rapidly in recent years. However, the existing variable frequency controller is based on a DSP + FPGA system architecture, uses a DSP chip as a main chip, and performs peripheral design of a processor by using a motor control function of the DSP chip. The framework has the advantages of flexible structure and strong universality. The method has the defects that the DSP chip has limited main frequency (usually hundreds of megameters), so that the frequency conversion controller based on the DSP + FPGA system framework has defects in real-time task processing and multi-task processing, and is only suitable for occasions with low requirements on the performance of frequency conversion equipment.

From this, in an optional embodiment, the embodiment of the utility model provides a frequency conversion controller can be based on ARM + FPGA system architecture's high performance frequency conversion controller, can realize quick real-time response and the frequency conversion control of high accuracy to the demand that high-end frequency conversion equipment of adaptation and frequency conversion system used.

Fig. 5 is a schematic view of a frequency conversion controller in an embodiment of the present invention, as shown in fig. 5, the frequency conversion controller includes: an FPGA chip 111, and any of the optional or preferred SPI to ethernet interface circuits described above.

The system comprises an SPI (serial peripheral interface) to Ethernet interface circuit, an ARM chip 101 and a frequency conversion device, wherein the ARM chip in the SPI to Ethernet interface circuit is used for controlling one or more frequency conversion devices; the FPGA chip 111 is connected with the ARM chip 101 and is used for transmitting the control signals output by the ARM chip 101 to each frequency conversion device in parallel; ARM chip 101 communicates with an external ethernet device through RJ45 interface 103 provided by SPI-to-ethernet interface circuitry, for receiving or sending ethernet signals.

Optionally, the ARM chip adopted by the embodiment of the present invention may be an MCIMX6Q5EYM12AD chip; the FPGA chip can be an XC6SLX16-2FTG256C chip.

The embodiment of the utility model provides a frequency conversion controller, with the ARM chip as the main control chip of converter, with the peripheral interface chip of FPGA chip as the converter, utilize the ARM chip can realize various complex algorithms, utilize the FPGA chip not only can realize high-speed parallel data transmission, can also realize quick response and high accuracy frequency conversion control, the real-time strong, the flexibility is high. This frequency conversion controller passes through the embodiment of the utility model provides a SPI changes ethernet interface circuit realizes the conversion between ARM chip SPI signal and the ethernet signal for ARM chip 101 changes the RJ45 interface that ethernet interface circuit provided and communicates with outside ethernet equipment through SPI, thereby is convenient for the communication of ARM chip system and computer.

The embodiment of the utility model provides a frequency conversion controller can adopt 24V DC power supply, provides power source and is connected with external power source through the FPGA chip. Alternatively, the power interface may be a power terminal.

Optionally, the embodiment of the utility model provides an among the frequency conversion controller, the ARM chip adopts 4 nuclear A9 series, and basic frequency can reach 1 GHz. Compare with the dominant frequency (hundred megas grades) of current DSP chip, the embodiment of the utility model provides a frequency conversion controller based on ARM + FPGA system architecture can realize quick real-time response and high accuracy frequency conversion control to more be adapted to the demand of high-end converter and system application. Additionally, the embodiment of the utility model provides an among the variable frequency controller, the FPGA chip is responsible for parallel high-speed data processing, and work such as optical fiber data communication realizes the function of a controller area a plurality of motors through coordination. Optionally, the ARM chip may perform high-speed data communication with the FPGA chip through the local bus.

In an optional embodiment, the embodiment of the present invention provides a frequency conversion controller, which may further include: and the external expansion board is connected with the FPGA chip 111 and is used for expanding various field buses or Ethernet buses. The FPGA chip expands the external expansion board through the internal bus, can realize the support of various field buses and real-time Ethernet buses, and enhances the expansibility of the system.

Optionally, the embodiment of the utility model provides an among the variable frequency controller, FPGA chip 111 can also be used to expand out following arbitrary one kind of interface: the device comprises a CAN bus interface, an RS485 bus interface, an RS232 bus interface, an SSI encoder signal interface, an incremental encoder signal interface, a digital output signal interface, a digital input signal interface, an analog output signal interface, an analog input signal interface and an interrupt signal transmission interface. By expanding the data transmission interfaces of various communication protocols, the coordinated and unified operation of multiple communication protocols is realized. The FPGA chip expands an interrupt signal transmission interface for receiving or sending a quick interrupt signal in a plastic optical fiber or glass optical fiber mode, and data synchronization and signal synchronization among a plurality of controllers are achieved. The ARM chip also supports an interrupt triggering function so as to realize the emergency processing of the fast signals.

By the way, the utility model provides a frequency conversion controller adopts long life cycle's ARM chip, can satisfy the requirement of the long life cycle of industrial product, high reliability, high stability. The controller adopts a main stream Linux system kernel version which is stably maintained for a long time, a real-time operating system is built in to complete a real-time multitask function, and free development of software codes can be realized by adopting a C language or a C + + language. Optionally, the method can also support the conventional embedded programming functions of debugging codes of the C language or the C + + language under the Eclipse software framework, viewing built-in variables of the program and the like. Furthermore, the programming languages such as PLC, ladder diagram, structure text, instruction list, CFC, SFC and the like can be supported.

To sum up, the embodiment of the utility model provides a SPI changes ethernet interface circuit and changes ethernet interface circuit's variable frequency controller including this SPI changes ethernet protocol chip through SPI, realizes the interconversion between ARM chip primary SPI signal and the ethernet signal, has greatly simplified general ethernet protocol implementation process, possesses extensive commonality.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An SPI-to-ethernet interface circuit, comprising: an ARM chip (101), an SPI-to-Ethernet protocol chip (102) and an RJ45 interface (103);

wherein the RJ45 interface (103) communicates with an external Ethernet device for receiving or transmitting Ethernet signals; the SPI-Ethernet protocol chip (102) is connected between the ARM chip (101) and the RJ45 interface (103) and used for converting an SPI signal output by the ARM chip (101) into an Ethernet signal which can be identified by the RJ45 interface (103) or converting an Ethernet signal from the RJ45 interface (103) into an SPI signal which can be received by the ARM chip (101).

2. The SPI-to-ethernet interface circuit according to claim 1, wherein said ARM chip (101) is an iMX6DQ chip; the SPI-Ethernet protocol chip (102) is a W5500 chip.

3. The SPI-to-ethernet interface circuit of claim 2 wherein said iMX6DQ chip comprises: MOSI signal pin, MISO signal pin, CS # signal pin, INT signal pin, SCK signal pin and RST # signal pin; the W5500 chip includes: MOSI signal pin, MISO signal pin, CS # signal pin, INT signal pin, SCK signal pin and RST # signal pin;

the MOSI signal pin, the MISO signal pin, the CS # signal pin, the INT signal pin, the SCK signal pin and the RST # signal pin of the iMX6DQ chip are respectively connected with the MOSI signal pin, the MISO signal pin, the CS # signal pin, the INT signal pin, the SCK signal pin and the RST # signal pin of the W5500 chip.

4. The SPI-to-ethernet interface circuit according to claim 2, wherein said RJ45 interface (103) comprises: RJ _ TX + signal pin, RJ _ TX-signal pin, RJ _ RX + signal pin and RJ _ RX-signal pin; the W5500 chip still includes: a TXP signal pin, a TXN signal pin, an RXP signal pin and an RXN signal pin;

the RJ _ TX + signal pin of the RJ45 interface (103) is connected with the TXP signal pin of the W5500 chip; an RJ _ TX-signal pin of the RJ45 interface (103) is connected with a TXN signal pin of the W5500 chip; an RJ _ RX + signal pin of the RJ45 interface (103) is connected with an RXP signal pin of the W5500 chip; an RJ _ RX-signal pin of the RJ45 interface (103) is connected with an RXN signal pin of the W5500 chip.

5. The SPI-to-ethernet interface circuit according to claim 2, wherein said SPI-to-ethernet interface circuit further comprises: a first indicator light and a second indicator light; the RJ45 interface (103) further comprises: a Data signal pin and a Link signal pin;

the Data signal pin of the RJ45 interface (103) is connected with a first indicator light, and the first indicator light is used for indicating the Data state of the RJ45 interface; and a Link signal pin of the RJ45 interface (103) is connected with a second indicator light, and the second indicator light is used for indicating the connection state of the RJ45 interface.

6. An SPI-to-ethernet interface circuit as recited in claim 5, wherein said first indicator light and said second indicator light are both light emitting diodes.

7. The SPI-to-ethernet interface circuit according to claim 1, wherein said SPI-to-ethernet interface circuit further comprises: and the RTC clock chip (104) is connected with the ARM chip (101) and is used for providing a clock signal.

8. The SPI-to-ethernet interface circuit according to claim 1, wherein said SPI-to-ethernet interface circuit further comprises: a nixie tube driving chip (105) and a nixie tube (106);

the nixie tube driving chip (105) is connected with the ARM chip (101) and used for driving the nixie tube (106) to be turned on or turned off; the nixie tube (106) is used for displaying the state information of the ARM chip (101).

9. The SPI-to-ethernet interface circuit according to claim 1, wherein said SPI-to-ethernet interface circuit further comprises: a DDR memory (107) and an MMC memory (108);

the DDR memory (107) is connected with the ARM chip (101) and used for storing memory data; the MMC memory (108) is connected with the ARM chip (101) and used for storing data.

10. The SPI-to-ethernet interface circuit according to claim 1, wherein said SPI-to-ethernet interface circuit further comprises: and the CF card interface (109) is connected with the ARM chip (101) and is used for storing data into an external CF card or reading the data in the external CF card.

11. A variable frequency controller, comprising: the SPI-to-ethernet interface circuit of any one of claims 1 to 10.