CN210837329U

CN210837329U - SMD integrated piezoresistor

Info

Publication number: CN210837329U
Application number: CN201921901110.XU
Authority: CN
Inventors: 隋台中; 吴伟; 苏周; 路学亮; 葛金鑫; 郭庆超
Original assignee: Xingqin Changzhou Electronic Co ltd; Huawei Technologies Co Ltd
Current assignee: Xingqin Changzhou Electronic Co ltd; Huawei Technologies Co Ltd
Priority date: 2019-11-06
Filing date: 2019-11-06
Publication date: 2020-06-23
Anticipated expiration: 2029-11-06

Abstract

The utility model relates to a SMD integrated piezo-resistor, including pressure sensitive chip, conductive pin and encapsulated layer, pressure sensitive chip at least 2, every pressure sensitive chip both sides are all attached with the conductive electrode, the one end of conductive pin with the conductive electrode welding, the other end of conductive pin bend the shaping at same horizontal plane; after welding, the conductive pins are respectively arranged between two adjacent pressure sensitive chips and on the outer side of the outermost pressure sensitive chip and form an assembly with the pressure sensitive chips; the encapsulating layer wraps the assembly attached with the conductive pins, the encapsulating layer is provided with an upper surface plane used for automatic absorption and a lower surface plane used for mounting, and the lower surfaces of the conductive pins after being bent and molded are flush with the lower surface plane of the encapsulating layer. The utility model is different from the common SMD component, the whole packaging design is a vertical structure, which effectively reduces the occupation area of the PCB; has the characteristics of integration, miniaturization, high reliability, lead-free environmental protection requirement satisfaction and the like.

Description

SMD integrated piezoresistor

Technical Field

The utility model relates to an electronic components, especially a SMD integrated piezo-resistor.

Background

The piezoresistor is a voltage-limiting type protection device. By utilizing the nonlinear characteristic of the piezoresistor, when overvoltage appears between two poles of the piezoresistor, the piezoresistor can clamp the voltage to a relatively fixed voltage value, thereby realizing the protection of a post-stage circuit. The main parameters of the piezoresistor are piezovoltage, current capacity, junction capacitance, response time and the like. When the voltage applied to the varistor is below its threshold value, the current flowing through it is extremely small, corresponding to a resistance of infinite value. That is, when the voltage across it is below its threshold, it behaves as an open-state switch. When the voltage across the varistor exceeds its threshold, the current flowing through it increases sharply, corresponding to a resistance of infinitesimal magnitude. That is, when the voltage applied to it is above its threshold, it behaves as a closed-state switch.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is: a patch type integrated piezoresistor is provided.

The utility model provides a technical scheme that its technical problem adopted is: a patch type integrated piezoresistor comprises at least 2 piezochips, conductive pins and an encapsulating layer, wherein conductive electrodes are attached to two sides of each piezochip, one ends of the conductive pins are welded with the conductive electrodes, and the other ends of the conductive pins are bent and formed on the same horizontal plane; after welding, the conductive pins are respectively arranged between two adjacent pressure sensitive chips and on the outer side of the outermost pressure sensitive chip and form an assembly with the pressure sensitive chips; the encapsulating layer wraps the assembly attached with the conductive pins, the encapsulating layer is provided with an upper surface plane used for automatic absorption and a lower surface plane used for mounting, and the lower surfaces of the conductive pins after being bent and molded are flush with the lower surface plane of the encapsulating layer.

Further, the pressure sensitive chip of the present invention is a polycrystalline semiconductor pressure sensitive chip, and the polycrystalline semiconductor pressure sensitive chip is a circular, square or equilateral polygon.

Furthermore, electrically conductive pin and electrically conductive electrode between through the welding of high temperature leadless solder.

Furthermore, the encapsulating layer is made of low-stress epoxy resin, ceramic or other high-temperature-resistant insulating materials.

Further, pressure sensitive chip, electrically conductive pin and encapsulated layer encapsulate the component of vertical SMD structure.

Further say, encapsulated layer's lower table plane on be provided with the recess, electrically conductive pin buckle the shaping after be located the recess and electrically conductive pin buckles the lower surface after the shaping and the lower table plane of encapsulated layer flush.

Furthermore, the bending directions of the conductive pins of the present invention are the same or different; the conductive pins are led out independently or connected and led out according to application.

Further, the utility model discloses arrange the electrically conductive pin between two adjacent pressure sensitive chips in and arrange the electrically conductive pin in the outside pressure sensitive chip outside in and form respectively and draw forth the route.

The utility model has the advantages that: the packaging structure is different from a common SMD component, the whole packaging structure is designed into a vertical structure, and the occupied area of a PCB is effectively reduced; has the characteristics of integration, miniaturization, high reliability, lead-free environmental protection requirement satisfaction and the like.

Drawings

Fig. 1-2 are schematic structural views of the present invention;

FIGS. 3-5 are schematic views of the application of the present invention;

in the figure: 10. a pressure sensitive chip; 11. a conductive electrode; 21-23, conductive pins; 30. high temperature lead-free solder; 40. an encapsulation layer; 41. and (4) a groove.

Detailed Description

The invention will now be described in further detail with reference to the drawings and preferred embodiments. These drawings are simplified schematic drawings and illustrate the basic structure of the present invention only in a schematic manner, and thus show only the components related to the present invention.

As shown in fig. 1-5, the chip-type integrated piezoresistor is packaged by high-temperature resistant polycrystalline semiconductor piezoresistor chips, conductive pins, and low-stress epoxy resin into a vertical SMD structure, wherein the number of the piezoresistor chips is 2.

Conductive electrodes 11 are attached to both sides of each pressure-sensitive chip 10; one end of the conductive pin 21/22/23 is soldered to the conductive electrode 11 of the chip by high temperature lead-free solder, and the low stress encapsulating resin 40 is encapsulated to form an assembly. The metal pins 22 are arranged in the middle of the pressure-sensitive chips 10, the

conductive pins

21 and 23 are respectively arranged on the other two sides of the pressure-sensitive chips 10 to form an assembly component, and the

conductive pins

21, 22 and 23 are formed and arranged on one side of the package to form a surface. The low stress encapsulation resin 40 encapsulates the varistor assembly with the conductive leads 21/22/23, and the encapsulation material 40 forms two planes, one for automatic absorption and the other for lead extraction in combination with the design of the grooves 41. A group of grooves 41 are designed on one plane of the packaging resin, so that a coplanar effect can be formed when the conductive pins are led out, and the phenomena of component toppling and shifting in the SMT assembly process are avoided by combining with gravity center control.

Conductive pins

21, 22 and 23 are arranged among the 2 pressure-sensitive components 10, the other two sides of the pressure-sensitive components are also attached with the conductive pins, and the middle attached pin and the pins at the two sides form a leading-out passage respectively. The

conductive pins

21, 22 and 23 are formed on one surface, and the

conductive pins

21, 22 and 23 can be formed on the surface in one direction or different directions; the conductive pins can be led out independently or connected and led out according to application. When the

conductive pins

21, 22 and 23 are led out independently, the independent individuals of the two equivalent piezoresistors work; the

conductive pins

21 and 23 are connected together and are connected with the conductive pin 22 in parallel, so that the impact resistance of the component to surge current can be improved exponentially;

conductive pins

21, 23 are connected together while conductive pin 22 is not connected to a circuit; the

conductive pins

21 and 23 are connected in series to form a voltage-sensitive component, which can withstand 2 times of working voltage.

The utility model has the advantages of a plurality of pressure sensitive chip set and design into the standing structure, can reduce circuit board area occupied, and be convenient for automatic SMT production.

The utility model discloses have electrically conductive pin and can constitute cluster, parallel connection in a flexible way, not only be favorable to integrating of circuit design, satisfy different operating voltage and/or different surge application environment's protection requirement.

The utility model discloses inside electrical connection has adopted high temperature leadless solder, not only satisfies SMT welding temperature's requirement, can realize leadless environmental protection requirement again.

The utility model discloses the subassembly body adopts low stress epoxy molding encapsulation, avoids mechanical stress to the influence of inside polycrystal semiconductor chip, has improved the reliability of subassembly.

The utility model discloses be different from general SMD subassembly, adopted vertical project organization, can reduce SMD's PCB area occupied effectively.

The utility model discloses a coplanar design of electrically conductive pin combines the focus control of body, avoids vertical structural design's subassembly to take place to empty, the emergence of aversion in SMT equipment technology.

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. The utility model provides a SMD integrated piezo-resistor, includes pressure sensitive chip, electrically conductive pin and encapsulated layer, its characterized in that: the number of the pressure-sensitive chips is at least 2, conductive electrodes are attached to two sides of each pressure-sensitive chip, one end of each conductive pin is welded with the corresponding conductive electrode, and the other end of each conductive pin is bent and formed on the same horizontal plane; after welding, the conductive pins are respectively arranged between two adjacent pressure sensitive chips and on the outer side of the outermost pressure sensitive chip and form an assembly with the pressure sensitive chips; the encapsulating layer wraps the assembly attached with the conductive pins, the encapsulating layer is provided with an upper surface plane used for automatic absorption and a lower surface plane used for mounting, and the lower surfaces of the conductive pins after being bent and molded are flush with the lower surface plane of the encapsulating layer.

2. The chip integrated varistor of claim 1, wherein: the pressure-sensitive chip is a polycrystalline semiconductor pressure-sensitive chip which is circular or equilateral polygon.

3. The chip integrated varistor of claim 1, wherein: and the conductive pin and the conductive electrode are welded through high-temperature lead-free solder.

4. The chip integrated varistor of claim 1, wherein: the encapsulating layer is low-stress epoxy resin or ceramic.

5. The chip integrated varistor of claim 1, wherein: the pressure-sensitive chip, the conductive pins and the encapsulating layer are packaged into a component with a vertical SMD structure.

6. The chip integrated varistor of claim 1, wherein: the lower surface plane of the encapsulating layer is provided with a groove, the conductive pins are positioned in the groove after being bent and molded, and the lower surfaces of the bent and molded conductive pins are flush with the lower surface plane of the encapsulating layer.

7. The patch type integrated piezoresistor of claim 6, wherein: the bending directions of the conductive pins are the same or different; the conductive pins are led out independently or connected and led out according to application.

8. The patch type integrated varistor of claim 7, wherein: and the conductive pins arranged between two adjacent pressure-sensitive chips and the conductive pins arranged on the outer side of the outermost pressure-sensitive chip form leading-out passages respectively.