CN210835649U

CN210835649U - Switch control protection circuit for preventing false action

Info

Publication number: CN210835649U
Application number: CN201921589787.4U
Authority: CN
Inventors: 胡文干
Original assignee: Shenzhen H&T Intelligent Control Co Ltd
Current assignee: Shenzhen H&T Intelligent Control Co Ltd
Priority date: 2019-09-19
Filing date: 2019-09-19
Publication date: 2020-06-23
Anticipated expiration: 2029-09-19

Abstract

The embodiment of the utility model provides a relate to on-off control technical field, disclose an on-off control protection circuit of preventing malfunction, include: the circuit comprises a first control circuit, a second control circuit and a switch circuit; the input end of the first control circuit is connected with the single chip microcomputer, the output end of the first control circuit is connected with the input end of the second control circuit, the input end of the second control circuit is also connected with the single chip microcomputer, and the output end of the second control circuit is connected with the switch circuit; and when in misoperation, the first control circuit receives the PWM pulse signal output by the singlechip, outputs a first level to the second control circuit according to the PWM pulse signal, and controls the switch circuit to be switched off through the second control circuit. In this way, the embodiment of the utility model provides a can prevent that the malfunction from damaging the device, improve the reliability of product, can reduce the safety protection cost of product.

Description

Switch control protection circuit for preventing false action

Technical Field

The embodiment of the utility model provides a relate to on-off control technical field, concretely relates to prevent on-off control protection circuit of malfunction.

Background

In the application of electronic technology, when a P-MOS switch at the output high-voltage terminal of an intelligent quick-charging lithium battery charger is controlled, after an NPN triode is generally turned on at a high level at an IO port of a single chip Microcomputer (MCU), a power P-MOS transistor is turned on by a negative pressure difference between a voltage to ground of a gate of the P-MOS and a source of the P-MOS.

Most of the existing P-MOS driving circuits are high-level turn-on triodes, and the P-MOS turn-on output is directly turned on through resistance voltage division. Under normal conditions, the IO port of the MCU detects that the battery pack is inserted and is not in a full pack state, and then the P-MOS tube is opened to charge the access equipment. However, in products with higher requirements on safety performance, such as lithium batteries, lead-acid batteries, nickel-hydrogen nickel-chromium battery packs, electric tools, garden tools and the like, the protection function of some battery packs is not comprehensive enough, and double protection is particularly important through a charger. Before the single chip microcomputer is initialized, each IO port is in an uncontrolled state in a short time, and the high level output by the IO ports is used for opening the NPN triode, so that the power P-MOS tube is directly switched on, and the charging equipment and the device of the charger are damaged.

SUMMERY OF THE UTILITY MODEL

In view of the above, embodiments of the present invention provide a switch control protection circuit that prevents malfunction, overcoming the above problems or at least partially solving the above problems.

According to the utility model discloses an aspect of the embodiment provides a prevent on-off control protection circuit of malfunction, include: the circuit comprises a first control circuit, a second control circuit and a switch circuit; the input end of the first control circuit is connected with the single chip microcomputer, the output end of the first control circuit is connected with the input end of the second control circuit, the input end of the second control circuit is also connected with the single chip microcomputer, and the output end of the second control circuit is connected with the switch circuit; and when in misoperation, the first control circuit receives the PWM pulse signal output by the singlechip, outputs a first level to the second control circuit according to the PWM pulse signal, and controls the switch circuit to be switched off through the second control circuit.

In an alternative form, the first control circuit includes: the single-chip microcomputer is connected with the power supply, the first capacitor is connected with the single-chip microcomputer, the other end of the single-chip microcomputer is connected with one end of the first resistor, the other end of the first resistor is connected with the anode of the first diode, the cathode of the first diode is connected with the first end of the first transistor, the second end of the first transistor is grounded, and the third end of the first transistor is connected with the input end of the second control circuit.

In an optional manner, the first control circuit further includes a second capacitor and a second resistor, the second resistor is connected between the first terminal and the second terminal of the first transistor, and the second capacitor is connected in parallel to both ends of the second resistor.

In an optional manner, the first control circuit further includes a second diode, a cathode of the second diode is connected to the other end of the first resistor, and an anode of the second diode is connected to the second end of the first transistor.

In an optional manner, the second control circuit includes a second transistor, a first end of the second transistor is connected to the third end of the first transistor and the single chip, a second end of the second transistor is grounded, and a third end of the second transistor is connected to the switch circuit.

In an optional manner, the second control circuit further includes: one end of the third resistor is connected with the third end of the first transistor and the single chip microcomputer, the other end of the third resistor is connected with the first end of the second transistor, and the fourth resistor is connected between the first end and the second end of the second transistor.

In an optional manner, the first transistor and the second transistor are NPN triodes, the first terminal is a base of the NPN triode, the third terminal is an emitter of the NPN triode, and the third terminal is a collector of the NPN triode.

In an alternative form, the switching circuit includes: the first end of the third transistor is connected with the third end of the second transistor, the second end of the third transistor is connected with the power supply, the third end of the third transistor is a positive output end, the third capacitor is connected with the fourth capacitor in parallel, one end of the third capacitor is connected with the power supply, and the other end of the third capacitor is grounded and is a negative output end.

In an optional manner, the switch circuit further includes a fifth resistor and a sixth resistor, the fifth resistor is connected between the first terminal and the second terminal of the third transistor, and the sixth resistor is connected between the first terminal of the third transistor and the third terminal of the second transistor.

In an optional manner, the third transistor is an enhancement P-MOS transistor, a first end of the third transistor is a gate, a second end of the third transistor is a source, and a third end of the third transistor is a drain.

The utility model discloses prevent on-off control protection circuit of malfunction includes: the circuit comprises a first control circuit, a second control circuit and a switch circuit; the input end of the first control circuit is connected with the single chip microcomputer, the output end of the first control circuit is connected with the input end of the second control circuit, the input end of the second control circuit is also connected with the single chip microcomputer, and the output end of the second control circuit is connected with the switch circuit; when in misoperation, the first control circuit receives the PWM pulse signal output by the singlechip, outputs a first level to the second control circuit according to the PWM pulse signal, and controls the switching circuit to be switched off through the second control circuit, so that the device can be prevented from being damaged by the misoperation, the reliability of the product is improved, and the safety protection cost of the product can be reduced.

The foregoing is only an overview of the embodiments of the present invention, and in order to make the technical means of the embodiments of the present invention more clearly understood, the embodiments of the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the embodiments of the present invention is given.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 shows a schematic structural diagram of a switch control protection circuit for preventing a malfunction according to an embodiment of the present invention;

fig. 2 shows a schematic circuit diagram of a first control circuit provided by an embodiment of the present invention;

fig. 3 shows a schematic circuit diagram of a second control circuit provided by the embodiment of the present invention;

fig. 4 is a circuit diagram of a switching circuit provided by an embodiment of the present invention;

fig. 5 shows a complete circuit schematic diagram of the switch control protection circuit for preventing malfunction according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Fig. 1 shows the structure schematic diagram of the switch control protection circuit for preventing malfunction provided by the embodiment of the present invention, as shown in fig. 1, the switch control protection circuit 10 for preventing malfunction includes: a first control circuit 11, a second control circuit 12, and a switch circuit 13; the input end of the first control circuit 11 is connected with the single chip microcomputer MCU, the output end of the first control circuit is connected with the input end of the second control circuit 12, the input end of the second control circuit 12 is also connected with the single chip microcomputer MCU, and the output end of the second control circuit 12 is connected with the switch circuit 13; during false operation, the first control circuit 11 receives a PWM pulse signal output by the MCU, outputs a first level to the second control circuit 12 according to the PWM pulse signal, and controls the switch circuit 13 to be turned off through the second control circuit 12, so as to prevent false operation, and prevent the switch circuit 13 from being turned on incompletely for a short time to increase power consumption and damage devices during initialization of the MCU. The MCU at least comprises a positive power supply end and a negative power supply end, wherein the positive power supply end is connected with a power supply voltage VDD, and the negative power supply end is grounded GND.

In the embodiment of the present invention, as shown in fig. 2, the first control circuit 11 includes: first electric capacity C1, first resistance R1, first diode D1 and first transistor Q1, first electric capacity C1's one end with single-chip microcomputer MCU connects, the other end with the one end of first resistance R1 is connected, the other end of first resistance R1 with the anode of first diode D1 is connected, the negative pole of first diode D1 with the first end of first transistor Q1 is connected, the second end ground connection GND of first transistor Q1, the third terminal of first transistor Q1 with the input of second control circuit 12 is connected. The PWM pulse signal output by the MCU is converted into an ac signal through the first capacitor C1, rectified through the first diode D1, and transmitted to the first transistor Q1, and the control signal P2 is output from the third terminal of the first transistor Q1 and transmitted to the second control circuit 12. The first resistor R1 is a current limiting resistor to prevent excessive current.

The first control circuit 11 further includes a second capacitor C2, a second resistor R2, and a second diode D2, wherein the second resistor R2 is connected between the first terminal and the second terminal of the first transistor Q1, and the second capacitor C2 is connected in parallel to two terminals of the second resistor R2. The cathode of the second diode D2 is connected to the other end of the first resistor R1, and the anode of the second diode D2 is connected to the second end of the first transistor Q1. The second capacitor C2 is a filter capacitor for converting the ac signal into a dc high level signal. The second resistor R2 is used for controlling a voltage difference between the first terminal and the second terminal of the first transistor Q1 to be greater than a threshold voltage when the PWM pulse signal is input to the input terminal of the first control circuit 11, so as to ensure that the first transistor Q1 operates in the amplification region. The second diode D2 constitutes an off discharge loop for the first transistor Q1.

In the embodiment of the present invention, as shown in fig. 3, the second control circuit 12 includes a second transistor Q2, the first end of the second transistor Q2 is connected to the third end of the first transistor Q1 and the MCU, the second end of the second transistor Q2 is grounded GND, and the third end of the second transistor Q2 is connected to the switch circuit 13.

The second control circuit 12 further includes: a third resistor R3 and a fourth resistor R4, one end of the third resistor R3 is connected to the third end of the first transistor Q1 and the MCU, the other end is connected to the first end of the second transistor Q2, and the fourth resistor R4 is connected between the first end and the second end of the second transistor Q2. The third resistor R3 has the same function as the first resistor R1 of the first control circuit 11, and the fourth resistor R4 has the same function as the second resistor R2 of the first control circuit 11, which will not be described herein again.

In the embodiment of the present invention, as shown in fig. 4, the switch circuit 13 includes: a third capacitor C3, a fourth capacitor C4 and a third transistor Q3, wherein a first end of the third transistor Q3 is connected to the third end of the second transistor Q2, a second end of the third transistor Q3 is connected to the power supply VIN, the third end is a positive output end V +, the third capacitor C3 is connected to the fourth capacitor C4 in parallel, one end of the third capacitor C is connected to the power supply VIN, and the other end of the third capacitor C4 is connected to the ground GND and is a negative output end V-. The third capacitor C3 and the fourth capacitor C4 are output filter capacitors.

The switch circuit 13 further includes a fifth resistor R5 and a sixth resistor R6, the fifth resistor R5 is connected between the first terminal and the second terminal of the third transistor Q3, and the sixth resistor R6 is connected between the first terminal of the third transistor Q3 and the third terminal of the second transistor Q2. The fifth resistor R5 and the sixth resistor R6 are voltage dividing resistors for dividing the voltage of the power source VIN.

In the embodiment of the utility model, the embodiment of the utility model provides a prevent switch control protection circuit's of malfunction complete circuit diagram is shown in fig. 5, first transistor Q1 with second transistor Q2 is the NPN triode, first end does the base of NPN triode, the third end does the projecting pole of NPN triode, the third end does the collecting electrode of NPN triode. The third transistor Q3 is an enhancement P-MOS transistor, the first terminal of the third transistor Q3 is a gate (G) electrode, the second terminal is a source (S) electrode, and the third terminal is a drain (D) electrode. The third transistor Q3 is an output power PMOS transistor.

In practical situations, the MCU is not a completely ideal device, and before initialization, each pin has an uncontrolled state of tens of uS, and the IO port has an instantaneous peak voltage of 1-2V, which may trigger the second transistor Q2 to turn on. The embodiment of the utility model provides an in, singlechip MCU's PWM mouth output PWM pulse signal this moment converts alternating current signal into through first electric capacity C1, after first resistance R1 current-limiting, carries out the rectification through first diode D1, becomes direct current high level letter with alternating current signal after filtering through second electric capacity C2, and first transistor Q1 switches on. The second diode D2 now acts as a turn-off discharge loop for the first transistor Q1. After the first transistor Q1 is turned on, the control signal P2 outputted from the collector is pulled to a low level, and the second transistor Q2 is turned off. The gate of the third transistor Q3 has no loop to the ground, and the third transistor Q3 is turned off, so that malfunction can be prevented, the problem that the device is damaged when power consumption is increased due to the fact that the third transistor Q3 is turned on incompletely for a short time when malfunction occurs is avoided, the reliability of the product can be improved, and the safety protection cost of the product is reduced.

When the initialization of the MCU is completed, the IO port of the MCU detects that the battery pack (not shown) connected to the positive and negative output terminals of the third transistor Q3 is connected and the voltage of the battery pack is within the normal charging range, the MCU controls the PWM port to close, and the first transistor Q1 is turned off. The IO port of the MCU outputs high level to control the second transistor Q2 to be conducted to the ground, the collector of the second transistor Q2 outputs low level, the power supply VIN is divided by the fifth resistor R5 and the sixth resistor R6 to enable the G electrode of the third transistor Q3 to generate level to the ground, the negative differential voltage generated between the G electrode of the third transistor Q3 and the power supply VIN is smaller than the threshold voltage of the third transistor Q3, and the third transistor Q3 is conducted, so that the normal charging of equipment such as a rear-end battery pack is completed. The embodiment of the utility model provides a through the design of the on-off control protection circuit who adopts to prevent the malfunction, do not produce the secondary damage to rear end battery package and equipment, reduce the protection design cost of product, provide the product reliability, be favorable to improving the comprehensive competitiveness of product.

The utility model discloses prevent on-off control protection circuit 10 of malfunction includes: a first control circuit 11, a second control circuit 12, and a switch circuit 13; the input end of the first control circuit 11 is connected with the single chip microcomputer MCU, the output end of the first control circuit is connected with the input end of the second control circuit 12, the input end of the second control circuit 12 is also connected with the single chip microcomputer MCU, and the output end of the second control circuit 12 is connected with the switch circuit 13; when in misoperation, the first control circuit 11 receives the PWM pulse signal output by the MCU, outputs a first level to the second control circuit 12 according to the PWM pulse signal, and controls the switch circuit 13 to be switched off through the second control circuit 12, so that the device can be prevented from being damaged by the misoperation, the reliability of the product is improved, and the safety protection cost of the product can be reduced.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the embodiments of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: rather, the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Moreover, those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names. The steps in the above embodiments should not be construed as limiting the order of execution unless specified otherwise.

Claims

1. A switch control protection circuit (10) that prevents false actions, the switch control protection circuit (10) comprising: a first control circuit (11), a second control circuit (12), and a switch circuit (13); the input end of the first control circuit (11) is connected with a single chip Microcomputer (MCU), the output end of the first control circuit is connected with the input end of the second control circuit (12), the input end of the second control circuit (12) is also connected with the MCU, and the output end of the second control circuit (12) is connected with the switch circuit (13); when the circuit is in misoperation, the first control circuit (11) receives the PWM pulse signal output by the single chip Microcomputer (MCU), outputs a first level to the second control circuit (12) according to the PWM pulse signal, and controls the switch circuit (13) to be switched off through the second control circuit (12).

2. The switch-controlled protection circuit (10) according to claim 1, wherein the first control circuit (11) comprises: first electric capacity (C1), first resistance (R1), first diode (D1) and first transistor (Q1), the one end of first electric capacity (C1) with singlechip (MCU) is connected, the other end with the one end of first resistance (R1) is connected, the other end of first resistance (R1) with the anode of first diode (D1) is connected, the negative pole of first diode (D1) with the first end of first transistor (Q1) is connected, the second end ground connection (GND) of first transistor (Q1), the third terminal of first transistor (Q1) with the input of second control circuit (12) is connected.

3. The switch-controlled protection circuit (10) of claim 2, wherein the first control circuit (11) further comprises a second capacitor (C2) and a second resistor (R2), the second resistor (R2) being connected between the first terminal and the second terminal of the first transistor (Q1), the second capacitor (C2) being connected in parallel across the second resistor (R2).

4. The switch-controlled protection circuit (10) according to claim 2, wherein the first control circuit (11) further comprises a second diode (D2), a cathode of the second diode (D2) being connected to the other end of the first resistor (R1), an anode of the second diode (D2) being connected to the second end of the first transistor (Q1).

5. The switch-controlled protection circuit (10) according to claim 2, characterized in that the second control circuit (12) comprises a second transistor (Q2), a first terminal of the second transistor (Q2) being connected to the third terminal of the first transistor (Q1) and to the single-chip Microcomputer (MCU), a second terminal of the second transistor (Q2) being connected to Ground (GND), a third terminal of the second transistor (Q2) being connected to the switch circuit (13).

6. The switch-controlled protection circuit (10) of claim 5, wherein the second control circuit (12) further comprises: a third resistor (R3) and a fourth resistor (R4), one end of the third resistor (R3) is connected to the third terminal of the first transistor (Q1) and the single chip Microcomputer (MCU), the other end is connected to the first terminal of the second transistor (Q2), and the fourth resistor (R4) is connected between the first terminal and the second terminal of the second transistor (Q2).

7. The switch-controlled protection circuit (10) of claim 5, wherein the first transistor (Q1) and the second transistor (Q2) are NPN transistors, the first terminal is a base of the NPN transistor, the third terminal is an emitter of the NPN transistor, and the third terminal is a collector of the NPN transistor.

8. The switch-controlled protection circuit (10) according to claim 5, wherein the switching circuit (13) comprises: the first end of the third transistor (Q3) is connected with the third end of the second transistor (Q2), the second end is connected with a power supply (VIN), the third end is a positive output end, the third capacitor (C3) is connected with the fourth capacitor (C4) in parallel, one end is connected with the power supply (VIN), and the other end is Grounded (GND) and is a negative output end.

9. The switch-controlled protection circuit (10) of claim 8, wherein the switch circuit (13) further comprises a fifth resistor (R5) and a sixth resistor (R6), the fifth resistor (R5) being connected between the first and second terminals of the third transistor (Q3), the sixth resistor (R6) being connected between the first terminal of the third transistor (Q3) and the third terminal of the second transistor (Q2).

10. The switch-controlled protection circuit (10) of claim 8, wherein the third transistor (Q3) is an enhancement P-MOS transistor, and the first terminal of the third transistor (Q3) is a gate, the second terminal is a source, and the third terminal is a drain.