CN210742494U - Four-way-belt ultra-wideband imaging radar system for shallow foreign matter detection - Google Patents
Four-way-belt ultra-wideband imaging radar system for shallow foreign matter detection Download PDFInfo
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Abstract
The utility model relates to a four-way belt ultra wide band imaging radar system for shallow foreign matter detection, which comprises a radar host and an antenna array, wherein the antenna array comprises a plurality of groups of antenna units connected in series; the radar host comprises a battery management unit, a display control unit, a multi-path time base control unit and a data acquisition and processing unit. The multi-channel time base control unit generates a trigger signal of a multi-channel antenna and starts the sampling and holding of the receiving antenna array, and the multi-channel time base control unit comprises an FPGA module, a delay circuit and a multi-channel gating switch; the data acquisition processing unit is used for multichannel data acquisition, data preprocessing and data imaging, and comprises: the device comprises a CPLD module, an encoder, an A/D conversion module, a first data processing module and a second data processing module. The utility model adopts the cascade antenna array, which can perform large-area detection; the system is provided with a plurality of sampling channels, and a plurality of radar images can be obtained through one-time scanning; the data acquisition and processing unit adopts a dual-processor mode, the operational capability of the system is greatly improved, and data imaging can be displayed in real time.
Description
Technical Field
The utility model relates to a ground penetrating radar especially relates to a radar system that is used for cross-band ultra wide band formation of image of shallow foreign matter detection.
Background
At present, the electromagnetic wave principle is utilized to carry out the structural inspection of buildings in shallow media, the flaw detection of buildings, the thickness detection of reinforcing steel bar protection layers and the security inspection detection, and the instruments mainly comprise a ground penetrating radar and a millimeter wave through-wall radar. The working frequency band of the millimeter wave through-wall radar is concentrated at 30 GHz-300 GHz, the resolution is high, but the penetration capability is poor, and the detection depth of a common concrete medium is less than 5 cm; compared with millimeter wave radar, the ground penetrating radar has the working frequency band concentrated in 0.5 GHz-3 GHz and high penetrating power, and is particularly suitable for detecting shallow foreign matters within m level. Traditional single probe ground penetrating radar instrument detection efficiency is lower, and is lower to overlapping about multilayer reinforcing bar etc. and buries the thing resolution ratio underground, to the large tracts of land survey, needs the repeated scanning, and data uniformity is relatively poor, and formation of image needs the aftertreatment, causes that data processing time is long and lags behind, and the data processing result can not show in real time.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that a radar system that is applicable to large tracts of land and surveys, but the cross-belt ultra wide band formation of image that is used for shallow foreign matter to survey in real time is provided.
In order to solve the technical problem, the technical scheme of the utility model is that: a radar system of four-way belt ultra wide band imaging for shallow foreign matter detection comprises a radar host and an antenna array, wherein the antenna array comprises a plurality of groups of antenna units, transmitting antennas of the antenna units are connected in series, and receiving antennas of the antenna units are connected in series;
the radar host includes:
the battery management unit is electrically connected with the battery and provides a matching power supply for the radar system;
the display control unit is used for displaying the control data and the data imaging result of the radar system in real time;
the multi-channel time base control unit is used for generating trigger signals of multi-channel antennas and starting the sampling and holding of a receiving antenna array, and comprises the following components:
the FPGA module is connected with a clock chip and used for generating trigger signals of the multi-path antenna and sequentially triggering the plurality of transmitting antennas or receiving antennas in one sampling period;
the delay circuit comprises a delay shift chip and is used for ensuring the synchronization of trigger signals, and the delay circuit is connected with a data port of the FPGA module and is used for acquiring delay increment;
the multi-path gating switch comprises a group of transmitting gating switches for controlling the transmitting antennas and a group of receiving gating switches for controlling the receiving antennas, wherein the transmitting gating switches and the receiving gating switches are respectively and correspondingly connected with one transmitting antenna or one receiving antenna of the antenna array, and the transmitting gating switches and the receiving gating switches respond to the trigger signals sent by the FPGA module and are switched on and start the corresponding transmitting antennas or the corresponding receiving antennas in a specific time period in the sampling period;
the data acquisition processing unit is used for multichannel data acquisition and data preprocessing, and positioning and imaging different echo time delays of a target path according to the antenna array, and comprises: the system comprises a CPLD module, an encoder, an A/D conversion module, a first data processing module and a second data processing module, wherein the encoder, the A/D conversion module, the first data processing module and the second data processing module are all electrically connected with the CPLD module;
the CPLD module receives a trigger signal of the encoder and controls starting of acquisition of echo data or data processing;
the A/D conversion module responds to the control signal of the CPLD module, acquires the echo data and converts the echo data into a digital signal;
the second data processing module reads the conversion data of the A/D conversion module through a serial port and preprocesses the conversion data;
the first data processing module receives the control signal sent by the FPGA module, acquires the preprocessed data of the second data processing unit through a data port, performs algorithm processing on the preprocessed data, and sends the result to the display control unit.
As a preferred technical scheme, the clock chip, the delay shift chip and the multi-path gating switch all adopt LVPECL level chips, the FPGA module is electrically connected with the clock chip, the delay shift chip and the multi-path gating switch through level conversion circuits, and the level conversion circuits convert TTL levels of output signals of the FPGA module into LVPECL levels.
As a preferable technical solution, the multiple-way gate switch is further electrically connected to a driver, and the driver amplifies and shapes the trigger signal of the LVPECL level output by the multiple-way gate switch and then transmits the trigger signal to the transmitting antenna or the receiving antenna.
As a preferred technical solution, the display control unit is a human-computer interaction device, and the first data processing module is connected to the human-computer interaction device through an ethernet interface.
As a preferred technical solution, the first data processing module and the second data processing module are both DSPs.
Since the technical scheme is used, the beneficial effects of the utility model are that: the utility model adopts the antenna array formed by connecting a plurality of groups of antennas in series, which can carry out large-area detection; the consistency of trigger signals is ensured through the multi-channel time base control unit, a plurality of gating switches can be triggered in a periodic time division manner, a plurality of radar images can be obtained through one-time scanning, and the scanning times are reduced; because the system is designed and processed with large data volume and high data processing correlation, the data acquisition and processing unit adopts a dual-processor mode, the operational capability of the system is greatly improved, the data processing speed is high, the echo data can be directly processed through the dual-processor without being exported, and the data imaging is displayed in the display control unit in real time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a system block diagram of an embodiment of the present invention;
FIG. 2 is a functional block diagram of a multi-way time base control unit;
FIG. 3 is a control timing diagram of channel scanning;
FIG. 4 is a functional block diagram of a data acquisition processing unit;
FIG. 5 is a flow chart of a processing algorithm of the data acquisition processing unit;
FIG. 6 is a schematic diagram of the connection of an antenna array.
Detailed Description
As shown in fig. 1, a four-way ultra-wideband imaging radar system for shallow foreign object detection comprises a radar host and an antenna array, wherein the antenna array comprises a plurality of groups of antenna units, transmitting antennas of the antenna units are connected in series, and receiving antennas of the antenna units are connected in series;
the radar host computer includes: the radar system comprises a battery management unit, a display control unit, a multi-channel time base control unit and a data acquisition and processing unit, wherein the battery management unit is electrically connected with a battery and provides a matching power supply for the radar system; the multi-channel time base control unit is used for generating a trigger signal of a multi-channel antenna and starting the sampling and holding of the receiving antenna array; the data acquisition and processing unit is used for acquiring multichannel data and preprocessing the data, positioning and imaging different echo time delays of a target path according to the antenna array, and the display control unit is used for displaying control data of the radar system and a data imaging result in real time; the antenna array transmits signals to a target body at different positions and receives reflected signals of different paths at the same time, and echoes of all the antennas are connected in series through a switch and are sent to the data acquisition and processing unit.
The power management unit provides energy for the equipment, the built-in lithium ion battery provides input, various voltages required in the equipment are provided by using the power integrated chip, and an NMOS reverse prevention and transient voltage suppression protection circuit is preferably adopted to ensure the stable operation of the system. When the switch key is pressed down, the control chip of the power management unit controls each unit to be powered on at a certain delay interval after detecting a starting signal, detects the electric quantity of the battery of the host machine through an I2C port at regular time, and generates an alarm when the electric quantity is less than 5%; when the switch key is lifted, the singlechip detects a shutdown signal to control each unit to power off.
A multi-way time base control unit comprising:
the FPGA module is connected with a clock chip and used for generating trigger signals of the multi-path antenna and sequentially triggering the plurality of transmitting antennas or receiving antennas in one sampling period;
the delay circuit comprises a delay shift chip and is used for ensuring the synchronization of the trigger signals, and the delay circuit is connected with a data port of the FPGA module and is used for acquiring delay increment;
the multi-path gating switch comprises a group of transmitting gating switches for controlling transmitting antennas and a group of receiving gating switches for controlling receiving antennas, wherein the transmitting gating switches and the receiving gating switches are respectively and correspondingly connected with one transmitting antenna or one receiving antenna of the antenna array, and the transmitting gating switches and the receiving gating switches respond to trigger signals sent by the FPGA module and are switched on and start the corresponding transmitting antennas or the corresponding receiving antennas at a specific time period in a sampling period.
In the present embodiment, as shown in fig. 2 and fig. 3, the multi-channel time base control unit adopts a track scanning alternation, multi-channel serial cascade array design.
And the multi-channel time base control unit encodes the transmitting trigger signal and the receiving trigger signal of each channel antenna according to preset working parameters and the sequence of the recording channels to form a serial trigger signal sequence, and the serial trigger signal sequence is sequentially sent to each antenna after being switched by a switch. The multi-channel time base control unit consists of an FPGA chip, a delay circuit, a multi-channel switch circuit and a driver.
The FPGA receives parameter commands sent by the data acquisition and processing unit through the SPI serial port, the parameter commands comprise radar working parameters such as channel number, time window, scanning rate, signal position and sampling point number, and control logics such as delay chip delay data control, trigger signal coding and radar channel switching signals are completed in the FPGA. In this embodiment, the number of channels is 4.
The control logic is embodied as follows:
firstly, realizing SPI receiving and sending interface communication;
secondly, setting a register and storing the receiving parameters;
and thirdly, setting a trigger signal code according to the received channel number command, for example, setting the first channel trigger signal code to 0001, the second channel trigger signal code to 0010, the third channel trigger signal code to 0100, and the fourth channel trigger signal code to 1000.
Fourthly, generating a trigger pulse signal with corresponding frequency in a frequency division mode according to parameters such as a time window, a scanning rate, a signal position, a sampling point number and the like;
and fifthly, realizing the serial connection of the four groups of trigger pulse signals according to the sequence from 1 to 4, and synchronously generating the switch gating signals.
In order to ensure digital controllability and strict time synchronization of the trigger signals, a clock and a delay shift chip of the multi-channel time base control circuit are realized by adopting a low-swing and quick LVPECL level chip. Because the LVPECL circuit has larger power consumption, if each channel respectively adopts an independent delay circuit, the heat productivity is higher, and the LVPECL circuit is not suitable for handheld equipment, so that four channels share one delay circuit and adopt a time-sharing working mode. The multi-path receiving pulses output by the FPGA are connected in series on a data line, and under the action of a delay circuit, accurate and uniform delay is carried out by taking delta t as a delay increment until the delay within a set time window range is finished; and the delay increment delta t of the delay circuit is written in by the FPGA through a data line. In order to match the level and impedance of the output signal, a level conversion circuit is used for realizing the switching from the TTL level to the LVPECL level, and the TTL level of the output signal of the FPGA module is converted into the LVPECL level.
With reference to the timing sequence of fig. 3, the multi-channel switching switch circuit is composed of a group of transmitting gating switches and a group of receiving gating switches, each group of switches is a 1:4 LVPECL switch switching chip, and the information of the switching switches between the channels is controlled by the FPGA programming. The switching of the multi-path selector switch is realized as follows: when the rising edge of the first FSCAN arrives, the FPGA generates an antenna 1 gating signal, and the transmitting gating switch and the receiving gating switch are switched to a channel 1 to be output simultaneously; when the rising edge of the second FSCAN arrives, the FPGA generates an antenna 2 gating signal, and the transmitting gating switch and the receiving gating switch are switched to 2 channels for output; when the rising edge of the third FSCAN comes, the FPGA generates an antenna 3 gating signal, and the transmitting gating switch and the receiving gating switch are switched to 3 channels to be output simultaneously; when the rising edge of the fourth FSCAN comes, the FPGA generates an antenna 4 gating signal, and the transmitting gating switch and the receiving gating switch are switched to 4 channels to be output simultaneously; and circulating in sequence, wherein the number of the cascade antennas can be randomly set from 1 to 4, and the logic rules of transmitting and receiving the pulse gating control signal of each cascade antenna are the same.
In this embodiment, the trigger signal and the transmission trigger signal are both differential LVPECL signals, and since the swing amplitude of the LVPECL signal is small and the transmission loss of the long line is large, the multi-path gate switch amplifies and shapes the output trigger signal through the driver pair, preferably, the driver is a pulse driving circuit, and the pulse driving circuit amplifies and shapes the trigger signal to form trigger pulse signals of about 15V, which are respectively sent to the antenna end.
As shown in fig. 4 and 5, the data acquisition and processing unit is used for multichannel data acquisition and data preprocessing, positioning and imaging different echo time delays of a target path according to an antenna array, and receives command parameters of the display control unit through an ethernet interface, and includes: the CPLD module, the encoder, the A/D conversion module, the first data processing module and the second data processing module, in this embodiment, the first data processing module and the second data processing module are both DSPs.
The encoder, the A/D conversion module, the first data processing module DSP1 and the second data processing module DSP2 are electrically connected with the CPLD module, the A/D conversion module is connected with the DSP1 through serial ports, the data ports of the DSP1 and the DSP1 are connected, and the DSP1 is electrically connected with the FPGA module through an SPI interface. The DSP1 is connected with the display control unit through an Ethernet interface, and also can be connected with an upper computer or a man-machine interaction device through the Ethernet interface, and the upper computer or the man-machine interaction device is used as a display device to realize radar system control, data real-time display and data imaging result display.
In this embodiment, the CPLD module receives a trigger signal of the encoder, controls the start of acquisition of echo data or data processing, and completes data acquisition and processing in a coordinated manner, and the a/D conversion module completes digital conversion of the echo data by using a 16-bit high-speed a/D chip with a 1.33Msps conversion rate, thereby realizing sampling of echo signals of the 4-channel antenna. The echoes of the four antennas are sent to the A/D conversion module in a serial mode. Under the control of the CPLD, the A/D acquires a group of antenna array echo signals once when the external encoder trigger signals are triggered, and the group of antenna array echo signals are sent to the DSP2 through a serial port.
The DSP2 reads the A/D conversion data through the serial port, and preprocesses the multi-path echo data, and the preprocessed data are sent to the DSP 1. The DSP1 receives the preprocessed data sent by the DSP2, performs algorithm processing such as offset, zero point correction and data imaging of multi-path echo data, and transmits the processed result to the display control unit through the Ethernet interface. The DSP1 also receives command parameters of an upper computer or man-machine interaction equipment through the Ethernet interface, sends command information to the DSP2 through the data port, and sends parameters required by radar work to the time base control unit through the SPI.
And (3) realizing three-dimensional slice imaging, wherein a C-scan scanning mode is adopted for data acquisition, namely, in the xoy plane, detection is carried out along a latticed measuring line, and acquisition of a certain area is completed. As shown in fig. 4 and 5, the DSP2 is responsible for preprocessing such as multi-channel data acquisition, zero point correction, data filtering, background elimination, and auto gain, and needs to store a large amount of data, which is far from being satisfied by the internal storage space of the DSP2, so that a 64MB piece of SDRAM is overlapped as an external data storage to store the original data and the preprocessed data, and occupies the CE0 space of the DSP 2. The external FLASH is used as a program memory, and after the system is powered on, the user program stored in the external FLASH is guided to the high-speed data memory to run, and occupies the CE1 space of the DSP2 together with the CPLD. The DSP1 is responsible for data migration, data interpolation, data fusion and slice extraction processing, and takes into account the data type and the complexity of a processing algorithm, two 64MB SDRAMs are adopted as external data memories, and respectively occupy the space of CE0 and CE2 of the DSP 1. FLASH, as an external program memory, occupies CE1 space of DSP1 together with CPLD.
As shown in fig. 6, this embodiment uses 4 independent 2000MHz antennas to form an antenna array, four groups of antennas are arranged on the same plane, the centers of the antennas are on a straight line, and they are arranged in a straight line, and the adjacent antennas are connected in series by a series line to form the antenna array. The serial connection adopts a cable mode, and can also select a board-level cascaded butt joint socket to transmit the transmitting trigger signal, the receiving trigger signal, the synchronous signal, the coding signal, the power signal and the echo signal of the next level.
The size of a single antenna is 8cm multiplied by 8cm, 4 2000MHz antennas are sequentially arranged from left to right, and the midpoint of the 1 st 2000MHz antenna is the 1 st scanning measuring line, namely the measuring line 1; the midpoint of the 2 nd 2000MHz antenna is the 2 nd scanning test line, i.e. test line 2; the midpoint of the 3 rd 2000MHz antenna is a 3 rd scanning test line, namely test line 3; the midpoint of the 4 th 2000MHz antenna is the 4 th scan test line, test line 4. The spacing between the test lines was 8 cm.
The utility model discloses in, in the antenna array, can increase or reduce the antenna number or change the antenna type as required. The number of the cascade antennas can be set from 1 to N arbitrarily.
The basic principles, main features and advantages of the present invention have been shown and described above. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the foregoing embodiments and descriptions are provided only to illustrate the principles of the present invention without departing from the spirit and scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (5)
1. The utility model provides a radar system that is used for shallow foreign matter to survey cross area ultra wide band formation of image which characterized in that: the radar antenna array comprises a radar host and an antenna array, wherein the antenna array comprises a plurality of groups of antenna units, transmitting antennas of the antenna units are connected in series, and receiving antennas of the antenna units are connected in series;
the radar host includes:
the battery management unit is electrically connected with the battery and provides a matching power supply for the radar system;
the display control unit is used for displaying the control data and the data imaging result of the radar system in real time;
the multi-channel time base control unit is used for generating trigger signals of multi-channel antennas and starting the sampling and holding of a receiving antenna array, and comprises the following components:
the FPGA module is connected with a clock chip and used for generating trigger signals of the multi-path antenna and sequentially triggering the plurality of transmitting antennas or receiving antennas in one sampling period;
the delay circuit comprises a delay shift chip and is used for ensuring the synchronization of trigger signals, and the delay circuit is connected with a data port of the FPGA module and is used for acquiring delay increment;
the multi-path gating switch comprises a group of transmitting gating switches for controlling the transmitting antennas and a group of receiving gating switches for controlling the receiving antennas, wherein the transmitting gating switches and the receiving gating switches are respectively and correspondingly connected with one transmitting antenna or one receiving antenna of the antenna array, and the transmitting gating switches and the receiving gating switches respond to the trigger signals sent by the FPGA module and are switched on and start the corresponding transmitting antennas or the corresponding receiving antennas in a specific time period in the sampling period;
the data acquisition processing unit is used for multichannel data acquisition and data preprocessing, and positioning and imaging different echo time delays of a target path according to the antenna array, and comprises: the system comprises a CPLD module, an encoder, an A/D conversion module, a first data processing module and a second data processing module, wherein the encoder, the A/D conversion module, the first data processing module and the second data processing module are all electrically connected with the CPLD module;
the CPLD module receives a trigger signal of the encoder and controls starting of acquisition of echo data or data processing;
the A/D conversion module responds to the control signal of the CPLD module, acquires the echo data and converts the echo data into a digital signal;
the second data processing module reads the conversion data of the A/D conversion module through a serial port and preprocesses the conversion data;
the first data processing module receives the control signal sent by the FPGA module, acquires the preprocessed data of the second data processing unit through a data port, performs algorithm processing on the preprocessed data, and sends the result to the display control unit.
2. The radar system for four-pass ultra-wideband imaging for shallow foreign object detection as recited in claim 1, wherein: the clock chip, the delay shifting chip and the multi-path gating switch all adopt LVPECL level chips, the FPGA module is respectively and electrically connected with the clock chip, the delay shifting chip and the multi-path gating switch through level conversion circuits, and the level conversion circuits convert TTL levels of output signals of the FPGA module into LVPECL levels.
3. The radar system for four-pass ultra-wideband imaging for shallow foreign object detection as recited in claim 2, wherein: the multi-channel gate switch is also electrically connected with a driver, and the driver amplifies and shapes the LVPECL level trigger signal output by the multi-channel gate switch and then sends the trigger signal to the transmitting antenna or the receiving antenna.
4. The radar system for four-pass ultra-wideband imaging for shallow foreign object detection as recited in claim 1, wherein: the display control unit is a human-computer interaction device, and the first data processing module is connected with the human-computer interaction device through an Ethernet interface.
5. The radar system for four-pass ultra-wideband imaging for shallow foreign object detection as recited in claim 1, wherein: the first data processing module and the second data processing module are both DSPs.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113093161A (en) * | 2021-03-22 | 2021-07-09 | Oppo广东移动通信有限公司 | Ultra-wideband device, test system and test method thereof |
| CN113204013A (en) * | 2021-04-19 | 2021-08-03 | 珠海上富电技股份有限公司 | High-resolution millimeter wave radar based on FPGA and signal processing method |
| WO2022227301A1 (en) * | 2021-04-30 | 2022-11-03 | 华为技术有限公司 | Radar system and terminal device |
| US11686841B2 (en) | 2021-04-30 | 2023-06-27 | Huawei Technologies Co., Ltd. | Radar system and terminal device |
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2019
- 2019-09-19 CN CN201921558897.4U patent/CN210742494U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113093161A (en) * | 2021-03-22 | 2021-07-09 | Oppo广东移动通信有限公司 | Ultra-wideband device, test system and test method thereof |
| CN113093161B (en) * | 2021-03-22 | 2024-05-24 | Oppo广东移动通信有限公司 | Ultra-wideband equipment, test system and test method thereof |
| CN113204013A (en) * | 2021-04-19 | 2021-08-03 | 珠海上富电技股份有限公司 | High-resolution millimeter wave radar based on FPGA and signal processing method |
| WO2022227301A1 (en) * | 2021-04-30 | 2022-11-03 | 华为技术有限公司 | Radar system and terminal device |
| US11686841B2 (en) | 2021-04-30 | 2023-06-27 | Huawei Technologies Co., Ltd. | Radar system and terminal device |
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