CN210690753U - Power supply chip test circuit integrating communication function - Google Patents
Power supply chip test circuit integrating communication function Download PDFInfo
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- CN210690753U CN210690753U CN201921458186.XU CN201921458186U CN210690753U CN 210690753 U CN210690753 U CN 210690753U CN 201921458186 U CN201921458186 U CN 201921458186U CN 210690753 U CN210690753 U CN 210690753U
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Abstract
The utility model discloses a power chip test circuit of integrated communication function, this circuit include logic tester, power chip peripheral circuit and be used for connecting the chip seat of the power chip that awaits measuring, logic tester and power chip peripheral circuit are connected, and logic tester and the examination of awaiting measuring power chip are connected and are communicated, the examination of awaiting measuring power chip and power chip peripheral circuit are connected. The utility model discloses a power chip test circuit accomplishes to be close to the power chip that awaits measuring with power chip peripheral circuit relatively, makes power chip's peripheral loop minimize, tests power chip peripheral circuit's output voltage and power chip's communication function simultaneously through the logic tester, because the IO of logic tester is more in quantity, can carry out multistation simultaneous testing. The utility model has the characteristics of efficiency of software testing is high, stability is good.
Description
[ technical field ] A method for producing a semiconductor device
The utility model relates to a power chip tests technical field, in particular to high and the good power chip test circuit of integrated communication function of stability of efficiency of software testing.
[ background of the invention ]
The power supply chip is mainly used for power supply conversion and is widely applied to various electronic devices. With the continuous improvement of the functions of electronic devices, the power supply chip generally integrates various modules with different functions, for example, a power supply chip integrating a communication function. The power supply chip directly influences the operation of electronic equipment, and the power supply chip on the market is usually realized by adopting an analog tester, and for the power supply chip with the integrated communication function, because the chip pins are more, the number of channels of the analog tester is limited, multi-station testing is difficult to realize, and the test communication function has limitation.
[ summary of the invention ]
The utility model aims to provide a power chip test circuit of integrated communication function that efficiency of software testing is high and stability is good.
The utility model provides a pair of integrated communication function's power chip test circuit, this circuit include logic tester, power chip peripheral circuit and be used for connecting the chip seat of the power chip that awaits measuring, logic tester and power chip peripheral circuit are connected, and logic tester and the examination of awaiting measuring power chip are connected and are communicated, the examination of awaiting measuring power chip and power chip peripheral circuit are connected.
The logic tester communicates with the power supply chip to be tested through I2C.
The logic tester is provided with a plurality of IO ports for controlling the enabling end of the power supply chip to be tested and detecting the output voltage of the peripheral circuit (20) of the power supply chip.
The power chip peripheral circuit comprises a first resistor R1, a second resistor R2, a first inductor L1, a first capacitor C1 and a second capacitor C2, wherein one end of the first resistor R1 is connected with one end of the second resistor R2 and a power chip to be tested respectively, the other end of the first resistor R1 is connected with one end of the first inductor L1, the anode of the first capacitor C1, one end of the second capacitor C2 and a logic tester respectively, the other end of the second resistor R2 is grounded, the other end of the first inductor L1 is connected with the power chip to be tested, and the cathode of the first capacitor C1 and the other end of the second capacitor C2 are grounded.
The power chip peripheral circuit comprises a third resistor R3, a fourth resistor R4, a fifth resistor R5, a second inductor L2, a third capacitor C3 and a fourth capacitor C4, wherein one end of the third resistor R3 is connected with one end of the fourth resistor R4 and a power chip to be tested respectively, the other end of the third resistor R3 is connected with one end of the second inductor L2, the anode of the third capacitor C3, one end of the fourth capacitor C4, one end of the fifth resistor R5 and a logic tester respectively, the other end of the fourth resistor R4 and the other end of the fifth resistor R5 are grounded, the other end of the second inductor L2 is connected with the power chip to be tested, and the cathode of the third capacitor C3 and the other end of the fourth capacitor C4 are grounded.
The power supply chip to be tested is provided with an I2C communication interface and a work enabling end.
A plurality of the circuits are integrated on the same circuit board.
The utility model has the advantages that: the utility model discloses a power chip test circuit accomplishes to be close to the power chip that awaits measuring with power chip peripheral circuit relatively, makes power chip's peripheral loop minimize, tests power chip peripheral circuit's output voltage and power chip's communication function simultaneously through the logic tester, because the IO of logic tester is more in quantity, can carry out multistation simultaneous testing. The utility model has the characteristics of efficiency of software testing is high, stability is good.
[ description of the drawings ]
Fig. 1 is a schematic block diagram of the present invention.
Fig. 2 is a peripheral circuit diagram of the power chip of the present invention.
Fig. 3 is a peripheral circuit diagram of another power chip according to the present invention.
Fig. 4 is a test flow chart of the present invention.
[ detailed description ] embodiments
The following examples are further to explain and supplement the present invention, and do not constitute any limitation to the present invention.
As shown in fig. 1 and fig. 2, the power chip testing circuit with integrated communication function of the present invention includes a logic tester 10, a power chip peripheral circuit 20 and a chip holder (not shown in the figure) for connecting a power chip 30 to be tested.
As shown in fig. 1, the logic tester 10 is connected to the power chip peripheral circuit 20 and the power chip 30 to be tested, and has a plurality of IO ports for controlling the enable terminal of the power chip 30 to be tested, testing whether the communication function of the power chip is normal, and testing whether the output voltage of the power chip peripheral circuit 20 is normal.
As shown in fig. 2, the power chip peripheral circuit 20 is connected to the logic tester 10 and the power chip 30 to be tested, and when the power chip 30 to be tested is in operation, the power chip peripheral circuit 20 outputs a voltage, the logic tester 10 reads the voltage through the IO port and determines whether the output voltage of the power chip to be tested is normal, it comprises a first resistor R1, a second resistor R2, a first inductor L1, a first capacitor C1 and a second capacitor C2, wherein, one end of the first resistor R1 is respectively connected with one end of the second resistor R2 and the feedback end of the power chip 30 to be tested, the other end of the first inductor is connected to one end of a first inductor L1, the anode of a first capacitor C1, one end of a second capacitor C2 and the IO port of the logic tester 10, the other end of a second resistor R2 is grounded, the other end of the first inductor L1 is connected to the switch output end of the power chip 30 to be tested, and the cathode of the first capacitor C1 and the other end of the second capacitor C2 are grounded. The first resistor R1 and the second resistor R2 form a voltage division circuit, a reference voltage is generated and is connected to a feedback end of the power supply chip 30 to be tested and used for adjusting output voltage, the first inductor L1 is a filter inductor, a direct current voltage is generated after a switch output end of the power supply chip 30 to be tested passes through the first inductor L1, the first capacitor C1 filters a low-frequency signal of the direct current voltage, the second capacitor C2 filters a high-frequency signal of the direct current voltage, the filtered direct current voltage is connected to an IO port of the logic tester 10, the logic tester 10 detects the direct current voltage, and whether the output voltage function of the power supply chip 30 to be tested is normal or not is judged.
As shown in fig. 3, in another embodiment, the power chip peripheral circuit 20 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a second inductor L2, a third capacitor C3 and a fourth capacitor C4, wherein one end of the third resistor R3 is connected to one end of the fourth resistor R4 and the feedback end of the power chip 30 to be tested, the other end of the third resistor R3 is connected to one end of the second inductor L2, the anode of the third capacitor C3, one end of the fourth capacitor C4, one end of the fifth resistor R5 and the IO port of the logic tester 10, the other end of the fourth resistor R4 and the other end of the fifth resistor R5 are grounded, the other end of the second inductor L2 is connected to the switch output end of the power chip 30 to be tested, and the cathode of the third capacitor C3 and the other end of the fourth capacitor C4 are grounded. The third resistor R3 and the fourth resistor R4 form a voltage divider circuit, generate a reference voltage to be connected to a feedback end of the power chip 30 to be tested, and adjust an output voltage, the second inductor L2 is a filter inductor, a dc voltage is generated at a switch output end of the power chip 30 to be tested after passing through the second inductor L2, the third capacitor C3 filters a low-frequency signal of the dc voltage, the fourth capacitor C4 filters a high-frequency signal of the dc voltage, the filtered dc voltage is connected to an IO port of the logic tester 10, the logic tester 10 detects the dc voltage, and determines whether the output voltage function of the power chip 30 to be tested is normal.
The power chip 30 to be tested is connected with the logic tester 10 and the power chip peripheral circuit 20, and is provided with an I2C communication interface and a work enabling terminal. When the enable terminal of the power supply chip 30 to be tested is not enabled, the power supply chip peripheral circuit 20 has no output voltage, and when the enable terminal of the power supply chip 30 to be tested is enabled, the power supply chip peripheral circuit 20 has output voltage.
Because the test circuit has simple structure and small volume, a plurality of circuits can be integrated on one circuit board, and the multi-station simultaneous test is realized, so that the test efficiency is high and the stability is good.
As shown in fig. 4, the testing process of the present invention is as follows:
s10, the logic tester 10 controls the enable terminal of the power chip 30 to be tested not to be enabled.
S20, the logic tester 10 detects and determines whether the power chip peripheral circuit 20 has an output voltage.
If the power chip peripheral circuit 20 has an output voltage indicating that the enable terminal of the power chip 30 to be tested has a fault, the logic tester 10 controls the manipulator to take out the fault chip, and the test is finished.
If the power chip peripheral circuit 20 has no output voltage, step S30 is executed.
S30, the logic tester 10 controls the enable terminal of the power chip 30 to be tested to enable.
S40, the logic tester 10 detects and judges whether the output voltage of the power chip peripheral circuit 20 is normal.
If the output voltage of the power chip peripheral circuit 20 is abnormal, which indicates that the power chip 30 to be tested has a fault, the logic tester 10 controls the manipulator to take out the fault chip, and the test is finished.
If the output voltage of the power chip peripheral circuit 20 is normal, the logic tester 10 communicates with the power chip 30 to be tested through the I2C communication interface.
S50, the logic tester 10 determines whether the communication of the power chip 30 to be tested is normal.
If the power supply chip 30 to be tested is not communicated normally, the logic tester 10 controls the manipulator to take out the fault chip, and the test is finished.
If the power supply chip 30 to be tested is in normal communication, the logic tester 10 controls the manipulator to take out the normal chip, and the test is finished.
Although the present invention has been described in connection with the above embodiments, the scope of the present invention is not limited thereto, and modifications, replacements, and the like to the above members are all within the scope of the claims of the present invention without departing from the concept of the present invention.
Claims (7)
1. The power chip test circuit with the integrated communication function is characterized by comprising a logic tester (10), a power chip peripheral circuit (20) and a chip holder for connecting a power chip (30) to be tested, wherein the logic tester (10) is connected with the power chip peripheral circuit (20), the logic tester (10) is connected with the power chip (30) to be tested and communicates with the power chip (30), and the power chip (30) to be tested is connected with the power chip peripheral circuit (20).
2. The integrated communication capable power supply chip test circuit according to claim 1, wherein the logic tester (10) communicates with the power supply chip (30) to be tested through I2C.
3. The power chip test circuit with integrated communication function according to claim 1, wherein the logic tester (10) is provided with a plurality of IO ports for controlling the enable terminal of the power chip (30) to be tested and detecting the output voltage of the power chip peripheral circuit (20).
4. The power chip test circuit with integrated communication function of claim 1, wherein the power chip peripheral circuit (20) comprises a first resistor R1, a second resistor R2, a first inductor L1, a first capacitor C1 and a second capacitor C2, one end of the first resistor R1 is connected to one end of a second resistor R2 and the power chip (30) to be tested, and the other end thereof is connected to one end of a first inductor L1, the anode of the first capacitor C1, one end of a second capacitor C2 and the logic tester (10), the other end of the second resistor R2 is grounded, the other end of the first inductor L1 is connected to the power chip (30) to be tested, and the cathode of the first capacitor C1 and the other end of the second capacitor C2 are grounded.
5. The power chip test circuit with integrated communication function as claimed in claim 1, wherein the power chip peripheral circuit (20) comprises a third resistor R3, a fourth resistor R4, a fifth resistor R5, a second inductor L2, a third capacitor C3 and a fourth capacitor C4, one end of the third resistor R3 is connected to one end of the fourth resistor R4 and the power chip (30) to be tested, and the other end is connected to one end of the second inductor L2, the anode of the third capacitor C3, one end of the fourth capacitor C4, one end of the fifth resistor R5 and the logic tester (10), respectively, the other end of the fourth resistor R4 and the other end of the fifth resistor R5 are grounded, the other end of the second inductor L2 is connected to the power chip (30) to be tested, and the cathode of the third capacitor C3 and the other end of the fourth capacitor C4 are grounded.
6. The integrated communication function power supply chip test circuit as recited in claim 1, wherein the power supply chip (30) to be tested is provided with an I2C communication interface and a work enabling terminal.
7. The integrated communication capable power chip test circuit of claim 1, wherein a plurality of the integrated communication capable power chip test circuits are integrated on the same circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921458186.XU CN210690753U (en) | 2019-09-04 | 2019-09-04 | Power supply chip test circuit integrating communication function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921458186.XU CN210690753U (en) | 2019-09-04 | 2019-09-04 | Power supply chip test circuit integrating communication function |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210690753U true CN210690753U (en) | 2020-06-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921458186.XU Active CN210690753U (en) | 2019-09-04 | 2019-09-04 | Power supply chip test circuit integrating communication function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210690753U (en) |
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2019
- 2019-09-04 CN CN201921458186.XU patent/CN210690753U/en active Active
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