CN210665871U

CN210665871U - Metering and insulation detector for direct current charging pile

Info

Publication number: CN210665871U
Application number: CN201921526005.2U
Authority: CN
Inventors: 黄健
Original assignee: Hangzhou Chuangrui New Energy Technology Co ltd
Current assignee: Hangzhou Chuangrui New Energy Technology Co ltd
Priority date: 2019-09-09
Filing date: 2019-09-09
Publication date: 2020-06-02
Anticipated expiration: 2029-09-09

Abstract

The utility model discloses a measurement and insulation detector for direct current fills electric pile belongs to electric automobile direct current and fills electric pile detection technical field. The power supply unit is connected with the control acquisition unit and the insulation detection unit, and the insulation detection unit is characterized by comprising an electric bridge driving module, a relay isolation module and a bus processing module which are connected with the control acquisition unit, wherein an insulation detection end is connected with the relay isolation module, and the electric bridge driving module and the relay isolation module are respectively connected with the bus processing module. The linearity is good, the anti-interference ability is strong, the number of separated components is small, the power consumption is relatively small, the processing of the metering chip on the voltage and the current is applied, and the requirements of the charging pile on the instantaneity and the precision of voltage and current collection are met. And secondly, the system adopts a testing principle of combining a balanced bridge and an unbalanced bridge, so that the problem that the balanced bridge cannot be detected when the positive bus and the negative bus are grounded simultaneously is avoided.

Description

Metering and insulation detector for direct current charging pile

Technical Field

The utility model relates to an electric automobile direct current fills electric pile and detects technical field, concretely relates to measurement and insulation detection appearance for direct current fills electric pile.

Background

Most photovoltaic at present, inverter, motor control fills electric pile bus current and gathers and mostly adopt, and the front end is put with fortune, and middle linear opto-coupler that adds, the mode collection that the back end was put with fortune, and this kind of mode linearity is not too good, relates to separation components and parts many moreover, and the consumption is also great relatively.

The existing method for detecting the insulation of the direct current system mainly comprises a bridge balance principle and a low-frequency detection principle, an insulation monitoring device realized according to the bridge balance principle is widely used, but the method cannot detect the condition that the insulation of the positive pole and the negative pole of the direct current system is equally reduced; even if the insulation monitoring device gives an alarm, the insulation resistance of the system to the ground cannot be directly obtained, the method for detecting the ground fault by using the low-frequency detection principle is a new method adopted in recent years, but the ground resistance which can be detected by the insulation monitoring device is limited by the distributed capacitance of the direct current system to the ground, low-frequency alternating current signals are easily interfered by the outside, and in addition, the injected low-frequency alternating current signals increase the voltage ripple coefficient of the direct current system.

Most of current charging pile bus current/voltage collection adopt linear opto-couplers, for example adopt HCNR200 and HCNR201, and the linearity of voltage transmission ratio is relatively poor.

SUMMERY OF THE UTILITY MODEL

Not enough to prior art, the utility model provides a measurement and insulation detection appearance for direct current fills electric pile.

The utility model provides a measurement and insulation detection appearance for direct current fills electric pile, includes electrical unit, control acquisition unit and insulation detection unit, and electrical unit is connected with control acquisition unit and insulation detection unit, insulation detection unit includes bridge drive module, relay isolation module, the generating line processing module who is connected with control acquisition unit, and insulation detection end is connected with relay isolation module, bridge drive module and relay isolation module are connected with generating line processing module respectively.

Furthermore, the bus processing module comprises a positive bus insulation processing module and a negative bus insulation processing module, the positive bus insulation processing module comprises a third equidirectional secondary voltage division circuit and a third voltage division circuit, a third following circuit, a third reverse circuit and a third reverse secondary voltage division circuit which are connected in sequence, and the third following circuit is connected with the third equidirectional secondary voltage division circuit; the negative bus insulation processing module comprises a fourth voltage division circuit, a fourth following circuit, a fourth reverse circuit and a fourth reverse secondary voltage division circuit which are sequentially connected.

Further, the bridge driving module comprises a driving chip U7, a triode Q1 and a triode Q2, and the control acquisition unit is connected with the input end of the driving chip U7 through the triode Q1; the control acquisition unit is connected with the input end of a driving chip U7 through a triode Q2, two negative input ends of the driving chip U7 are grounded AGND1, and the output end of the driving chip U7 is connected with the bus processing module.

Furthermore, the relay isolation module comprises a positive relay isolation module and a negative relay isolation module, the positive relay isolation module comprises a relay K1 and a triode Q3, the control acquisition unit is connected with the relay K1 through the triode Q3, and the positive insulation detection end is connected with the bus processing module through the relay K1; the negative relay isolation module comprises a relay K2 and a triode Q4, the control acquisition unit is connected with the relay K2 through the triode Q4, and the negative insulation detection end is connected with the bus processing module through the relay K2.

Furthermore, the metering device also comprises a metering unit, wherein the metering unit comprises a metering module, a photoelectric isolation module, a battery bus voltage conditioning module, a mains supply voltage conditioning module and a mains supply current conditioning module, the mains supply voltage conditioning module and the mains supply current conditioning module are connected with the metering module, the metering module is connected with the control acquisition unit through the photoelectric isolation module, and the battery bus voltage conditioning module is connected with the control acquisition unit.

Furthermore, the battery bus voltage conditioning module comprises a battery positive bus voltage conditioning module and a battery negative bus voltage conditioning module, the battery positive bus voltage conditioning module comprises a first equidirectional secondary voltage division circuit, and a first voltage division circuit, a first following circuit, a first reverse circuit and a first reverse secondary voltage division circuit which are sequentially connected, and the first following circuit is connected with the first equidirectional secondary voltage division circuit; the battery negative bus voltage conditioning module comprises a second voltage division circuit, a second following circuit, a second reverse circuit and a second reverse secondary voltage division circuit which are sequentially connected.

Furthermore, the detector also comprises a communication unit and a storage unit, and the communication module adopts an RS485 communication mode.

The differential input is adopted, the linearity is good, the anti-interference capability is strong, the number of separated components is small, the power consumption is relatively small, the voltage and current are processed by the metering chip, and the requirements of the charging pile on the real-time performance and the precision of voltage and current acquisition are met. And secondly, the system adopts a testing principle of combining a balanced bridge and an unbalanced bridge, so that the problem that the balanced bridge cannot be detected when the positive bus and the negative bus are grounded simultaneously is avoided.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a block diagram of a metering unit;

FIG. 3 is a block diagram of an insulation detecting unit;

FIG. 4 is a schematic circuit diagram of a first power conversion module;

FIG. 5 is a schematic circuit diagram of a second power conversion module;

FIG. 6 is a schematic diagram of a circuit for controlling the acquisition unit;

FIG. 7 is a schematic circuit diagram of a communication unit;

FIG. 8 is a schematic circuit diagram of a memory cell;

fig. 9 is a schematic diagram of a mains voltage and mains current acquisition circuit;

FIG. 10 is a schematic circuit diagram of a positive bus voltage conditioning module for a battery;

FIG. 11 is a schematic circuit diagram of a negative bus voltage conditioning module for a battery;

FIG. 12 is a schematic circuit diagram of a photo-isolation module;

FIG. 13 is a schematic circuit diagram of a bridge driver module;

FIG. 14 is a schematic circuit diagram of a relay isolation module and bus bar handling module;

FIG. 15 is a schematic diagram of a display module circuit;

wherein: 1-a power supply unit; 2-controlling the acquisition unit; 3-a storage unit; 4-a communication unit; 5-an insulation detection unit; 6-a metering unit; 7-a photoelectric isolation module; 8-a metering module; 9-mains voltage conditioning module; 10-a battery bus voltage conditioning module; 11-a mains current conditioning module; 12-a relay isolation module; 13-bridge drive module; 14-bus bar processing module.

Detailed Description

The technical solution of the present invention is further explained below with reference to the drawings of the specification.

The utility model discloses a power supply unit 1, measurement unit 6, insulating detecting element 5, memory cell 3, communication unit 4 and control acquisition unit 2, as shown in fig. 1.

The power supply unit 1 includes a first power conversion module and a second power conversion module.

The first power conversion module is shown in fig. 4, and comprises a first power conversion chip U1, wherein a WRA1205S DC-DC conversion chip is adopted, the input end of the first power conversion chip U1 is connected with external direct current power supplies VC + and VS-, the output ends are respectively power supply +5V1_ DC, power supply-5V 1_ DC and ground AGND2, a capacitor C1A is arranged between the direct current power supplies 12+ and 12-, the VC + end is provided with a fuse F1, so as to obtain power supplies VC + and VC-, and supply power to the metering unit 6, the insulation detection unit 5, the communication unit 4, the storage unit 3 and the control acquisition unit 2. The ground AGND2 obtains DG2 through a series resistor R4, a power supply +5V1 is obtained by filtering through a capacitor C12 and a capacitor C13 which are connected between +5V1_ dc and DG2 in parallel, and a power supply + D5V1 is obtained through a resistor R6 which is connected with +5V1 in series.

As shown in FIG. 5, the second power conversion module has input terminals directly connected to power sources VC + and VS-, and an output terminal + Vo is power source +5V2,0V is ground AGND1, and Cs is power source-5V 2, two capacitors C11 and C10 are connected in parallel between +5V2 and AGND1, and two capacitors C4 and C3 are connected in parallel between AGND1 and-5V 2. Meanwhile, capacitors C5 and C7 are connected in parallel between the +5V2 and the AGND1, a power supply +5V2A is obtained after filtering, capacitors C6 and C8 are connected in parallel between the power supply +5V2A and the AGND1, a resistor R2 connected in series with the positive end of a capacitor C6 is connected with a power supply V +5D _ DC, a resistor R3 connected in series with the negative end of a capacitor C6 is connected with a ground DG1, and a capacitor C9 is arranged between the power supply V +5D _ DC and the ground DG 1.

As shown in fig. 6, the control acquisition unit 2 includes a control acquisition chip U3 and peripheral circuits thereof, the control acquisition chip U3 employs STM8S005K6, and a pin 1 NRST of the control acquisition chip U3 is grounded to DG1 through a capacitor C2; the pin 2 and the pin 3 of the acquisition chip U3 are controlled to be connected with a crystal oscillator Y1, and the DG1 is grounded through a capacitor C16 and a capacitor C19; the 4-pin VSS of the control acquisition chip U3 is directly grounded to DG 1; the 5-pin VCAP of the control acquisition chip U3 is grounded DG1 through a capacitor C1; the pin 6 and the pin 7 of the control acquisition chip U3 are connected and are connected with a power supply V +5D _ DC, and the power supply V +5D _ DC is connected with NRST through a resistor R1; the pin 9 of the acquisition control chip U3 is directly connected with the power supply +5V 2A; the pin 10 of the control acquisition chip U3 is directly connected with the ground AGND 1; the 17 pin, the 22 pin to the 24 pin of the control acquisition chip U3 are respectively connected with the metering unit 6 through resistors R88, R8, R7 and R5, and the metering unit 6 transmits data to the control acquisition chip U3; a pin 26 of the control acquisition chip U3 pulls up a power supply +5V2 through a resistor R18, and the power supply +5V2 is connected with an AGND1 in parallel through a capacitor C31 and a capacitor C32.

As shown in fig. 7, the communication unit 4 is configured to communicate with the outside, and includes a communication chip U4 and peripheral circuits thereof, the communication chip U4 specifically uses MAX485ESA, the 1 pin RXD, the 2 pin RTS, and the 4 pin TXD of the communication chip U4 are respectively connected to the 31 pin, the 18 pin, and the 30 pin of the control acquisition chip U3, and the 3 pin of the communication chip U4 is connected to the 2 pin; a pin 5 of a communication chip U4 is directly grounded AGND1, a pin 6 RS485A is pulled up to a power supply +5V2 through a resistor R11, an AGND1 is grounded through a bidirectional diode P3, a pin 7 RS485B is pulled down to ground AGND1 through a resistor R19, AGND1 is grounded through a bidirectional diode P2, a pin 8 is connected with a power supply +5V2, and AGND1 is grounded through a capacitor C17.

As shown in fig. 8, the storage unit 3 is configured to store data acquired by the control acquisition chip U3, and includes a storage chip U5 and a peripheral circuit thereof, the storage chip U5 specifically adopts AT24C512BV, pins 1 to 4 and 7 of the storage chip U5 are directly grounded AGND1, and the pin 5 SDA is connected to pin 11 of the control acquisition chip U3, and pulls up the power supply +5V2A through a resistor R21; the 6-pin SCL is connected with a 27 pin of a control acquisition chip U3, and a power supply +5V2A is pulled up through a resistor R20; the 8-pin is directly connected with a power supply +5V 2A.

As shown in fig. 3, the metering unit 6 can meter the mains voltage V1+, the battery bus voltage V2+, V2-, and the mains current I +, I-. The metering mains voltage V1+, the battery bus voltage V2+, V2-and the mains current I + and I-are connected into the circuit through a first interface J1 and a second interface J2.

As shown in fig. 2, the metering unit 6 includes a metering module 8, a photoelectric isolation module 7, and a mains supply voltage conditioning module 9 and a mains supply current conditioning module 11 connected to the metering module 8, the metering module 8 is connected to the control acquisition unit 2 through the photoelectric isolation module 7, and the battery bus voltage conditioning module 10 is connected to the control acquisition chip U3.

As shown in fig. 9, the metering module 8 includes a metering chip U9 and its peripheral circuits, specifically an ATT7053BU chip. The 1 pin of the metering chip U9 is connected with a power supply + D5V1, and is grounded DG2 through a capacitor C20 and a capacitor C21 which are connected in parallel; the 2 pin of the metering chip U9 is a reset pin, is connected with a power supply + D5V1 through a resistor R13, and is grounded DG2 through a capacitor C26; c24 and C23 are connected in parallel between the pin 3 of the metering chip U9 and the ground AGND 2; 4 pins of the metering chip U9 are pulled up to a power supply + D5V1 through a resistor R12; filtering the power supply +5V1 through a capacitor C28 and a capacitor C30 to obtain a power supply AVCC, and connecting a pin 5 of a metering chip U9 with the AVCC; the pin 8 and the pin 9 of the metering chip U9 are connected and grounded to AGND2 through a resistor R15; the 12 pins of the metering chip U9 are grounded AGND2 through a capacitor C29 and a capacitor C27; AGND2 pin 13 of the measurement chip U9; pins 18 to 21 of the metering chip U9 are SPI communication pins, the pin 18 is connected with a power supply + D5V1 through a resistor R14, AGND2 is grounded through a capacitor C25, and the pins 18 to 21 are connected with the photoelectric isolation module 7; a crystal oscillator Y2 is connected between the pin 22 and the pin 23 of the metering chip U9 in series, and DG2 is grounded through a capacitor C18 and a capacitor C22; the 24 pin of metrology chip U9 is grounded to DG 2.

As shown in fig. 12, the optoelectronic isolation module 7 is a optoelectronic isolation chip U12, specifically, the model is ADuM1401, a pin 1 of the optoelectronic isolation chip U12 is connected to a power supply +5V2,

pins

2 and 8 are grounded AGND1, a capacitor C58 is connected in series between the pin 1 and the pin 2, and a pin 7 is pulled up to the power supply +5V2 through a resistor R89. A pin 16 of the photoelectric isolation chip U12 is connected with a power supply +5V1, a pin 15 and a pin 9 are grounded AGND2, and a series capacitor C59 and a pin 10 between the pin 16 and the pin 15 are pulled up to the power supply +5V1 through a resistor R90. Pins 3 to 6 are connected with a control acquisition chip U3, and pins 11 to 14 are connected with a metering chip U9.

As shown in fig. 9, the utility voltage conditioning module 9 is a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, and a resistor R27 connected in series between the utility voltage VI + and the ground DG2, wherein the two ends of the resistor R27 are connected in parallel with the resistor R28 and the capacitor C34, and the divided voltage V3P is connected to the pin 6 of the metering chip U9; the 7 pins of the metering chip U9 are grounded to DG2 through a resistor R29 and a capacitor C36 which are connected in parallel.

As shown in fig. 10 and 11, the battery bus voltage conditioning module 10 includes a battery positive bus voltage conditioning module and a battery negative bus voltage conditioning module, where the battery positive bus voltage conditioning module includes a first voltage dividing circuit, a first follower circuit, a first reverse circuit, a first equidirectional secondary voltage dividing circuit, and a first reverse secondary voltage dividing circuit. The first voltage division circuit comprises a resistor R64, a resistor R65, a resistor R66, a resistor R67, a resistor R68, a resistor L8 and a resistor R69 which are connected in series between a positive bus voltage V2+ and ground AGND1, a capacitor C49 is connected in parallel between two ends of a resistor R69, and SAME-DC + of a common end of the resistor R69 and the resistor L8 is connected with the first follower circuit. The first follower circuit comprises a first operational amplifier U10A, wherein a pin 8 of the first operational amplifier U10A is connected with a power supply +5V2 and is grounded AGND1 through a capacitor C50, a pin 4 of the first operational amplifier U10A is connected with a pin 5V2 and is grounded AGND1 through a capacitor C51, a common end SAME-DC + of a resistor R69 and a resistor L8 is connected with a positive input end of the first operational amplifier U10A, a negative input end is directly connected with an output end H5, and an output end H5 is connected with a first inverter circuit and a first in-phase secondary voltage division circuit. The first synclastic voltage dividing circuit is formed by connecting a resistor R72, a resistor L6 and a resistor R73 in series between an output end H5 of the first operational amplifier U10A and ground AGND1, two ends of the resistor R73 are connected with a capacitor C52 in parallel, a resistor RL6 is connected with the common end of the resistor L6 and the resistor R73, and the other end PB8 of the resistor RL6 is connected with a pin 12 of the control acquisition chip U3. The first inverting circuit comprises a second operational amplifier U10B, the positive input end of the second operational amplifier U10B is grounded AGND1 through a resistor R87, the negative input end is connected with the output end H5 of the first operational amplifier U10A through a resistor R70, a resistor R71 is connected between the negative input end and the output end of the second operational amplifier U10B in series, and the output end is connected with the first inverting secondary voltage division circuit. The first reverse secondary voltage division circuit is formed by connecting a resistor R74, a resistor L7 and a resistor R75 in series between an output end H6 of the second operational amplifier U10B and ground AGND1, two ends of the resistor R75 are connected with a capacitor C53 in parallel, a common end of the resistor L7 and a resistor R75 is connected with a resistor RL7, and the other end PB7 of the resistor RL7 is connected with a pin 14 of the control acquisition chip U3.

The battery negative bus voltage conditioning module comprises a second voltage division circuit, a second following circuit, a second reverse circuit and a second reverse secondary voltage division circuit. The second voltage division circuit comprises a resistor R81, a resistor R82, a resistor R83, a resistor R84, a resistor R85, a resistor L10 and a resistor R86 which are connected in series between the negative bus voltage V2-and the ground AGND1, a capacitor C57 is connected in parallel between two ends of the resistor R86, and a common end SAME-DC-of the resistor R86 and the resistor L10 is connected with the second follower circuit. The second follower circuit comprises a third operational amplifier U11A, wherein a pin 8 of the third operational amplifier U11A is connected with a power supply +5V2 and is grounded AGND1 through a capacitor C54, a pin 4 of the third operational amplifier U11A is connected with a pin 5V2 and is grounded AGND1 through a capacitor C55, a common end SAME-DC of a resistor R86 and a resistor L10 is connected with a positive input end of the third operational amplifier U11A, a negative input end is directly connected with an output end H7, and an output end H7 is connected with a second inverter circuit. The first inverting circuit comprises a fourth operational amplifier U11B, the positive input end of the fourth operational amplifier U11B is grounded AGND1 through a resistor R76, the negative input end is connected with the output end H7 of the third operational amplifier U11A through a resistor R77, a resistor R78 is connected between the negative input end of the fourth operational amplifier U11B and the output end H8 in series, and the output end H8 is connected with the second inverting secondary voltage division circuit. The second reverse secondary voltage division circuit is formed by connecting a resistor R79, a resistor L9 and a resistor R80 in series between an output end H8 of the fourth operational amplifier U11B and ground AGND1, two ends of the resistor R80 are connected with a capacitor C56 in parallel, a common end of the resistor L9 and a resistor R80 is connected with a resistor RL9, and the other end PB6 of the resistor RL9 is connected with a pin 15 of the control acquisition chip U3.

As shown in fig. 9, the utility current conditioning module 11 is a utility current, wherein a positive terminal I + of the utility current is grounded to DG2 through a resistor R33 and a capacitor C38, a negative terminal I-of the utility current is grounded to DG2 through a resistor R40 and a capacitor C40, a common terminal of the resistor R33 and the capacitor C38 is V1P, a common terminal of the resistor R40 and the capacitor C40 is V1N, and the V1P and the V1N are respectively connected to

pins

10 and 11 of the metering chip U9.

As shown in fig. 3, the insulation detection unit 5 includes a bridge driving module 13, a relay isolation module 12, and a bus bar processing module 14. As shown in fig. 13, the bridge driving module 13 includes a driving chip U7, a transistor Q1, and a transistor Q2, where AQW216 is adopted for the driving chip U7, a pin PB1 of a control acquisition chip U3 is connected to a base of the transistor Q1 through a resistor R32, and is grounded to AGND1 through a capacitor C39, an emitter of the transistor Q1 is connected to the power supply +5V2, and a collector of the transistor Q1 is connected to a pin 1 of the driving chip U7 through a resistor R34; a pin PB2 of the control acquisition chip U3 is connected with a base electrode of a triode Q2 through a resistor R38, the base electrode of the triode Q2 is grounded AGND1 through a capacitor C41, an emitter electrode of the triode Q2 is connected with a power supply +5V2, and a collector electrode of the triode Q1 is connected with a pin 3 of a driving chip U7 through a resistor R39; pins 2, 4, 6 and 7 of the driving chip U7 are grounded AGND1, pin 8V-DC + of the driving chip U7 is connected with the positive bus insulation processing module, and pin 5 of the driving chip U7 is connected with the negative bus insulation processing module.

As shown in fig. 14, the bus bar processing module 14 includes a positive bus bar insulation processing module and a negative bus bar insulation processing module, and the positive bus bar insulation processing module includes a third voltage division circuit, a third follower circuit, a third inverter circuit, a third equidirectional secondary voltage division circuit, and a third inverter secondary voltage division circuit. A resistor R50, a resistor R43, a resistor R44, a resistor R45, a resistor R46, a resistor R47, a resistor L5 and a resistor R48 are connected in series between an 8-pin V-DC + of a driving chip U7 and ground AGND1, two ends of the resistor R48 are connected with a capacitor C44 in parallel, and a common end SAMV-DC + of the resistor L5 and the resistor R48 is connected with a third follower circuit. The third follower circuit comprises a fifth operational amplifier U6A, wherein the pin 8 of the fifth operational amplifier U6A is connected with a power supply +5V2 and is grounded AGND1 through a capacitor C35, the pin 4 of the fifth operational amplifier U6A is connected with a power supply-5V 2 and is grounded AGND1 through a capacitor C37, the common end SAMV-DC + of a resistor L5 and a resistor R48 is connected with the positive input end of the fifth operational amplifier U6A, the negative input end of the fifth operational amplifier U6A is connected with an output end H3, and the output end H3 of the fifth operational amplifier U6A is connected with a third homodromous secondary voltage division circuit and a third inverter circuit. The third equidirectional secondary voltage division circuit is that the output end H3 of the fifth operational amplifier U6A is grounded AGND1 through a resistor R36, a resistor L1 and a resistor R41, two ends of the resistor R41 are connected in parallel with a capacitor C42, a resistor L1 and a resistor R41 are connected with a common end resistor RL1, and the other end PB3 of the resistor RL1 is connected with a pin 13 of the control acquisition chip U3. The third inverting circuit comprises a sixth operational amplifier U6B, the positive input terminal of the sixth operational amplifier U6B is grounded through a resistor R30, the negative input terminal of the sixth operational amplifier U6B is connected with the output terminal H3 of the fifth operational amplifier U6A through a resistor R31 and is connected with the output terminal H4 of the sixth operational amplifier U6B through a resistor R35, and the output terminal H4 of the sixth operational amplifier U6B is connected with the third inverting secondary voltage dividing circuit. The third reverse secondary voltage division circuit is that the output end H4 of the sixth operational amplifier U6B is grounded AGND1 through a series resistor R37, a resistor L2 and a resistor R42, two ends of the resistor R42 are connected with a capacitor C43 in parallel, the common end of the resistor L2 and the resistor R42 is connected with a resistor RL2, and the other end PB4 of the resistor RL2 is connected with a pin 16 of the control acquisition chip U3.

The negative bus insulation processing module comprises a fourth voltage division circuit, a fourth following circuit, a fourth reverse circuit and a fourth reverse secondary voltage division circuit. A resistor R63, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R58, a resistor L4 and a resistor R60 are connected in series between a pin 5V-DC-of the driving chip U7 and ground AGND1, a capacitor C47 is connected in parallel to two ends of the resistor R60, and a common end SAMV-DC-of the resistor L4 and the resistor R60 is connected with a fourth follower circuit. The fourth follower circuit comprises a seventh operational amplifier U8A, wherein the 8 pin of the seventh operational amplifier is connected with a power supply +5V2 and is grounded AGND1 through a capacitor C45, the 4 pin of the seventh operational amplifier U8A is connected with a power supply-5V 2 and is grounded AGND1 through a capacitor C46, the common terminal SAMV-DC-of a resistor L4 and a resistor R60 is connected with the positive input terminal of the seventh operational amplifier U8A, the negative input terminal of the seventh operational amplifier U8A is connected with the output terminal H1, and the output terminal H1 of the seventh operational amplifier U8A is connected with a fourth inverter circuit. The fourth inverting circuit includes an eighth operational amplifier U8B, the positive input terminal of the eighth operational amplifier U8B is grounded through a resistor R51, the negative input terminal of the eighth operational amplifier U8B is connected to the output terminal H1 of the seventh operational amplifier U8A through a resistor R52 and to the output terminal H2 of the eighth operational amplifier 8B through a resistor R53, and the output terminal H2 of the eighth operational amplifier U8B is connected to the fourth inverting secondary voltage divider circuit. The fourth reverse secondary voltage division circuit is that the output end H2 of the eighth operational amplifier U8B is grounded AGND1 through a series resistor R59, a resistor L3 and a resistor R62, two ends of the resistor R62 are connected with a capacitor C48 in parallel, a common end of the resistor L3 and a resistor R62 is connected with a resistor RL3, and the other end PB5 of the resistor RL3 is connected with an 8 pin of the control acquisition chip U3.

The relay isolation module 12 is shown in fig. 14 and comprises a positive relay isolation module and a negative relay isolation module, wherein the positive relay isolation module comprises a relay K1 and a triode Q3, the base of the triode Q3 is connected with a 19-pin K2-Ctl of the control acquisition chip U3 through a resistor R49, an emitter is connected with a power supply +5V2, a diode D1 is connected in series between the emitter and a collector, the collector is connected with a pin 1 of the relay K1, a pin 2 of the relay K1 is connected with an AGND1, a pin 3 of the relay K1 is connected with a positive insulation detection end, and a pin 4 of the relay K1 is connected with a common end of a resistor R50 and a resistor R43. The negative relay isolation module comprises a relay K2 and a triode Q4, the base of the triode Q4 is connected with a pin 20K 1-Ctl of a control acquisition chip U3 through a resistor R61, an emitter is connected with a power supply +5V2, a diode D2 is connected between the emitter and a collector in series, the collector is connected with a pin 1 of the relay K2, a pin 2 of the relay K2 is connected with an AGND1, a pin 3 of the relay K2 is connected with a negative insulation detection end, the positive insulation detection end and the negative insulation detection end are respectively a positive output end and a negative output end of the AC-to-DC module, the AC-to-DC module outputs power to a battery, and a pin 4 of the relay K2 is connected with a common end of a resistor R63 and a resistor R54.

And a pin 19K 2-Ctl and a pin 20K 1-Ctl of the control acquisition chip U3 control the closing of the relays K1 and K2, and when the relays K1 and K2 are closed, the output end of the AC-to-DC module can be connected into a circuit for insulation detection. A pin PB1 and a pin PB2 of the control acquisition chip U3 control whether V-CD + and V-DC-are connected with the ground AGND1 or not, when both V-CD + and V-DC-are connected with the AGND1, the measurement mode is an unbalanced bridge measurement mode, and when one end of the V-CD + and V-DC-is not connected with the ground AGND1, the measurement mode is a balanced bridge measurement mode.

In order to show operating condition, the utility model discloses still be equipped with the display module, as shown in fig. 15, include and gather chip U3's 21 feet with the control and be connected emitting diode LED1, emitting diode LED 1's the other end passes through resistance R17 and resistance R16 and connects power +5V2, and resistance R19 ground connection AGND1 is passed through to resistance R16's one end.

An independent power isolation module is adopted to supply power to the metering chip, and a voltage sampling loop adopts a plurality of precise resistor voltage division modes and is also provided with a filter circuit; the voltage of the current sampling loop at two ends of the shunt is directly sent to a sampling port of the metering chip through the filter circuit. The metering chip and the control acquisition chip are communicated by adopting an SPI with photoelectric isolation; the SPI communication ensures real-time and stable data; the metering chip ensures that the data is reliable and effective.

The effective voltage range of insulation detection is DC 150V-DC 750V, and the voltage of an input bus is switched on or off by a high-voltage relay; the DC floating earth positive and negative pole has an insulation resistance value to earth ranging from 0 to 1.5M. The user can realize data acquisition through the RS485 interface cyclic scanning monitoring module, and can also reset and stop the module through instructions. The balance mode adopts a balance bridge to measure the insulation resistance value, and a theoretical model thereof assumes that the positive bus and the negative bus of the system have ground fault at one end and no fault at the other end, and tests the ground resistance value at the fault end. The unbalanced mode is that an unbalanced bridge is constructed in the module, and the insulation resistance value is obtained by scanning the voltage of positive and negative terminals.

Claims

1. The utility model provides a measurement and insulation detection appearance for direct current fills electric pile, includes electrical unit (1), control acquisition unit (2) and insulation detection unit (5), and electrical unit (1) is connected with control acquisition unit (2) and insulation detection unit (5), its characterized in that insulation detection unit (5) are including bridge drive module (13), relay isolation module (12), generating line processing module (14) be connected with control acquisition unit (2), and insulation detection end is connected with relay isolation module (12), bridge drive module (13) and relay isolation module (12) are connected with generating line processing module (14) respectively.

2. The metering and insulation detector for the direct-current charging pile according to claim 1, wherein the bus processing module (14) comprises a positive bus insulation processing module and a negative bus insulation processing module, the positive bus insulation processing module comprises a third equidirectional secondary voltage division circuit and a third voltage division circuit, a third following circuit, a third reverse circuit and a third reverse secondary voltage division circuit which are connected in sequence, and the third following circuit is connected with the third equidirectional secondary voltage division circuit; the negative bus insulation processing module comprises a fourth voltage division circuit, a fourth following circuit, a fourth reverse circuit and a fourth reverse secondary voltage division circuit which are sequentially connected.

3. The meter and insulation detector for the direct current charging pile according to claim 1, wherein the bridge driving module (13) comprises a driving chip U7, a transistor Q1 and a transistor Q2, and the control acquisition unit (2) is connected with an input end of the driving chip U7 through the transistor Q1; the control acquisition unit (2) is connected with the input end of a driving chip U7 through a triode Q2, two negative input ends of the driving chip U7 are grounded AGND1, and the output end of the driving chip U7 is connected with the bus processing module (14).

4. The metering and insulation detector for the direct current charging pile according to claim 1, characterized in that the relay isolation module (12) comprises a positive relay isolation module and a negative relay isolation module, the positive relay isolation module comprises a relay K1 and a triode Q3, the control acquisition unit (2) is connected with the relay K1 through the triode Q3, and the positive insulation detection end is connected with the bus processing module (14) through the relay K1; the negative relay isolation module comprises a relay K2 and a triode Q4, the control acquisition unit (2) is connected with the relay K2 through the triode Q4, and the negative insulation detection end is connected with the bus processing module (14) through the relay K2.

5. The metering and insulation detector for the direct-current charging pile according to claim 1, characterized by further comprising a metering unit (6), wherein the metering unit (6) comprises a metering module (8), a photoelectric isolation module (7), a battery bus voltage conditioning module (10), a mains voltage conditioning module (9) and a mains current conditioning module (11), the metering module (8) is connected with the control acquisition unit (2) through the photoelectric isolation module (7), and the battery bus voltage conditioning module (10) is connected with the control acquisition unit (2).

6. The metering and insulation detector for the direct-current charging pile according to claim 5, characterized in that the battery bus voltage conditioning module (10) comprises a battery positive bus voltage conditioning module and a battery negative bus voltage conditioning module, the battery positive bus voltage conditioning module comprises a first equidirectional secondary voltage division circuit, and a first voltage division circuit, a first following circuit, a first reverse circuit and a first reverse secondary voltage division circuit which are connected in sequence, and the first following circuit is connected with the first equidirectional secondary voltage division circuit; the battery negative bus voltage conditioning module comprises a second voltage division circuit, a second following circuit, a second reverse circuit and a second reverse secondary voltage division circuit which are sequentially connected.

7. The measuring and insulation detector for the direct current charging pile according to claim 1, characterized in that the detector comprises a communication unit (4) and a storage unit (3), wherein the communication unit (4) adopts an RS485 communication mode.