CN210640249U

CN210640249U - Semiconductor memory device with a memory cell having a plurality of memory cells

Info

Publication number: CN210640249U
Application number: CN201922032330.XU
Authority: CN
Inventors: 刘忠明; 白世杰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-11-22
Filing date: 2019-11-22
Publication date: 2020-05-29
Anticipated expiration: 2029-11-22

Abstract

The present disclosure relates to the field of semiconductor technology, and provides a semiconductor memory, which includes a substrate, a peripheral circuit portion and a memory cell array portion, wherein the substrate includes a first molding surface and a second molding surface, and the first molding surface and the second molding surface are respectively located at two sides of the substrate; at least part of the peripheral circuit portion is disposed on the first molding surface; the memory cell array part is arranged on the second molding surface; wherein, the substrate is provided with a first contact through hole, and two end faces of the first contact through hole are respectively exposed on the first molding surface and the second molding surface to conduct the peripheral circuit part and the memory cell array part. The peripheral circuit part and the memory cell array part are arranged up and down, so that the area of the semiconductor memory is effectively reduced, and the storage density of the semiconductor memory is improved.

Description

Semiconductor memory device with a memory cell having a plurality of memory cells

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor memory.

Background

A conventional circuit arrangement of a semiconductor memory is such that a dense region (memory cell array section) and a peripheral circuit region (peripheral circuit section) are distributed in the same horizontal region. The area of the dense area is about 60%, and the arrangement mode limits the improvement of the storage density of the memory, namely the area of the semiconductor memory is larger, and the delay time is longer.

SUMMERY OF THE UTILITY MODEL

It is a primary object of the present disclosure to overcome at least one of the above-mentioned deficiencies of the prior art and to provide a semiconductor memory.

The utility model provides a semiconductor memory, include:

the substrate comprises a first molding surface and a second molding surface, wherein the first molding surface and the second molding surface are respectively positioned at two sides of the substrate;

a peripheral circuit portion, at least a part of which is disposed on the first molding surface;

a memory cell array portion disposed on the second molding surface;

wherein, the substrate is provided with a first contact through hole, and two end faces of the first contact through hole are respectively exposed on the first molding surface and the second molding surface to conduct the peripheral circuit part and the memory cell array part.

In one embodiment of the present invention, the semiconductor memory further includes:

the base is arranged on one side, away from the substrate, of the peripheral circuit part.

In an embodiment of the present invention, the peripheral circuit portion includes:

a circuit layer disposed on the substrate;

the dielectric layer is arranged on the first molding surface, and the circuit layer is sealed in the dielectric layer and the substrate;

the interconnection layer is arranged in the medium layer and is used for connecting the circuit layer;

the base is arranged on one side, away from the substrate, of the dielectric layer.

and the transition layer is connected between the dielectric layer and the substrate.

In an embodiment of the present invention, a second contact through hole is provided on the substrate, two end faces of the second contact through hole are exposed to the first molding surface and the second molding surface, respectively, a third contact through hole is provided on the memory cell array portion, the second contact through hole is connected to the third contact through hole, and the semiconductor memory further includes:

and the bonding pad is arranged on one side of the memory cell array part, which is far away from the substrate, and is conducted with the peripheral circuit part through the third contact through hole and the second contact through hole.

In one embodiment of the present invention, the semiconductor memory further includes a first contact plug and a second contact plug, and the memory cell array portion includes:

a plurality of word lines, which are arranged in parallel;

the bit lines are arranged in parallel, and the extending direction of the word lines is vertical to the extending direction of the bit lines;

the first contact plugs and the second contact plugs are multiple, the multiple first contact plugs conduct the multiple word lines with the peripheral circuit part, and the multiple second contact plugs conduct the bit lines with the peripheral circuit part.

In one embodiment of the present invention, the extending direction of the first contact plug is perpendicular to the extending direction of the word line, and the extending direction of the second contact plug is perpendicular to the extending direction of the bit line.

In one embodiment of the present invention, the plurality of first contact plugs are located on the same side of the word line and are arranged in a staggered manner, and/or the plurality of second contact plugs are located on the same side of the bit line and are arranged in a staggered manner; or the like, or, alternatively,

the plurality of first contact plugs are respectively located at both ends of the word lines and are arranged alternately, and/or the plurality of second contact plugs are respectively located at both ends of the bit lines and are arranged alternately.

In one embodiment of the present invention, the semiconductor memory is a dynamic random access memory.

The utility model discloses a semiconductor memory includes substrate, peripheral circuit part and memory cell array part, and peripheral circuit part and memory cell array part are located the first molding surface and the second molding surface of substrate respectively, and peripheral circuit part and memory cell array part belong to the mode of arranging from top to bottom promptly to effectively reduced semiconductor memory's area, realized the promotion to semiconductor memory storage density with this.

Drawings

Various objects, features and advantages of the present disclosure will become more apparent from the following detailed description of preferred embodiments thereof, when considered in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the disclosure and are not necessarily drawn to scale. In the drawings, like reference characters designate the same or similar parts throughout the different views. Wherein:

FIG. 1 is a schematic diagram illustrating the structure of a semiconductor memory according to an exemplary embodiment;

FIG. 2 is a schematic diagram illustrating a structure of a substrate provided by a method of fabricating a semiconductor memory device, according to an exemplary embodiment;

fig. 3 is a schematic structural view illustrating a first contact via formed by a method of manufacturing a semiconductor memory according to an exemplary embodiment;

fig. 4 is a schematic structural view showing a state after a peripheral circuit portion is formed by a manufacturing method of a semiconductor memory according to an exemplary embodiment;

fig. 5 is a schematic structural view illustrating a preparation method of a semiconductor memory device for bonding a peripheral circuit portion to a substrate according to an exemplary embodiment;

fig. 6 is a schematic structural view illustrating a structure after bonding of a peripheral circuit portion and a substrate is completed using a manufacturing method of a semiconductor memory according to an exemplary embodiment;

FIG. 7 is a schematic diagram illustrating a structure after thinning a substrate using a method for fabricating a semiconductor memory according to an exemplary embodiment;

fig. 8 is a schematic structural view illustrating a memory cell array portion formed by a manufacturing method of a semiconductor memory according to an exemplary embodiment;

FIG. 9 is a schematic diagram illustrating a structure after forming a pad using a method of fabricating a semiconductor memory according to an exemplary embodiment;

fig. 10 is a schematic diagram illustrating an arrangement of word lines and first contact plugs or bit lines and second contact plugs of a semiconductor memory according to an exemplary embodiment;

fig. 11 is a schematic diagram illustrating an arrangement of a word line and a first contact plug or a bit line and a second contact plug of a semiconductor memory according to another exemplary embodiment.

The reference numerals are explained below:

10. a substrate; 11. a first molding surface; 12. a second molding surface; 13. a first contact via; 14. a second contact via; 20. a peripheral circuit section; 21. a circuit layer; 22. a dielectric layer; 23. an interconnect layer; 30. a memory cell array portion; 31. a third contact via; 32. a word line; 33. a bit line; 40. a substrate; 50. a transition layer; 60. a pad; 70. a first contact plug; 71. and a second contact plug.

Detailed Description

Exemplary embodiments that embody features and advantages of the present disclosure are described in detail below in the specification. It is to be understood that the disclosure is capable of various modifications in various embodiments without departing from the scope of the disclosure, and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.

In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary structures, systems, and steps in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure.

An embodiment of the present invention provides a semiconductor memory, please refer to fig. 1, the semiconductor memory includes: a substrate 10, the substrate 10 comprising a first molding surface 11 and a second molding surface 12, the first molding surface 11 and the second molding surface 12 being respectively located at both sides of the substrate 10; a peripheral circuit portion 20, at least a part of the peripheral circuit portion 20 being disposed on the first molding surface 11; a memory cell array portion 30, the memory cell array portion 30 being disposed on the second molding surface 12; wherein, the substrate 10 is provided with a first contact through hole 13, and both end surfaces of the first contact through hole 13 are exposed to the first molding surface 11 and the second molding surface 12, respectively, to conduct the peripheral circuit portion 20 and the memory cell array portion 30.

The semiconductor memory according to an embodiment of the present invention includes a substrate 10, a peripheral circuit portion 20 and a memory cell array portion 30, wherein the peripheral circuit portion 20 and the memory cell array portion 30 are respectively disposed on a first molding surface 11 and a second molding surface 12 of the substrate 10, i.e., the peripheral circuit portion 20 and the memory cell array portion 30 belong to an up-down arrangement manner, thereby effectively reducing the area of the semiconductor memory and realizing the improvement of the storage density of the semiconductor memory.

In one embodiment, compared with the prior art in which the peripheral circuit portion 20 and the memory cell array portion 30 are distributed in the same horizontal region, the peripheral circuit portion 20 and the memory cell array portion 30 of the present embodiment are distributed in two horizontal regions, thereby reducing the horizontal area of the semiconductor memory (the horizontal area occupied by the original peripheral circuit portion 20), and thus achieving the enhancement of the storage density of the semiconductor memory. In addition, considering that the thickness of the semiconductor memory is much smaller than the length and width of the semiconductor memory, when the peripheral circuit portion 20 and the memory cell array portion 30 are distributed up and down, the connection distance between the two is reduced, thereby reducing the communication time between the two, and reducing the operation delay time of the semiconductor memory.

In one embodiment, the first contact Via 13 is a Through-Silicon Via (TSV) that electrically connects the peripheral circuit portion 20 and the memory cell array portion 30.

In one embodiment, as shown in fig. 1, the semiconductor memory further includes: and a base 40, wherein the base 40 is arranged on one side of the peripheral circuit part 20, which faces away from the substrate 10. The base 40 and the substrate 10 sandwich the peripheral circuit section 20, and the provision of the base 40 can enhance the strength of the semiconductor memory, that is, the size in the thickness direction thereof is increased. The substrate 40 is used as a stiffener to assist in the processing of the semiconductor memory device to prevent the semiconductor memory device from breaking during the manufacturing process.

In one embodiment, the substrate 10 may be a P-type substrate or an N-type substrate. The substrate 40 is a carrier wafer.

In one embodiment, as shown in fig. 4, the peripheral circuit section 20 includes: a circuit layer 21, the circuit layer 21 being disposed on the substrate 10; a dielectric layer 22, the dielectric layer 22 is arranged on the first molding surface 11, and the circuit layer 21 is sealed in the dielectric layer 22 and the substrate 10; an interconnection layer 23, the interconnection layer 23 being disposed in the dielectric layer 22 for connecting the circuit layer 21; wherein, the base 40 is disposed on a side of the dielectric layer 22 facing away from the substrate 10. The circuit layer 21 includes a bulk field effect transistor having a gate, a source, and a drain, the interconnect layer 23 is used to connect the respective devices in the circuit layer 21, and the dielectric layer 22 belongs to a protective layer for sealing the circuit layer 21 and the interconnect layer 23.

As shown in fig. 6, the semiconductor memory further includes: and the transition layer 50, wherein the transition layer 50 is connected between the dielectric layer 22 and the substrate 40. The transition layer 50 may isolate the dielectric layer 22 from the substrate 40 so that the two cannot be in direct contact and secondarily insulate the peripheral circuit portion 20. The transition layer 50 is a passivation layer, and the material thereof may be one of silicon dioxide, silicon nitride, organic matter, or a combination thereof.

In one embodiment, the substrate 10 is provided with a second contact through hole 14, both end surfaces of the second contact through hole 14 are exposed to the first molding surface 11 and the second molding surface 12, respectively, the memory cell array portion 30 is provided with a third contact through hole 31, and the second contact through hole 14 is connected to the third contact through hole 31, and the semiconductor memory further includes: and a pad 60, the pad 60 being disposed on a side of the memory cell array portion 30 facing away from the substrate 10, the pad 60 being in electrical communication with the peripheral circuit portion 20 through the third contact via 31 and the second contact via 14. The pad 60 is provided for connecting the semiconductor memory device with an external device, i.e., the pad 60 is conducted to the peripheral circuit portion 20 through the third contact via 31 and the second contact via 14, and the peripheral circuit portion 20 is conducted to the memory cell array portion 30 through the first contact via 13, thereby achieving electrical communication of the external device with the memory cell array portion 30.

In one embodiment, the second contact via 14 and the third contact via 31 may directly interface, although other arrangements that ensure electrical connection, such as electrical connection, are not excluded.

In one embodiment, as shown in fig. 10 and 11, the semiconductor memory further includes a first contact plug 70 and a second contact plug 71, and the memory cell array portion 30 includes: a plurality of word lines 32, the plurality of word lines 32 being arranged in parallel; a plurality of bit lines 33, the plurality of bit lines 33 being arranged in parallel, the extending direction of the word line 32 being perpendicular to the extending direction of the bit lines 33; the first contact plugs 70 and the second contact plugs 71 are plural, the plural first contact plugs 70 conduct the plural word lines 32 with the peripheral circuit section 20, and the plural second contact plugs 71 conduct the bit lines 33 with the peripheral circuit section 20.

In one embodiment, the extending direction of the first contact plug 70 is perpendicular to the extending direction of the word line 32, and the extending direction of the second contact plug 71 is perpendicular to the extending direction of the bit line 33.

In one embodiment, the plurality of first contact plugs 70 are all located on the same side of the word lines 32 and are arranged alternately, and/or the plurality of second contact plugs 71 are all located on the same side of the bit lines 33 and are arranged alternately; or, a plurality of first contact plugs 70 are respectively located at both ends of the word lines 32 and are arranged alternately, and/or a plurality of second contact plugs 71 are respectively located at both ends of the bit lines 33 and are arranged alternately.

In one embodiment, the memory cell array section 30 includes a plurality of memory cells, each memory cell including a switching transistor having a gate, a source, and a drain, and an information storage element for the switching transistor, a word line 32 for connection with the gate of the switching transistor, and a bit line 33 for connection with the drain of the switching transistor.

In one embodiment, the distance between two adjacent word lines 32 is determined according to the design requirement, and the size of the first contact plug 70 also has a corresponding requirement, and the projection area of the first contact plug 70 on the word lines 32 is larger than the width of the word lines 32, so in order to avoid the contact between two adjacent first contact plugs 70 and ensure that each first contact plug 70 is connected to each word line 32, the arrangement of the first contact plugs 70 needs to be determined reasonably, as shown in fig. 10, each first contact plug 70 may be located on the same side of the word lines 32, but needs to be disposed in a staggered manner to prevent the contact between the two. As shown in fig. 11, since the first contact plug 70 is large, two first contact plugs 70 connected to two adjacent word lines 32 need to be disposed at both ends of the word lines 32 to prevent a mis-contact. Accordingly, the arrangement of the second contact plug 71 and the bit line 33 may participate in the arrangement of the first contact plug 70 and the word line 32.

In one embodiment, the semiconductor memory is a dynamic random access memory.

An embodiment of the present invention further provides a method for manufacturing a semiconductor memory, including: providing a substrate 10; forming a peripheral circuit portion 20 on the first molding surface 11 of the substrate 10; forming a memory cell array portion 30 on the second molding surface 12 of the substrate 10; wherein, a first contact through hole 13 is formed on the substrate 10, and both end surfaces of the first contact through hole 13 are exposed to the first molding surface 11 and the second molding surface 12, respectively, to conduct the peripheral circuit portion 20 and the memory cell array portion 30.

In one embodiment, before forming the memory cell array portion 30, the manufacturing method further includes: a base 40 is formed on the side of the peripheral circuit section 20 facing away from the substrate 10.

In one embodiment, a particular method of forming the substrate 40 includes: the peripheral circuit portion 20 formed on the substrate 10 is bonded to the base 40 by a wafer bonding technique.

In one embodiment, before forming the memory cell array portion 30, the manufacturing method further includes: the substrate 10 formed with the base 40 is thinned to form the second molding surface 12.

In one embodiment, after forming the memory cell array portion 30, the manufacturing method further includes: forming a third contact via hole 31 on the memory cell array portion 30; forming a pad 60 on a side of the memory cell array section 30 facing away from the substrate 10; wherein the substrate 10 is formed with a second contact via 14, and the second contact via 14 is connected with the third contact via 31, so that the pad 60 is conducted with the peripheral circuit portion 20 through the third contact via 31 and the second contact via 14.

In one embodiment, the first contact via 13 and the second contact via 14 are formed on the substrate 10, respectively, before the peripheral circuit section 20 is formed; alternatively, before the peripheral circuit section 20 is formed, the first contact via 13 is formed on the substrate 10, and the third contact via 31 and the second contact via 14 are formed at once on the memory cell array section 30 and the substrate 10.

In one embodiment, the method for manufacturing the semiconductor memory specifically comprises the following steps:

as shown in fig. 2, a substrate 10 is provided, and the substrate 10 may be a P-type substrate or an N-type substrate.

As shown in fig. 3, a first contact through hole 13 is formed on the substrate 10, and one end of the first contact through hole 13 is exposed on the first molding surface 11, the first contact through hole 13 being a through silicon via.

As shown in fig. 4, a peripheral circuit section 20 is formed on the substrate 10 formed with the first contact via 13, the peripheral circuit section 20 includes a circuit layer 21, a dielectric layer 22, and an interconnection layer 23, the circuit layer 21 is disposed on the substrate 10, the dielectric layer 22 is disposed on the first molding surface 11, the circuit layer 21 is sealed in the dielectric layer 22 and the substrate 10, and the interconnection layer 23 is disposed in the dielectric layer 22 for connecting the circuit layer 21.

As shown in fig. 5, the substrate 10 formed with the peripheral circuit section 20 is turned over 180 degrees, that is, the peripheral circuit section 20 is made downward, and a base 40 is prepared.

As shown in fig. 6, the peripheral circuit portion 20 is bonded to the substrate 40 by using a wafer bonding technique, and a transition layer 50 is required between the dielectric layer 22 and the substrate 40 as a transition, and the transition layer 50 is a passivation layer. The substrate 40 is a carrier wafer. The base 40 is mainly used for strengthening, and prevents the substrate 10 from being broken due to subsequent processing engineering, such as thinning the substrate 10, forming the third contact through hole 31 and the second contact through hole 14, and the like.

As shown in fig. 7, the substrate 10 is thinned to form the second molding surface 12, wherein the other end of the first contact through hole 13 is exposed on the second molding surface 12.

As shown in fig. 8, a memory cell array portion 30 is formed on the second molding surface 12.

As shown in fig. 9, the third contact via 31 and the second contact via 14 are formed at one time on the memory cell array section 30 and the substrate 10, and then the pad 60 is connected so that the pad 60 is conducted to the peripheral circuit section 20 through the third contact via 31 and the second contact via 14, thereby forming the semiconductor memory as shown in fig. 1.

In the present embodiment, since the peripheral circuit portion 20 and the memory cell array portion 30 are formed in the vertical direction, that is, the use of a mask layer for insulation can be reduced in the entire forming process, not only the mask can be saved but also the manufacturing efficiency can be improved.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and exemplary embodiments be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A semiconductor memory, comprising:

a substrate (10), the substrate (10) comprising a first molding surface (11) and a second molding surface (12), the first molding surface (11) and the second molding surface (12) being located on both sides of the substrate (10), respectively;

a peripheral circuit portion (20), at least part of said peripheral circuit portion (20) being disposed on said first molding surface (11);

a memory cell array portion (30), the memory cell array portion (30) being disposed on the second molding surface (12);

wherein a first contact through-hole (13) is provided on the substrate (10), and both end faces of the first contact through-hole (13) are exposed to the first molding surface (11) and the second molding surface (12), respectively, to conduct the peripheral circuit portion (20) and the memory cell array portion (30).

2. The semiconductor memory according to claim 1, further comprising:

a base (40), the base (40) being arranged on a side of the peripheral circuit portion (20) facing away from the substrate (10).

3. The semiconductor memory according to claim 2, wherein the peripheral circuit section (20) comprises:

a circuit layer (21), the circuit layer (21) being disposed on the substrate (10);

a dielectric layer (22), wherein the dielectric layer (22) is arranged on the first molding surface (11), and the circuit layer (21) is sealed in the dielectric layer (22) and the substrate (10);

an interconnect layer (23), said interconnect layer (23) disposed within said dielectric layer (22) for connecting said circuit layer (21);

wherein the base (40) is arranged on a side of the dielectric layer (22) facing away from the substrate (10).

4. The semiconductor memory according to claim 3, further comprising:

a transition layer (50), the transition layer (50) connected between the dielectric layer (22) and the substrate (40).

5. The semiconductor memory according to claim 1, wherein a second contact through-hole (14) is provided on the substrate (10), both end faces of the second contact through-hole (14) are exposed to the first molding surface (11) and the second molding surface (12), respectively, a third contact through-hole (31) is provided on the memory cell array portion (30), and the second contact through-hole (14) is connected to the third contact through-hole (31), the semiconductor memory further comprising:

a pad (60), the pad (60) being disposed on a side of the memory cell array portion (30) facing away from the substrate (10), the pad (60) being in conduction with the peripheral circuit portion (20) through the third contact via (31) and the second contact via (14).

6. The semiconductor memory according to claim 1, further comprising a first contact plug (70) and a second contact plug (71), the memory cell array portion (30) comprising:

a plurality of word lines (32), the plurality of word lines (32) being arranged in parallel;

a plurality of bit lines (33), wherein the plurality of bit lines (33) are arranged in parallel, and the extending direction of the word line (32) is vertical to the extending direction of the bit lines (33);

wherein the first contact plug (70) and the second contact plug (71) are each plural, the plural first contact plugs (70) conduct the plural word lines (32) to the peripheral circuit section (20), and the plural second contact plugs (71) conduct the bit lines (33) to the peripheral circuit section (20).

7. The semiconductor memory according to claim 6, wherein an extending direction of the first contact plug (70) is perpendicular to an extending direction of the word line (32), and an extending direction of the second contact plug (71) is perpendicular to an extending direction of the bit line (33).

8. The semiconductor memory according to claim 6, wherein a plurality of the first contact plugs (70) are each located on the same side of the word line (32) and arranged alternately, and/or a plurality of the second contact plugs (71) are each located on the same side of the bit line (33) and arranged alternately; or the like, or, alternatively,

a plurality of the first contact plugs (70) are respectively located at both ends of the word lines (32) and are arranged alternately, and/or a plurality of the second contact plugs (71) are respectively located at both ends of the bit lines (33) and are arranged alternately.

9. The semiconductor memory according to any one of claims 1 to 8, wherein the semiconductor memory is a dynamic random access memory.