CN210518265U

CN210518265U - Drive circuit of level conversion module

Info

Publication number: CN210518265U
Application number: CN201922189259.6U
Authority: CN
Inventors: 吕强; 孙忠民; 郭靖; 高连山; 赵红武
Original assignee: Xi'an Siyu Microelectronics Co Ltd
Current assignee: Xi'an Siyu Microelectronics Co Ltd
Priority date: 2019-12-07
Filing date: 2019-12-07
Publication date: 2020-05-12
Anticipated expiration: 2029-12-07

Abstract

The utility model provides a level conversion module's drive circuit belongs to the power electronic technology, and this level conversion module's drive circuit includes third PMOS pipe, fourth PMOS pipe, fifth PMOS pipe, sixth PMOS pipe, third NMOS pipe, fourth NMOS pipe, first electric capacity, second electric capacity, first NAND gate and second NAND gate etc.. The utility model discloses can shorten the conversion time of traditional level conversion module more than 50%, reach the response speed in 10ns level, under the prerequisite that does not increase the wide length ratio of MOS pipe in original circuit, promote analog switch's response efficiency by a wide margin.

Description

Drive circuit of level conversion module

Technical Field

The utility model belongs to the power electronic technology especially relates to a drive circuit of level conversion module.

Background

The traditional analog multiplexer chip adopts a high-voltage CMOS process, and the size of a device is larger than that of a low-voltage device, so that parasitic capacitance in a circuit is inevitably increased, and time delay is easily generated in the signal transmission process.

In the prior art, the voltage range of the signals of the DTL/TTL/CMOS interface and the logic control circuit is 0V-15V, however, the output voltage range of the analog switch is-15V, and the signals cannot be directly transmitted due to the different voltage ranges of the two signals, so that a Level Shift module is required to convert the signals of the logic control circuit to the control end of the output switch. The structure of a conventional Level Shift (Level Shift) module is shown in fig. 1.

In fig. 1, since the logic signal converts the voltage signal into the current signal through the first PMOS transistor P1 and the second PMOS transistor P2, and respectively drives the first NMOS transistor N1, the second NMOS transistor N2 and the gate-source capacitor of the output switch to charge, the driving capability is limited due to the influence of the factors such as chip area constraint and front stage matching occupied by the P1 transistor and the P2 transistor, so that the delay is increased. In order to achieve a faster switching speed, a certain current drive is needed, a large power loss is generated during signal switching, and the delay time of a traditional LevelShift module can reach 20-30 ns.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a novel drive circuit can shorten the conversion time of traditional level conversion module more than 50%, reaches the response speed in 10ns level, under the prerequisite that does not increase the width-length ratio of MOS pipe in original circuit, promotes analog switch's response efficiency by a wide margin.

In order to achieve the above object, the embodiments of the present invention adopt the following technical solutions:

the utility model provides a drive circuit of level conversion module, includes third PMOS pipe, fourth PMOS pipe, fifth PMOS pipe, sixth PMOS pipe, third NMOS pipe, fourth NMOS pipe, first electric capacity, second electric capacity, first NAND gate and second NAND gate, wherein: the source electrode of the sixth PMOS tube is connected with V_DDA power supply, a drain electrode of a sixth PMOS tube is respectively connected with a drain electrode of a fourth NMOS tube, the second capacitor and the first input end of the first NAND gate, a grid electrode of the sixth PMOS tube is respectively connected with a grid electrode of the fourth NMOS tube, the second input end of the first NAND gate and a signal control end in the level conversion module, and a source electrode of the fourth NMOS tube is connected with a third NMA source electrode of the OS tube; the output end of the first NAND gate is connected with the grid electrode of a fourth PMOS tube, and the source electrode of the fourth PMOS tube is connected with V_DDThe drain electrode of the fourth PMOS tube is respectively connected with the drain electrode of the first PMOS tube in the level conversion module and the drain electrode of the first NMOS tube; the source electrode of the fifth PMOS tube is connected with V_DDThe drain electrode of a fifth PMOS tube is respectively connected with the drain electrode of a third NMOS tube, the first capacitor and the first input end of the second NAND gate, the grid electrode of the fifth PMOS tube is respectively connected with the grid electrode of the third NMOS tube, the second input end of the second NAND gate and the signal control end in the level conversion module, and the source electrode of the third NMOS tube is grounded through a first resistor; the output end of the second NAND gate is connected with the grid electrode of a third PMOS tube, and the source electrode of the third PMOS tube is connected with V_DDAnd the drain electrode of the third PMOS tube is respectively connected with the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube in the level conversion module.

Preferably, one end of the first capacitor is connected to the drain of the fifth PMOS transistor and the first input end of the second not gate, and the other end of the first capacitor is connected to V_DDA power source. One end of the second capacitor is respectively connected with the drain electrode of the sixth PMOS tube and the first input end of the first NOT gate, and the other end of the second capacitor is connected with the V_DDA power source.

The utility model discloses a drive circuit of level conversion module has following beneficial effect:

the utility model discloses a novel drive circuit can shorten the conversion time of traditional level conversion module more than 50%, reaches the response speed in 10ns level, under the prerequisite that does not increase the width-length ratio of MOS pipe in original circuit, promotes analog switch's response efficiency by a wide margin, makes the design of traditional level conversion module no longer receive the influence of factors such as chip area restraint, preceding stage matching and switching loss.

Drawings

Fig. 1 is a schematic circuit diagram of a conventional level shift module;

fig. 2 is a schematic structural diagram of the present invention.

Detailed Description

The invention is further explained according to the attached drawings:

as shown in fig. 1, in order to increase the switching speed of the conventional level shift module, the first PMOS transistor P1 and the second PMOS transistor P2 must provide a larger driving current, and it is mentioned that the width-to-length ratio of the first PMOS transistor P1 and the second PMOS transistor P2 cannot be simply increased due to the chip area constraint occupied by the first PMOS transistor P1 and the second PMOS transistor P2, the matching with the previous stage, and the switching loss. The circuit in dashed lines in fig. 2 is introduced to increase the drive current and increase the switching speed.

In fig. 2, the driving circuit of the level shifter module includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third NMOS transistor N3, a fourth NMOS transistor N4, a first capacitor C1, a second capacitor C2, a first nand gate I1, and a second nand gate I2.

Wherein: a source electrode of the sixth PMOS transistor P6 is connected to a VDD power supply, a drain electrode of the sixth PMOS transistor P6 is connected to a drain electrode of the fourth NMOS transistor N4, the second capacitor C2 and the first input end of the first nand gate I1, respectively, a gate electrode of the sixth PMOS transistor P6 is connected to a gate electrode of the fourth NMOS transistor N4, the second input end of the first nand gate I1 and the signal control end IN of the level shift module, respectively, and a source electrode of the fourth NMOS transistor N4 is connected to a source electrode of the third NMOS transistor N3; the output end of the first nand gate I1 is connected with the gate of a fourth PMOS tube P4, the source of the fourth PMOS tube P4 is connected with a VDD power supply, and the drain of the fourth PMOS tube P4 is respectively connected with the drain of a first PMOS tube P1 and the drain of a first NMOS tube N1 in the level conversion module; the source of the fifth PMOS transistor P5 is connected to the VDD power supply, the drain of the fifth PMOS transistor P5 is connected to the drain of the third NMOS transistor N3, the first capacitor C1 and the first input terminal of the second nand gate I2, respectively, the gate of the fifth PMOS transistor P5 is connected to the gate of the third NMOS transistor N3, the second input terminal of the second nand gate I2 and the signal control terminal IN the level shift module, respectively, and the source of the third NMOS transistor N3 is grounded through the first resistor R1; the output end of the second nand gate I2 is connected to the gate of a third PMOS transistor P3, the source of the third PMOS transistor P3 is connected to the VDD power supply, and the drain of the third PMOS transistor P3 is connected to the drain of a second PMOS transistor P2 and the drain of a second NMOS transistor N2 in the level shifter module, respectively.

Specifically, one end of the first capacitor C1 is connected to the drain of the fifth PMOS transistor P5 and the first input end of the second not gate I2, respectively, and the other end of the first capacitor C1 is connected to the VDD power supply. One end of the second capacitor C2 is connected to the drain of the sixth PMOS transistor P6 and the first input terminal of the first not gate I1, respectively, and the other end of the second capacitor C2 is connected to the VDD power supply.

The specific working process is as follows: the circuit portion IN the dotted line will increase the drive current during a short time when the signal at the signal control terminal IN changes. After the level shift conversion is completed, the original structure in fig. 1 is restored to maintain the signal level, so that the conversion speed is improved, and the switching loss is reduced. Specifically, when the IN signal changes from "1" to "0", the N3 transistor is turned on, the capacitor C2 is charged through the path of the N3 transistor and the R1 resistor, a short pulse signal a1 is formed at the gate of the P4 transistor through the nand gate I1, the a1 drives the P4 transistor to "help" the P1 transistor to provide driving power flow, so that the driving capability is enhanced, and after the pulse is finished, the P4 transistor is turned off, so that the switching speed is increased, and the power consumption is reduced. Similarly, when the IN signal changes from "0" to "1", the N4 transistor is turned on, the capacitor C1 is charged through the path of the N4 transistor and the R1 resistor, a short pulse signal a2 is formed at the gate of the P3 transistor through the nand gate I2, and the a2 drives the P3 transistor to "help" the P2 transistor to provide the driving power flow. In the traditional Level conversion module, the driving circuit is introduced, so that the conversion time of the Level Shift module can be increased from 20 to 30ns to 8 to 9 ns. The conversion time of the Level Shift module which seriously influences the response time of the analog switch IC is shortened to half of the original conversion time, and the response speed of the analog switch is greatly improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims

1. A driving circuit of a level conversion module comprises a third PMOS transistor (P3), a fourth PMOS transistor (P4), a fifth PMOS transistor (P5), a sixth PMOS transistor (P6), a third NMOS transistor (N3), a fourth NMOS transistor (N4), a first capacitor (C1), a second capacitor (C2), a first NAND gate (I1) and a second NAND gate (I2), wherein:

the source electrode of the sixth PMOS tube (P6) is connected with V_DDThe drain electrode of a sixth PMOS tube (P6) is respectively connected with the drain electrode of a fourth NMOS tube (N4), the second capacitor (C2) and the first input end of a first NAND gate (I1), the grid electrode of the sixth PMOS tube (P6) is respectively connected with the grid electrode of a fourth NMOS tube (N4), the second input end of the first NAND gate (I1) and the signal control end (IN) IN the level conversion module, and the source electrode of the fourth NMOS tube (N4) is connected with the source electrode of the third NMOS tube (N3);

the output end of the first NAND gate (I1) is connected with the gate of a fourth PMOS tube (P4), and the source of the fourth PMOS tube (P4) is connected with V_DDThe drain electrode of the fourth PMOS tube (P4) is respectively connected with the drain electrode of the first PMOS tube (P1) in the level conversion module and the drain electrode of the first NMOS tube (N1);

the source electrode of the fifth PMOS tube (P5) is connected with V_DDThe drain electrode of a fifth PMOS (P5) is respectively connected with the drain electrode of a third NMOS (N3), the first capacitor (C1) and the first input end of a second NAND gate (I2), the grid electrode of the fifth PMOS (P5) is respectively connected with the grid electrode of a third NMOS (N3), the second input end of a second NAND gate (I2) and the signal control end (IN) IN the level conversion module, and the source electrode of the third NMOS (N3) is grounded through a first resistor (R1);

the output end of the second NAND gate (I2) is connected with the grid of a third PMOS tube (P3), and the source of the third PMOS tube (P3) is connected with V_DDAnd the drain electrode of the third PMOS tube (P3) is respectively connected with the drain electrode of the second PMOS tube (P2) in the level conversion module and the drain electrode of the second NMOS tube (N2).

2. The driving circuit of the level shift module as claimed in claim 1, wherein one end of the first capacitor (C1) is connected to the drain of the fifth PMOS transistor (P5) and the first input terminal of the second NOT gate (I2), and the other end of the first capacitor (C1) is connected to V_DDA power source.

3. The driving circuit of the level shifter module as claimed in claim 1, wherein one end of the second capacitor (C2) is connected to the drain of the sixth PMOS transistor (P6) and the first input terminal of the first NOT gate (I1), and the other end of the second capacitor (C2) is connected to V_DDA power source.