CN210484156U - Server fan and BMC fault monitoring circuit based on CPLD - Google Patents
Server fan and BMC fault monitoring circuit based on CPLD Download PDFInfo
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Abstract
The utility model discloses a server fan and BMC fault monitoring circuit based on CPLD, connect with fan and BMC respectively, including the CPLD module, fan state output end output rotational speed feedback signal TACH, fan state output end is connected with BMC input end, CPLD input end respectively; the BMC output end outputs a fan rotating speed control signal PWM, and the BMC output end is respectively connected with the fan control input end and the CPLD input end; the CPLD module triggers an alarm circuit when the corresponding relation between the PWM signal duty ratio and the TACH signal frequency does not meet the specification of a fan manual, and triggers the alarm circuit when the PWM signal is abnormal. The utility model discloses a BMC running state is judged to PWM waveform shape, in time listens and reports to the police when BMC fan control module itself breaks down, has promoted diagnostic speed.
Description
Technical Field
The utility model belongs to the technical field of the fault monitoring technique and specifically relates to a server fan and BMC fault monitoring circuit based on CPLD.
Background
At present, the integration level of servers is higher and higher, especially blade servers, AI servers special for artificial intelligent computation and the like, which integrate a plurality of CPUs, GPUs, memory banks, hard disks and the like in a smaller case space, and the high-integration server provides higher performance and also increases the pressure of case heat dissipation. At present, the heat in the chassis is still taken away by the common heat dissipation mode of the server through the air draft or blowing of the fan, and the heat dissipation capacity of the fan influences the working performance of the air-cooled server to a great extent. Because the fan is always in a high-speed running state after the server is started, the fan shaft has poor lubrication degree due to long-time abrasion and dust accumulation, the noise of the fan is increased, the rotating speed of the fan is reduced, and a machine core can be burned out in serious cases to influence the normal operation of a machine. At present, fans on the servers mainly adopt a four-wire system control mode, and the rotating speed of the fans is directly regulated and controlled by the BMC according to temperature data sent back by the temperature sensor. Therefore, in order to ensure that the server can operate normally and continuously for a long time, real-time monitoring of the faults of the fan and the BMC is particularly important.
At present, fans on servers mainly adopt a four-wire control mode, as shown in fig. 1, a PWM pulse width modulation signal determining the rotation speed of the fan is directly sent out by a BMC chip on a motherboard to be connected to the fan, the duty ratio of a PWM square wave signal with a fixed period (the proportion of a high level period of the square wave signal in the whole period) determines the operation speed of the fan, and the larger the duty ratio is, the larger the rotation speed of the fan is; the TACH signal, which is fed back by the fan and is indicative of the actual speed, is typically connected to a dedicated TACH pin of the BMC, the TACH signal being a square wave signal with a 50% duty cycle, and the higher the fan speed the higher the TACH signal frequency. In many server designs at present, after being connected to the BMC, the TACH signal is not further processed except for being converted and translated into a rotating speed value, and under the condition, even if the rotating speed is abnormal after the fan fails, effective monitoring measures and alarm designs are not provided; the method comprises the following steps that part of servers compare the difference between an output signal PWM and an input signal TACH by using a BMC to judge the running state of a fan, but both the PWM signal and the TACH signal are operated by the BMC, when a fan control module in the BMC breaks down, the running condition of the fan is difficult to control and judge, and peripheral chips such as PCA9555 and the like are often additionally arranged on a board card in the design; at present, fault monitoring of BMC generally uses WATCHDOG signals, and fault detection risk exists when BMC faults are monitored through single signals.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a server fan and BMC fault monitoring circuit based on CPLD accomplishes the monitoring of fan running state and BMC operation in CPLD, has promoted diagnostic speed.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
the utility model provides a server fan and BMC fault monitoring circuit based on CPLD, is connected with fan and BMC respectively, characterized by, including the CPLD module, fan state output end output rotational speed feedback signal TACH, fan state output end is connected with BMC input, CPLD input respectively; the BMC output end outputs a fan rotating speed control signal PWM, and the BMC output end is respectively connected with the fan control input end and the CPLD input end; and when the corresponding relation between the PWM signal duty ratio and the TACH signal frequency which is not regulated by a fan manual is not met, the CPLD module triggers an alarm circuit when the PWM signal is abnormal.
Further, the CPLD module is respectively connected with the clock input unit and the LED display unit.
Furthermore, the CPLD module comprises a PWM signal edge detection unit and a PWM signal counting unit which are sequentially connected, a TACH signal edge detection unit and a TACH signal counting unit which are sequentially connected, a table look-up judgment unit and an alarm driving unit; the BMC output end is connected with the PWM signal edge detection unit, and the fan state output end is connected with the TACH signal edge detection unit; the output end of the PWM signal counting unit and the output end of the TACH signal counting unit are respectively connected with the input end of the table look-up judging unit, and the output end of the table look-up judging unit is connected with the alarm driving unit.
Further, the PWM signal edge detection unit includes a PWM signal rising edge detection circuit and a PWM signal falling edge detection circuit; the PWM signal rising edge detection circuit comprises a plurality of D triggers and phase inverters which are sequentially connected, and the clock input end of each D trigger is externally connected with a clock input unit; and the output of the phase inverter is connected with the input end of the PWM signal counting unit.
Further, the TACH signal edge detection unit comprises a TACH signal rising edge detection circuit and a TACH signal falling edge detection circuit; the TACH signal rising edge detection circuit comprises a plurality of D triggers and phase inverters which are sequentially connected, and the clock input end of each D trigger is externally connected with a clock input unit; and the output of the phase inverter is connected with the input end of the TACH signal counting unit.
Further, the table lookup judgment unit stores the PWM duty ratio m and the TACH signal frequency f defined by the fan manualTACHAnd the table look-up judging unit compares the two input end signals, and outputs a control signal to the alarm driving unit when the two input end signals do not meet the corresponding relation defined by the fan manual.
The effects provided in the contents of the present invention are only the effects of the embodiments, not all the effects of the present invention, and one of the above technical solutions has the following advantages or advantageous effects:
the utility model provides a server fan and BMC fault monitoring circuit based on CPLD. According to the method, the PWM signal and the TACH signal are simultaneously accessed into the CPLD, the monitoring of the running state of the fan is completed inside the CPLD, the resources inside the BMC are saved, the fault monitoring based on the CPLD hardware logic circuit has higher response speed, and peripheral chips such as PCA9555 are saved; at present, fault monitoring of BMC itself generally uses WATCHDOG signals, fault monitoring of BMC through single signal has error detection risk, BMC running state can be judged through PWM waveform form to this patent, in time detection and alarm when fault occurs in BMC fan control module itself, diagnosis speed has been promoted.
Drawings
FIG. 1 is a schematic view of a prior art fan operation monitoring;
fig. 2 is a schematic diagram of a hardware circuit structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of PWM signal edge detection;
FIG. 4 is a schematic diagram of the detection of the TACH signal edges;
FIG. 5 is a schematic diagram of a falling edge detection circuit;
FIG. 6 is a schematic diagram of a rising edge detection circuit;
101, a server four-wire system cooling fan, 102, an on-board BMC chip, 103, a PWM signal, 104, a TACH signal, 105, a pull-up resistor, 106, a pull-up resistor, 107, a CPLD chip, 108, an edge detection circuit of the PWM signal, 109, a clock counting and operation unit, 110, an edge detection circuit of the TACH signal, 111, a clock counting and operation unit, 112, a lookup table-judging circuit, 113, an alarm driving unit, 114, a control fault lamp, 115 and a crystal oscillator.
Detailed Description
In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.
As shown in fig. 2, a server fan and BMC fault monitoring circuit based on CPLD is respectively connected to a fan 101 and a BMC102, and includes a CPLD module 107, a fan state output end outputs a rotation speed feedback signal TACH, and the fan state output end is respectively connected to a BMC input end and a CPLD input end; the BMC output end outputs a fan rotating speed control signal PWM, and the BMC output end is respectively connected with the fan control input end and the CPLD input end; the CPLD module triggers an alarm circuit when the corresponding relation between the PWM signal duty ratio and the TACH signal frequency does not meet the regulation of a fan manual, and triggers the alarm circuit when the PWM signal is abnormal. The CPLD module is also connected to a crystal oscillator 115 and a control failure lamp 114, respectively.
The function of the edge detection circuit 108 for PWM signals is to detect the rising edge and the falling edge of the PWM square wave signal under the system clock; the clock counting and calculating unit 109 specifically functions to start counting the system clock every time the rising edge of the PWM signal is detected by the clock counting and calculating unit 108, as shown in fig. 3, then record the count value when the falling edge of the PWM signal is detected by the clock counting and calculating unit 108 so as to obtain the high level time Th1 of the PWM signal, and record the count value when the rising edge of the PWM signal is detected again by the clock counting and calculating unit 108 so as to obtain the period Tpwm of the PWM signal, at which time the counter is cleared to start a new round of detection. And obtaining the duty ratio m of the current PWM signal by taking the ratio of the high level time Th1 of the PWM signal to the period Tpwm of the PWM signal.
As shown in fig. 4, the function of the edge detection circuit 110 for the TACH signal is to detect the rising edge and the falling edge of the TACH square wave signal under the system clock; the clock count and operation unit 111 functions to start counting the system clock every time the 110 detects a rising edge of the TACH signal and to end counting every time the 110 detects a falling edge of the TACH signal, thereby obtaining the high level time T of the TACH signalh2The frequency of the obtained TACH signal is fTACH＝1/(2Th2)。
As shown in fig. 5, wherein 201 is a typical D flip-flop, the input signal D is a PWM or TACH signal, CLK 'is a system clock, Q is an output signal of the signal D delayed by one beat of clock by the flip-flop, and Q' is an inverted output signal of Q, which is not used in the present invention. The input signal RST is a reset signal that is active high or low and functions to asynchronously reset the D flip-flop. The function of 201 is to filter out glitches in the PWM and TACH input signals based on the fact that the D flip-flop is insensitive to glitches.
202 and 203 are typical D triggers, the input signal D is the Q end output signal of the front trigger, the two-stage D trigger is used for filtering part of glitch signals in the key input signal and providing input for 204; 205 is a digital inverter circuit whose function is to logically invert the Q output signal of 202. 204 is a logic and gate stage circuit, one end of which inputs a signal as the output of the Q end of the preceding stage D flip-flop and the other end of which inputs the output of the inverter 203; a "1" output at 204 indicates that a falling edge of the PWM or TACH signal has been detected. Similarly, the rising edge detection circuit is shown in fig. 6 and is not described in detail.
The look-up table-judging circuit 112 stores the correspondence between the PWM duty ratio m and the TACH signal frequency fTACH defined by the fan manual. The module 112 carries out comparison and judgment, and if the m and fTACH data output by the modules 109 and 111 can correspond to each other and meet the specification of a fan manual, the LED 114 does not give an alarm; if the two can not satisfy the corresponding relation defined by the fan manual, the 113 will drive the 114LED to alarm.
When the PWM signal continuous duty ratio detected by 112 is 100% and exceeds a certain time t, the BMC is in fault or the server system is continuously overheated, 113 drives and lights 114 an LED alarm prompt; or when the PWM signal period Tpwm detected by 112 is not the standard period duration defined by the fan manual, it represents that the BMC has a fault, and 113 will also drive to light 114 the LED alarm reminder.
The utility model discloses to only insert BMC's fan control signal PWM and rotational speed feedback signal TACH originally and inserted CPLD simultaneously, utilize border detection circuitry to draw rising edge and falling edge of PWM and TACH signal to this obtains actual PWM waveform cycle and duty cycle data, and obtains the frequency of TACH signal, thereby monitoring server fan running state, and can judge the BMC trouble according to PWM waveform form.
The utility model discloses mainly be applied to the detection of the trouble of the fan on the server, above-mentioned border detection circuitry detects the rising edge and the falling edge of PWM and TACH signal, and drive clock count and arithmetic unit begin the count respectively to obtain PWM signal duty cycle. Suppose m is 75% and the frequency f of the TACH signalTACH＝1/(2Th2) When the frequency is 10000Hz, the lookup table-judgment circuit judges whether 75 percent and 10000Hz meet the corresponding relation specified by a fan manual, if the manual specifies that the duty ratio of PWM 75 percent corresponds to the TACH feedback frequency of 10000Hz, the LED does not give an alarm; if the two can not meet the corresponding relation defined by the fan manual, the LED is driven to be lightened for alarming. When the PWM signal is detected to have a continuous duty ratio of 100% for a certain time, t is assumed to be equal toWhen 5 minutes, the BMC is in failure or the server system is continuously overheated, and the LED is driven to be lightened for warning and reminding; or when the detected PWM signal period TpwmIf the standard period time length is not defined by the fan manual, the fault occurs on the BMC, and the LED alarm prompt is driven to be lightened.
Although the present invention has been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without inventive work are still within the scope of the present invention.
Claims (6)
1. A server fan and BMC fault monitoring circuit based on CPLD is respectively connected with a fan and a BMC, and is characterized by comprising a CPLD module, wherein a fan state output end outputs a rotating speed feedback signal TACH, and the fan state output end is respectively connected with a BMC input end and a CPLD input end; the BMC output end outputs a fan rotating speed control signal PWM, and the BMC output end is respectively connected with the fan control input end and the CPLD input end; and when the corresponding relation between the PWM signal duty ratio and the TACH signal frequency which is not regulated by a fan manual is not met, the CPLD module triggers an alarm circuit when the PWM signal is abnormal.
2. The CPLD-based server fan and BMC fault monitoring circuit of claim 1, wherein the CPLD module is further connected with a clock input unit and an LED display unit, respectively.
3. The CPLD-based server fan and BMC fault monitoring circuit according to claim 2, wherein the CPLD module comprises a PWM signal edge detection unit and a PWM signal counting unit connected in sequence, a TACH signal edge detection unit and a TACH signal counting unit connected in sequence, a table look-up judgment unit, an alarm driving unit; the BMC output end is connected with the PWM signal edge detection unit, and the fan state output end is connected with the TACH signal edge detection unit; the output end of the PWM signal counting unit and the output end of the TACH signal counting unit are respectively connected with the input end of the table look-up judging unit, and the output end of the table look-up judging unit is connected with the alarm driving unit.
4. The CPLD-based server fan and BMC fault monitoring circuit of claim 3, wherein the PWM signal edge detection unit includes a PWM signal rising edge detection circuit and a PWM signal falling edge detection circuit; the PWM signal rising edge detection circuit comprises a plurality of D triggers and phase inverters which are sequentially connected, and the clock input end of each D trigger is externally connected with a clock input unit; and the output of the phase inverter is connected with the input end of the PWM signal counting unit.
5. The CPLD-based server fan and BMC fault monitoring circuit of claim 3, wherein the TACH signal edge detection unit includes a TACH signal rising edge detection circuit and a TACH signal falling edge detection circuit; the TACH signal rising edge detection circuit comprises a plurality of D triggers and phase inverters which are sequentially connected, and the clock input end of each D trigger is externally connected with a clock input unit; and the output of the phase inverter is connected with the input end of the TACH signal counting unit.
6. The CPLD-based server fan and BMC fault monitoring circuit as claimed in claim 3, wherein the lookup table determining unit stores PWM duty cycle m and TACH signal frequency f defined by fan manualTACHAnd the table look-up judging unit compares the two input end signals, and outputs a control signal to the alarm driving unit when the two input end signals do not meet the corresponding relation defined by the fan manual.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112032079A (en) * | 2020-08-03 | 2020-12-04 | 苏州浪潮智能科技有限公司 | Server fan PWM signal frequency detection device and method |
| CN113608944A (en) * | 2021-07-30 | 2021-11-05 | 联想长风科技(北京)有限公司 | Server fan fault detection system and method |
| CN114137347A (en) * | 2021-11-26 | 2022-03-04 | 北京经纬恒润科技股份有限公司 | Fault diagnosis method, calibration method and device for heat dissipation system |
| CN114691436A (en) * | 2022-03-30 | 2022-07-01 | 西安易朴通讯技术有限公司 | Server mainboard, server and signal control method |
| CN117271272A (en) * | 2023-11-22 | 2023-12-22 | 湖南博匠信息科技有限公司 | BMC-based fan in-place state monitoring method and system |
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2019
- 2019-08-09 CN CN201921285519.3U patent/CN210484156U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112032079A (en) * | 2020-08-03 | 2020-12-04 | 苏州浪潮智能科技有限公司 | Server fan PWM signal frequency detection device and method |
| CN113608944A (en) * | 2021-07-30 | 2021-11-05 | 联想长风科技(北京)有限公司 | Server fan fault detection system and method |
| CN114137347A (en) * | 2021-11-26 | 2022-03-04 | 北京经纬恒润科技股份有限公司 | Fault diagnosis method, calibration method and device for heat dissipation system |
| CN114137347B (en) * | 2021-11-26 | 2024-05-07 | 北京经纬恒润科技股份有限公司 | Fault diagnosis method, verification method and device for heat dissipation system |
| CN114691436A (en) * | 2022-03-30 | 2022-07-01 | 西安易朴通讯技术有限公司 | Server mainboard, server and signal control method |
| CN117271272A (en) * | 2023-11-22 | 2023-12-22 | 湖南博匠信息科技有限公司 | BMC-based fan in-place state monitoring method and system |
| CN117271272B (en) * | 2023-11-22 | 2024-02-02 | 湖南博匠信息科技有限公司 | BMC-based fan in-place state monitoring method and system |
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