CN210381138U - 4K video trapezoidal correction system - Google Patents
4K video trapezoidal correction system Download PDFInfo
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- CN210381138U CN210381138U CN201921158567.6U CN201921158567U CN210381138U CN 210381138 U CN210381138 U CN 210381138U CN 201921158567 U CN201921158567 U CN 201921158567U CN 210381138 U CN210381138 U CN 210381138U
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- 230000002093 peripheral effect Effects 0.000 claims abstract description 8
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- 238000006243 chemical reaction Methods 0.000 description 4
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- 238000010586 diagram Methods 0.000 description 1
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Abstract
The utility model discloses a trapezoidal correction system of 4K video mainly relates to the laser television field. The system comprises an IP00C381, a peripheral circuit thereof, a memory, a power supply set, a video data transmission circuit and a control interface circuit; the IP00C381 is respectively communicated with the front end MCU and the rear end DLP of the projector through a video data transmission circuit; the peripheral circuit comprises a clock generating circuit and a reset circuit; the power supply group comprises a power supply and a DC-DC power supply circuit for supplying power to each power supply voltage; the control interface circuit comprises a front end MCU control interface circuit and a PC control interface circuit. The beneficial effects of the utility model reside in that: the image is processed by the IP00C381 image processor, and the input image is processed and then mapped to the DMD array again, so that a rectangular image is generated on a screen, and trapezoidal correction is achieved.
Description
Technical Field
The utility model relates to a projector field specifically is trapezoidal correction system of 4K video.
Background
The projector is installed in a customer home, a video needs to be opened when the projector is used for the first time, the position of the projector is adjusted according to the position of a projected image, and the fact that a projection optical axis is perpendicular to a screen is guaranteed. The heights of the four legs of the projector are then adjusted according to the shape of the projected image to render the image projected onto the screen as rectangular as possible. When the optical axis of the projection system is not perpendicular to the imaging screen, the image may be geometrically distorted. One type of distortion is caused by the different distances from the top and bottom of the screen, called keystone distortion. The final image has different widths from top to bottom, so that the image is arched and cannot meet the requirements of viewing the film.
Keystone distortion can be corrected by optical or image processing means, but optical adjustment is difficult, expensive, and poorly adjustable. Therefore, the image processing method becomes the preferred keystone correction method. DDP4422-HV main control chip manufactured by TI company integrates a 2D Keystone correction function and supports a trapezoidal correction function with the image resolution of 2K, so that the circuit structure is simple and much, the debugging is convenient, but the trapezoidal correction image processing of 4K ultra-high definition images is not supported.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a 4K video trapezoidal correction system, it has solved the problem of the clear image keystone distortion of 4K superelevation, through IP00C381 image processor, remaps to the DMD array behind the image processing of will inputing to generate rectangular image on the screen, realize trapezoidal correction.
The utility model discloses a realize above-mentioned purpose, realize through following technical scheme:
the 4K video trapezoidal correction system comprises an IP00C381 and a peripheral circuit thereof, a memory, a power supply set, a video data transmission circuit and a control interface circuit; the IP00C381 is communicated with the front-end MCU and the rear-end DLP through video data transmission circuits respectively; the peripheral circuit generates a clock signal; the memory comprises DDR3 memory chips, and the DDR3 memory chips are communicated with the IP00C381 through an address bus and a data bus; the power supply group comprises a power supply and a DC-DC power supply circuit for supplying power to each power supply voltage, and is controlled by a main control circuit of the front-end MCU; the control interface circuit comprises a front end MCU control interface circuit and a PC control interface circuit, and the PC interface circuit is communicated with the IP00C381 and the computer.
Preferably, the peripheral circuit includes a clock generation circuit and a reset circuit.
Preferably, the video data transmission circuit adopts a V-by-one video transmission standard, and the interface of the video data transmission circuit is a 51pin connector.
Preferably, the memory comprises 4 DDR memory chips, and the data bus to IP00C381 adopts single-ended 85 ohm impedance; the address bus adopts a fly-by wiring mode, and the wiring is single-ended 85 ohm impedance; the IP00C381 to the 4 DDR3 memory chips are respectively controlled in an equal length mode.
Preferably, the DC-DC power circuit includes a 12V to 5V circuit, a 5V to 1.1V circuit, a 5V to 3.3V circuit, a 5V to 1.5V circuit, a 3.3V to 1.8V circuit, and a 3.3V to 0.75V circuit.
Preferably, the front end MCU control interface circuit adopts SPI serial communication mode configuration IP00C381, PC control interface circuit and front end MCU control interface circuit share SPI interface, the external SPI changes USB debug tool, SPI changes USB debug tool intercommunication computer.
Contrast prior art, the beneficial effects of the utility model reside in that:
the utility model discloses a data transmission circuit communicates IP00C381 and front end MCU, rear end DLP respectively, with the help of IP00C381, the power supply group, image processing function is realized in memory and relevant circuit cooperation, utilize computer configuration IP00C381 through PC control interface circuit, under front end MCU's control, with the help of the image processing function of this application, 4K image after will handling remaps DLP's DMD array again, thereby generate the rectangle image on the screen, realize trapezoidal correction.
Drawings
Fig. 1 is a circuit configuration diagram of a preferred embodiment of the present invention.
Fig. 2 is a V-by-one interface for video data input according to the present invention.
Fig. 3 is a V-by-one interface for video data output according to the present invention.
Fig. 4 shows an external DDR3 circuit of the IP00C381 of the present invention.
Fig. 5 shows a 12V to 5V power circuit of the present invention.
Figure 6 is the utility model discloses a 5V changes 3.3V power supply circuit.
Fig. 7 is a 5V to 1.5V power supply circuit of the present invention.
Fig. 8 is a control interface circuit of the present invention.
Detailed Description
The present invention will be further described with reference to the following specific examples.
Example (b): the 4K video trapezoidal correction system comprises an IP00C381, a clock generation circuit, a reset circuit, a memory, a power supply set, a video data transmission circuit and a control interface circuit; the IP00C381 image processor supports 4 paths of 4K @60HZ image input and 2 paths of 4K @60HZ image output; for 4K @60HZ images, free laminated display processing of 4 pictures can be supported, a 90-degree rotation function is supported, and an input/output interface supports a V-by-one interface. The IP00C381 is communicated with a front end MCU and a rear end DLP of the projector through video data transmission circuits respectively, the front end MCU is a main control chip of a correction system, video source data are received and processed and transmitted to the IP00C381 through the video data transmission circuit by adopting a V-by-one standard, the front end MCU can receive infrared or Bluetooth control signals, the front end MCU controls an IP00C381 image processor after receiving a remote control command of a user, the IP00C381 processes an image according to the front end MCU command and then transmits the image to the rear end DLP through the video data transmission circuit by adopting the V-by-one standard, the rear end DLP is a projector mainboard and controls a DMD array micromirror to project the image after receiving the video data. The interface of the video data transmission circuit adopts a 51pin socket FI-RE51S-HF, and two ends of the interface are provided with lock catches, so that the video data transmission circuit is convenient and firm to connect and plug. The memory comprises 4 DDR3 memory chips, the 4 DDR3 chips are communicated with the IP00C381 through an address bus and a data bus, and the part from the data bus to the IP00C381 adopts single-ended 85 ohm impedance and is additionally subjected to equal-length delay control; the address line adopts the fly-by way of routing, and the wiring is single-ended 85 ohm impedance, and in addition IP00C381 to 4 DDR3 memory chips do isometric control respectively, can effectually avoid signal attenuation, reduce signal delay, reinforcing anti-interference heat nature. The power supply set comprises an external power supply and a DC-DC power supply circuit for supplying power to each power supply voltage, the DC-DC power supply circuit comprises three stages of direct-current power supply conversion, a first stage is a circuit for converting input voltage 12V into 5V, the first stage is used as an input power supply of a second stage conversion circuit, and the output power is 10W; the second-stage power supply conversion comprises a circuit from 5V to 1.1V, a circuit from 5V to 3.3V and a circuit from 5V to 1.5V, and respectively supplies power to an IP00C381 kernel, a phase-locked loop and an input/output port, and supplies power to DDR3 by 1.5V; and the third stage is that the LDO power conversion circuit comprises a 3.3V-to-1.8V circuit and a 3.3V-to-0.75V circuit, and provides a pull-up power supply for an IP00C381 clock circuit and a DDR3 termination resistor respectively. The power supply group is controlled by a main control circuit of the front-end MCU and supplies power to the circuit board after receiving the power-on signal. Control interface circuit includes front end MCU control interface circuit, PC control interface circuit, front end MCU control interface circuit adopts SPI serial communication mode configuration IP00C381, PC control interface circuit and front end MCU control interface circuit sharing SPI interface, external SPI changes USB debug, SPI changes USB debug intercommunication computer, through computer software configuration IP00C381, need use computer configuration IP00C381 after first installation or removal projector.
Claims (6)
1.4K video trapezoidal correction system, its characterized in that: the system comprises an IP00C381, a peripheral circuit thereof, a memory, a power supply set, a video data transmission circuit and a control interface circuit;
the IP00C381 is communicated with the front-end MCU and the rear-end DLP through video data transmission circuits respectively;
the peripheral circuit generates a clock signal;
the memory comprises DDR3 memory chips, and the DDR3 memory chips are communicated with the IP00C381 through an address bus and a data bus;
the power supply group comprises a power supply and a DC-DC power supply circuit for supplying power to each power supply voltage, and is controlled by a front-end MCU;
the control interface circuit comprises a front end MCU control interface circuit and a PC control interface circuit, and the PC control interface circuit is communicated with the IP00C381 and the computer.
2. The 4K video keystone correction system of claim 1, wherein: the peripheral circuit includes a clock generation circuit and a reset circuit.
3. The 4K video keystone correction system of claim 1, wherein: the video data transmission adopts a V-by-one video transmission standard, and the interface of the video data transmission circuit is a 51pin connector.
4. The 4K video keystone correction system of claim 1, wherein: the memory comprises 4 DDR memory chips, and a single-ended 85 ohm impedance is adopted from the data bus to the IP00C 381; the address bus adopts a fly-by wiring mode, and the wiring is single-ended 85 ohm impedance; the IP00C381 to the 4 DDR3 memory chips are respectively controlled in equal length.
5. The 4K video keystone correction system of claim 1, wherein: the DC-DC power supply circuit comprises a circuit for converting 12V into 5V, a circuit for converting 5V into 1.1V, a circuit for converting 5V into 3.3V, a circuit for converting 5V into 1.5V, a circuit for converting 3.3V into 1.8V and a circuit for converting 3.3V into 0.75V.
6. The 4K video keystone correction system of claim 1, wherein: the front end MCU control interface circuit adopts SPI serial communication mode configuration IP00C381, PC control interface circuit and front end MCU control interface circuit sharing SPI interface, the outer SPI of joining in marriage changes USB debug, SPI changes USB debug and communicates the computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921158567.6U CN210381138U (en) | 2019-07-23 | 2019-07-23 | 4K video trapezoidal correction system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921158567.6U CN210381138U (en) | 2019-07-23 | 2019-07-23 | 4K video trapezoidal correction system |
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| Publication Number | Publication Date |
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| CN210381138U true CN210381138U (en) | 2020-04-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201921158567.6U Active CN210381138U (en) | 2019-07-23 | 2019-07-23 | 4K video trapezoidal correction system |
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| CN (1) | CN210381138U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113691786A (en) * | 2020-05-18 | 2021-11-23 | 青岛海信激光显示股份有限公司 | Laser projection system and starting method thereof |
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2019
- 2019-07-23 CN CN201921158567.6U patent/CN210381138U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113691786A (en) * | 2020-05-18 | 2021-11-23 | 青岛海信激光显示股份有限公司 | Laser projection system and starting method thereof |
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