CN2103572U - Electronic controller for card-punching apparatus - Google Patents
Electronic controller for card-punching apparatus Download PDFInfo
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- CN2103572U CN2103572U CN 91221867 CN91221867U CN2103572U CN 2103572 U CN2103572 U CN 2103572U CN 91221867 CN91221867 CN 91221867 CN 91221867 U CN91221867 U CN 91221867U CN 2103572 U CN2103572 U CN 2103572U
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- punching apparatus
- data
- interface
- cpu
- card
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Abstract
The utility model relates to an electronic controller for a card punching apparatus, which is made of jacquard weave tricot cards. For solving the bottleneck phenomenon that the plan of weave information is input manually in an electronic card punching apparatus, the utility model adopts large-scale circuit devices, such as a central processing unit, semiconductor memories, an interface circuit, etc., the data file of the plan of weave can be directly transformed, and the utility model can automatically control the electronic card punching apparatus accomplish the perforating work of the entire cards from start to finish, for accelerating the renewal of the designs and colors, and varieties of jacquard weave tricot and increasing the production efficiency of the jacquard weave tricot. The electronic controller for card punching apparatus can be widely suitable for the production of the jacquard weave tricot in the textile industry.
Description
The utility model relates to the electronics card-punching apparatus controller that a kind of jacquard warp-knitted figured cloth line version is made.
At present, China most jacquard warp-knitted figured cloth manufacturer uses the jacquard weave of Jacquard line version through compiling textile machine, and it controls the decorative pattern braiding with Jacquard line version by Jacquard device and some coupling mechanism.The making of Jacquard line version needs several different technical process, at first conceive pattern by the art director, secondly the sample of drawing or full-page proof sketch put artistic conception by the technologist according to sketch, again by manually single-frame line by line figure, color and the position of plan of weave being sent in the electronics card-punching apparatus by plan of weave.The electronics card-punching apparatus is controlled by two central processing units, its primary processor is responsible for the information input, compiling and to from the processor Data transmission, control the motion of mechanical punch pin from processor, because the electronics card-punching apparatus all is by artificial key entry data, so can only beat the delegation hole at every turn, efficient is extremely low, reason is manually to read each lattice of plan of weave with vision, and then lean on keyboard to key in the information of each lattice to the electronics card-punching apparatus, pierce complicated Jacquard line version like this and often need time of some months, seriously restricted the change of designs and varieties of warp knitted jacquard fabric and the efficient of production.
On the other hand along with the extensive use of CAD (CAD), the artificial plan of weave of drawing can be drawn out by CAD and automatically generated data file or by plotter, therefore " bottleneck " phenomenon that solves the making from plan of weave to Jacquard line version is to improving the production efficiency of jacquard warp-knitted figured cloth, and the update of accelerating the jacquard warp-knitted figured cloth designs and varieties has great significance.
The data file that the purpose of this utility model is to use micro-computer technology that CAD is generated is converted to can be by electronics card-punching apparatus institute's recognition data and instruction, thereby the primary processor that can replace the electronics card-punching apparatus finishes up to whole line versions perforation making directly to also controlling the perforation of finishing every capable information from processor automatically from the processor Data transmission.
The utility model comprises:
Central processor CPU, its multidigit BDB Bi-directional Data Bus DBUS links to each other with the long numeric data line of stored program read only memory ROM with the random access memory ram of storage data, its multidigit address bus ABUS links to each other with the multidigit address wire of input, ROM and the RAM of decoding circuit, and the output of decoding circuit links to each other with the buffer of ROM, RAM and interface circuit, the control end of latch respectively;
Interface circuit shows that by card-punching apparatus interface, keyboard input interface, the state of the I/O of analog switch control data signal and control signal output interface, data file input interface are constituted;
The oscillating circuit that it also comprises the power circuit that D.C. regulated power supply can be provided and high frequency clock signal can be provided.
Card-punching apparatus interface of the present utility model is made of multichannel alternative electronic analog swtich, and four data lines of data bus dbus are as D
0, D
1, D
2And D
3Through meeting the W of electronic analog swtich behind the data latches respectively
0, X
0, Y
0And Z
0Input is so that with the RESET that resets of the utility model CPU
0, data DATA
0, data gating DATACLOCK
0With perforation order PUNCH
0Deng export to the electronics card-punching apparatus from processor; Its U
0And V
0Input can connect two data lines of DBUS respectively through three state buffer, as D
4And D
5, so that receive from the electronics card-punching apparatus from signals such as the ready START of processor and the busy CARD of punch; Its U, V, W
1, X
1, Y
1And Z
1Input is the input signal from the electronics card-punching apparatus, as the reset RESET of electronics card-punching apparatus from the ready START of processor, the busy CARD of punch, primary processor
1, data DATA
1, data gating DATACLOCK
1With perforation order PUNCH
1U
1, V
1, W, X, Y and Z output be the signal to the output of electronics card-punching apparatus, as the ready START to primary processor output
1With the busy CARD of punch
1, to the RESET that resets, data DATA, data gating DATACLOCK and perforation order PUNCH from processor output; The switching signal line of its conversion and control end C and CPU control links to each other, so that make the electronics card-punching apparatus be in control of the present utility model or be in the control of electronics card-punching apparatus primary processor.
The conversion and control end C of the electronic analog swtich that switching signal of the present utility model is controlled can be through the decoder gating and through latch by the cpu address line, perhaps the road output signal line of data wire behind latch controlled, controlled by the control signal end of CPU itself, controlled by the output of single-pole double-throw switch (SPDT) behind the steady-state circuit of cancel key shake, when C is high level, electronic analog swtich gating " 1 " passage makes the electronics card-punching apparatus be in the control of self primary processor, when C was low level, passage 0 gating made the electronics card-punching apparatus be in control of the present utility model; Electronic analog swtich of the present utility model also can adopt the mechanical type band switch to replace, and its conversion and control need be by carrying out manually.
Data file input interface of the present utility model can CPU serial transmitting terminal TXD, the receiving terminal RXD serial input interface that connects level translator respectively and constituted, as RS-232 type serial input interface, level translator can select for use 1488(to send) and the 1489(reception) etc. chip, it also can be the serial communication interface that constitutes by serial communication control and level translator able to programme, as Z80-SIO or Intel8250, so that use with other computer interconnection.
Data file input interface of the present utility model can also be the Floppy Disk Controller interface, so that be connected with floppy disk.
CPU of the present utility model is only had a chip of central processing function, cpu chip as MC6800, Intel8000 and Z80 series, also can be CPU with RAM or (with) ROM(or EPROM or PROM) the one-chip computer chip that becomes one, as the one-chip computer of MCS48,51,96 series.
Advantage of the present utility model is to utilize microcomputer technology manually to become the perforation work of finishing whole line version with direct translation data information of micro computer and automatic control electronics card-punching apparatus from start to finish with vision reading plan of weave and manual its information of keying in, thereby solved " bottleneck " phenomenon that jacquard warp-knitted figured cloth Jacquard line version is made, accelerate the update of jacquard warp-knitted figured cloth designs and varieties, improved the production efficiency of jacquard warp-knitted figured cloth greatly.
Fig. 1 is the microcomputer control circuit theory diagram of the utility model embodiment, and it is as Figure of abstract.
Fig. 2 is the circuit diagram that the utility model adopts one-chip computer.
Fig. 3 is the utility model embodiment program flow diagram.
Fig. 4 is the utility model embodiment subroutine flow chart of boring a hole.
Further specify below in conjunction with accompanying drawing:
Show output interface, keyboard input interface and data file input interface by the utility model shown in Figure 1 by central processor CPU, random access memory ram, read only memory ROM, card-punching apparatus interface, state, and circuit such as power supply, work clock constitute, and its data bus dbus and address bus ABUS also can be the data/address bus that timesharing is used.
CPU of the present utility model can adopt 8031 type one-chip computers of MCS51 series, it adopts+the 5V DC power supply, have eight bidirectional data lines, ROM among Fig. 2 can be 2732, it is the erasable read-only memory EPROM of 4K byte, RAM can be 62256, it is the random access memory of 32K byte, the data bus dbus of 8031 one-chip computers links to each other with the long numeric data line of EPROM, RAM, also is connected with the latch LS273 of interface circuit and the input of three state buffer LS244 simultaneously; DBUS is becoming the address bus ABUS that timesharing is used behind latch LS373, and links to each other with the multidigit address wire of EPROM, RAM, the input of decoder LS138; The output of LS138 links to each other with buffer LS244 control end with the latch LS273 of RAM, EPROM, interface circuit respectively.
Interface circuit shows that by card-punching apparatus interface, keyboard input interface, state output interface, data file input interface are constituted.
Wherein: the card-punching apparatus interface is made of the three state buffer LS244 of two four-way alternative electronic analog swtich 14551, a slice latch LS273 and 1/2, and 14551A goes into one as two and goes out switch and use its input W
0, X
0, Y
0And Z
0Be that the utility model prepares the signal to the output of electronics card-punching apparatus, respectively by the D of DBUS
0, D
1, D
2And D
3Export 14551 W to through latch LS273
0, X
0, Y
0And Z
0, it is respectively to the reset RESET of electronics card-punching apparatus from processor output
0, data DATA
0, data gating DATACLOCK
0With perforation order PUNCH
0, other is four input W
1, X
1, Y
1And Z
1The RESET that resets from electronics card-punching apparatus primary processor
1, data DATA
1, data gating DATACLOCK
1With perforation order PUNCH
1, W
0, W
1Constitute two positions of a way switch, and its output is W, other three-way switch is as the same.So its output W, X, Y and Z are respectively the RESET that resets, data DATA, data gating DATACLOCK and perforation order PUNCH, and export to the electronics card-punching apparatus from processor, bore a hole with the information that control electronics card-punching apparatus is carried by data wire DATA serial.14551B goes into the scene 2 switch as one and uses, and its input U and V are respectively that it exports U from the ready START and the busy CARD signal of punch of electronics card-punching apparatus from processor
0And V
0Meet the D of DBUS through three state buffer LS244
4And D
5, represented to be ready to START
0With perforation free CARD is arranged
0Input signal.Output U
1And V
1Export the primary processor of electronics card-punching apparatus to, so that keep the function of electronics card-punching apparatus primary processor control, it has represented ready START
1With the busy CARD of punch
1Signal.The conversion and control end C of electronic analog swtich 14551 can be the input/output end port signal P that is sent by one-chip computer
10Meet the conversion and control end C of electronic analog swtich.
The keyboard input interface is by plurality of keys one end ground connection, and the other end connects respectively and draws resistance to meet DBUS behind three state buffer LS244 to form, therefore when key is pressed to the LS244 input low level, input high level when key lifts.
State shows that output interface is made of the some LEDs of LS273 output termination, and it can indicate " operation of electronics card-punching apparatus ", " controller state of a control ", " program operation ", " program out of service ", " data file input " and states such as " puncher are busy " respectively.
The data file input interface is that the plan of weave data file that computer generates through CAD is inputed to interface in the utility model internal RAM, it can be the serial input interface that serial transmitting terminal TXD, the receiving terminal RXD of one-chip computer connects level translator respectively and constituted, as RS-232 type serial input interface, its level translator can select for use 1488(to send respectively) and the 1489(reception) etc. chip, also can be the serial communication interface that constitutes by serial communication control and level translator able to programme, as Z80-SIO or Intel8250.In addition, the data file input interface can also be the Floppy Disk Controller interface, so that be connected with floppy disk.
Data message input conversion program flow process shown in Figure 3, it is to enter to wait for the data input after utility model control in judgement, deposit in the RAM when data just are converted into parallel data after serial line interface enters CPU, behind the Data Transfer Done, call the perforation subprogram.As shown in Figure 4, one striped version data counts initial value at first is set, as 1344 or 896, fetch data and convert serial code to from buffering area afterwards, after the electronics card-punching apparatus is ready to, send the data of a striped version from processor to card-punching apparatus, and the perforation order of after card-punching apparatus is ready to, sending PUNCH, the action that pierces a striped version of finishing from processor control electromagnet of card-punching apparatus so repeatedly, pierces up to the line version and to finish.
Claims (6)
1, a kind of electronics card-punching apparatus controller of jacquard warp-knitted figured cloth line version making is characterized in that it comprises:
Central processor CPU, its multidigit BDB Bi-directional Data Bus DBUS links to each other with the long numeric data line of stored program read only memory ROM with the random access memory ram of storage data, and its multidigit address bus ABUS links to each other with the multidigit address wire of input, ROM and the RAM of decoding circuit; The output of decoding circuit links to each other with the buffer of ROM, RAM and interface circuit and the sheet choosing end or the control end of latch respectively;
Interface circuit shows that by card-punching apparatus interface, keyboard input interface, the state of the I/O of analog switch control data signal and control signal output interface, data file input interface are constituted;
The oscillating circuit that it also comprises the power circuit that D.C. regulated power supply can be provided and high frequency clock signal can be provided.
2, electronics card-punching apparatus controller according to claim 1 is characterized in that the card-punching apparatus interface is made of multichannel alternative electronic analog swtich, and four data lines of data bus dbus are as D
0, D
1, D
2And D
3, through meeting the W of electronic analog swtich behind the data latches respectively
0, X
0, Y
0And Z
0Input, its U
0And V
0Input can connect two data lines of DBUS respectively through three state buffer, as D
4And D
5, its U, V, W
1, X
1, Y
1And Z
1Input is the input signal from the electronics card-punching apparatus, U
1, V
1, W, X, Y and Z output be the signal to the output of electronics card-punching apparatus, its conversion and control end C links to each other with the switching signal line of CPU control.
3, electronics card-punching apparatus controller according to claim 2, the conversion and control end C that it is characterized in that the electronic analog swtich controlled by the switching signal line can be by the cpu address line through the decoder gating and through latch or data wire road output signal line behind latch controlled, controlled by the control signal end of CPU itself, controlled by the output of two self-lock switch behind logic circuit.
4, electronics card-punching apparatus controller according to claim 1, it is characterized in that the serial input interface that serial transmitting terminal TXD, receiving terminal RXD that its data file input interface can be CPU connect level translator respectively and constituted, as RS-232 type standard serial input interface, also can be the serial communication interface that constitutes by serial communication control and level translator able to programme, as Z80-SIO or Intel8250.
5, electronics card-punching apparatus controller according to claim 1 is characterized in that its data file input interface can also be the Floppy Disk Controller interface, so that be connected with floppy disk.
6, electronics card-punching apparatus controller according to claim 1, it is characterized in that CPU only has chip MC6800, the Intel8000 of central processing function and a cpu chip of Z80 series, also can be CPU with RAM or (with) ROM(or EPROM or PROM) the one-chip computer chip that becomes one, as the one-chip computer of MCS48,51,96 series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 91221867 CN2103572U (en) | 1991-10-15 | 1991-10-15 | Electronic controller for card-punching apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 91221867 CN2103572U (en) | 1991-10-15 | 1991-10-15 | Electronic controller for card-punching apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2103572U true CN2103572U (en) | 1992-05-06 |
Family
ID=4928815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 91221867 Granted CN2103572U (en) | 1991-10-15 | 1991-10-15 | Electronic controller for card-punching apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2103572U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1087042C (en) * | 1999-11-23 | 2002-07-03 | 李加林 | Method for weaving colour brocade |
| CN1091180C (en) * | 2000-08-29 | 2002-09-18 | 李加林 | Method for weaving colour brocade |
-
1991
- 1991-10-15 CN CN 91221867 patent/CN2103572U/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1087042C (en) * | 1999-11-23 | 2002-07-03 | 李加林 | Method for weaving colour brocade |
| CN1091180C (en) * | 2000-08-29 | 2002-09-18 | 李加林 | Method for weaving colour brocade |
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|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |