CN210294833U - Improved DSP external protection circuit - Google Patents
Improved DSP external protection circuit Download PDFInfo
- Publication number
- CN210294833U CN210294833U CN201920988445.3U CN201920988445U CN210294833U CN 210294833 U CN210294833 U CN 210294833U CN 201920988445 U CN201920988445 U CN 201920988445U CN 210294833 U CN210294833 U CN 210294833U
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- dsp
- dog
- gate
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Abstract
The utility model discloses provide a modified DSP outside protection circuit to DSP control chip, including JTAG debug circuit, 4, the dog circuit of opening, 2, reset circuit, 7, logic circuit, 3. And 6, sending a feeding dog pulse signal to a door opening dog path 2 when each task period is finished. And (3) a gate-opening dog circuit 2, a reset circuit 7 and a JTAG debugging circuit 4. transmit respective signals to a logic circuit, and 3. process the signals and then reset the signals to a DSP reset pin 1. The utility model discloses following beneficial effect has: the DSP chip can be subjected to power-on reset and key reset, a gate dog circuit is not required to be disconnected, debugging and downloading of programs can be realized by connecting the JTAG simulator, and the gate dog circuit can be used for monitoring the running programs of the DSP when the DSP works.
Description
Technical Field
The utility model relates to a modified DSP outside protection circuit belongs to embedded hardware field.
Background
The DSP produced by TI corporation is mainly applied to the field of automatic control. The embedded system based on DSP has wide application in the fields of power electronic control, servo motor control, automatic driving, robot control and the like.
The DSP core in the DSP embedded system is powered by 1.8V or 1.3V low voltage, is easy to be subjected to electromagnetic interference, and allows a DSP program to enter illegal interruption, and the internal door-opening dog of the DSP chip is adopted to reset and restart the DSP, so that the external hardware door-opening dog is usually adopted to ensure the reliable operation of the embedded system and avoid the operation fault of the DSP program. However, when the external hardware is adopted to open the door dog, the JTAG simulator is used for debugging and downloading the program, the connection between the door dog opening circuit and the DSP reset pin is required to be disconnected, the DSP can be normally debugged and downloaded through the JTAG simulator, otherwise, the door dog opening circuit always sends a reset signal to the DSP, so that the DSP is always in a reset and restart state, and the program cannot be normally debugged and downloaded. When the debugging and downloading program are finished, the watchdog circuit is connected to the DSP reset pin again, and the running state of the DSP can be monitored. The method brings inconvenience to debugging and downloading programs, and a hardware circuit needs to be changed in the debugging process, so that the system development efficiency is reduced, and the workload of engineering personnel is increased.
SUMMERY OF THE UTILITY MODEL
To the not enough that prior art exists, the utility model aims at providing an improved DSP outside protection circuit to solve the problem that exists in the above-mentioned background. The utility model discloses convenient to use, the operation of being convenient for, stability is good, and anti-interference is strong, and the reliability is high.
In order to achieve the above purpose, the present invention is implemented by the following technical solutions: an improved DSP external protection circuit comprises a JTAG debugging circuit, a gate dog circuit, a reset circuit and a logic circuit.
And the JTAG debugging circuit 4 consists of 2 multiplied by 7 double rows of contact pins and a resistor and is used for being connected with a JTAG simulator, and a TRST signal pin of the JTAG debugging circuit is connected with a logic circuit and is used for enabling and inhibiting a reset signal of a door-opening dog circuit.
And the gate dog circuit 2 consists of a gate dog chip and a capacitor, and when each task cycle is finished, the DSP generates a dog feeding signal through a common IO port, and the gate dog circuit is provided with the gate dog signal to monitor the running state of the DSP in real time.
And the reset circuit 7 consists of a micro self-reset key and a resistance capacitor, and the reset key can forcibly reset and restart the DSP under any condition. When the DSP is powered on, the voltage of the capacitor cannot change suddenly, so that the DSP can be powered on and reset. The reset circuit transmits a reset signal to the logic circuit.
And the logic circuit 3 consists of an AND gate and an OR gate, and the logic circuit plays a role of a bridge between the JTAG debugging circuit, the gate opening dog circuit, the reset circuit and the DSP.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic block diagram of an improved external protection circuit for a DSP according to the present invention;
fig. 2 is a schematic circuit diagram of an improved external protection circuit for a DSP according to the present invention.
Detailed Description
In order to make the technical means, creation features, achievement purposes and functions of the present invention easy to understand, the present invention is further described below with reference to the following embodiments.
Referring to fig. 1 and fig. 2, the present invention provides a technical solution: an improved DSP external protection circuit comprises a JTAG debugging circuit 4, a gate dog circuit 2, a reset circuit 7 and a logic circuit 3.
The PCB circuit board is fabricated according to the circuit schematic of fig. 2. JTAG debug circuit, 4, by 2 x 7 double rows of contact pins, 8, and resistance R1, R2, R3, R4 make up, is used for connecting with JTAG simulator, the TRST signal pin of JTAG debug circuit is connected with logic circuit, 3, OR gate, 9. input end, are used for enabling and inhibiting the reset signal of the circuit of the dog of opening the door. All pins of the JTAG debugging circuit are connected with corresponding pins of the DSP through the PCB circuit. And 2, the gate dog circuit consists of a gate dog chip, 12 and a capacitor C1, and the DSP sends a dog feeding signal to a WDO pin of the gate dog chip through a common IO port when each task cycle is finished. And the reset circuit 2 consists of a micro self-reset button 14 and a resistor R7, a capacitor C5 and is connected to the input end of the logic circuit 3 and the AND gate 10. And the logic circuit 3 consists of an AND gate, a 10 OR gate and a 9, and sends the processed signals to a reset pin of the DSP.
The utility model discloses when in-service use, the engineer only need insert the JTAG emulator and can carry out normal software debugging to DSP, and the dog circuit of opening the door this moment is in invalid state, and reset circuit can realize power-on reset and button reset to DSP, and software debugging finishes with program solidification to DSP's Flash, and the system outage pulls out the JTAG emulator, and the system is power-on operation again, but this protection circuit real time monitoring DSP running state.
The foregoing illustrates and describes the principles, principal features and advantages of the invention. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (4)
1. An improved DSP external protection circuit comprises a JTAG debugging circuit, a gate dog circuit, a reset circuit and a logic circuit, and is characterized in that: the JTAG debug circuit, 4, the gate dog circuit, 2, the reset circuit, 7. the signal produced passes the logic circuit, 3, the signal comprehensive processing of each part, then send to the reset pin of DSP, while debugging the procedure in JTAG mode, the reset signal of the gate dog circuit is in the invalid state; when the DSP normally operates, the reset signal of the watchdog circuit is in an activated state, and the operation state of the DSP is monitored in real time; when the DSP program is run away, the door-opening dog circuit generates a reset signal to reset and restart the DSP.
2. The improved external protection circuit for a DSP according to claim 1, wherein: the logic circuit consists of an AND gate and an OR gate.
3. The improved external protection circuit for a DSP according to claim 1, wherein: the logic circuit comprehensively processes the TRST signal of the JTAG debugging circuit, the reset signal of the gate-opening dog circuit and the reset signal of the reset circuit and then transmits the processed signals to the reset pin of the DSP.
4. The improved external protection circuit for a DSP according to claim 1, wherein: the reset circuit consists of a micro self-reset key and a capacitance resistor, and can realize power-on reset and key reset restart of the DSP.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201920988445.3U CN210294833U (en) | 2019-06-28 | 2019-06-28 | Improved DSP external protection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201920988445.3U CN210294833U (en) | 2019-06-28 | 2019-06-28 | Improved DSP external protection circuit |
Publications (1)
Publication Number | Publication Date |
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CN210294833U true CN210294833U (en) | 2020-04-10 |
Family
ID=70099278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201920988445.3U Expired - Fee Related CN210294833U (en) | 2019-06-28 | 2019-06-28 | Improved DSP external protection circuit |
Country Status (1)
Country | Link |
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CN (1) | CN210294833U (en) |
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2019
- 2019-06-28 CN CN201920988445.3U patent/CN210294833U/en not_active Expired - Fee Related
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200410 Termination date: 20200628 |