CN210225586U

CN210225586U - DTMB high-definition digital television all-in-one machine

Info

Publication number: CN210225586U
Application number: CN201920581596.7U
Authority: CN
Inventors: Zhiqiang Wu; 吴志强
Original assignee: Shenzhen Riqin Technology Co Ltd
Current assignee: Shenzhen Riqin Technology Co Ltd
Priority date: 2019-04-26
Filing date: 2019-04-26
Publication date: 2020-03-31
Anticipated expiration: 2029-04-26

Abstract

The utility model discloses a DTMB high definition digital television integrated machine, which comprises a main control module, a digital audio and video decoding module, a display module and a power amplifier output module, wherein the digital audio and video decoding module, the display module and the power amplifier output module are connected with the main control module; the digital audio and video decoding module comprises a decoding circuit, the decoding circuit is connected with the main control module, the digital audio and video decoding module also comprises a tuning circuit and a CA decryption circuit which are connected with the decoding circuit, and the other end of the tuning circuit is connected with an audio and video signal receiving circuit; the display module comprises an LVDS display screen J9, and further comprises a screen backlight input circuit and a driving circuit, wherein the input end of the screen backlight input circuit is connected with the power supply end, the output end of the screen backlight input circuit is connected with the power supply input end of the driving circuit, the control input end of the driving circuit is connected with the main control module, and the output end of the driving circuit is connected with the LVDS display screen J9. The utility model discloses can support and receive multiple television program signal.

Description

DTMB high-definition digital television all-in-one machine

Technical Field

The utility model relates to a digital television technical field specifically relates to a DTMB high definition digital television all-in-one.

Background

The coding of DTMB digital television signals is mainly based on MPEG \ AVS in the early stage, 12 sets of standard definition programs are transmitted at a single frequency point, the image resolution reaches 480i, and the user experience is very poor; later, an operator upgrades the encoder to H.264\ AVS +, the image resolution reaches 576i, 12 sets of programs are transmitted by a single frequency point, the user experience is still poor, and particularly, the image quality is poor on a television with the size of more than 40 inches; in order to obtain better user experience, an operator adopts an H.264\ AVS + coding format to transmit high-definition programs with resolution of more than 720P, but only 2-3 sets of high-definition programs can be transmitted under the limitation of the compression ratio of an encoder. Most of set top boxes purchased by consumers at present and capable of watching local radio and television encrypted programs are CVBS (analog video broadcast and television) signal output, the definition of image quality is not enough, and the advantages of digital televisions cannot be reflected; at present, the television set sold in the market can only be called as a display at best because the product does not support the reception of digital television programs, or the television set with the function of receiving DTMB digital television only watches free programs but cannot watch encrypted programs.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a circuit structure is simple, can support the DTMB high definition digital television all-in-one who receives multiple DTMB digital television program signal.

The utility model discloses a technical scheme that DTMB high definition digital television all-in-one adopted is:

the utility model provides a DTMB high definition digital television all-in-one, includes host system, host system includes main control chip U8, main control chip U8 supports H.265 to decode, H.264 decodes, AVS + decodes, AVS decodes and MPEG decodes, still include with digital audio and video decoding module, display module and power amplifier output module that host system is connected.

The digital audio and video decoding module comprises a decoding circuit, the decoding circuit is connected with the main control module, the digital audio and video decoding module further comprises a tuning circuit and a CA (conditional access) decryption circuit, the tuning circuit is connected with the decoding circuit, and the other end of the tuning circuit is connected with an audio and video signal receiving circuit.

The display module comprises an LVDS display screen J9, and further comprises a screen backlight input circuit and a driving circuit, wherein the input end of the screen backlight input circuit is connected with a power supply end, the output end of the screen backlight input circuit is connected with the power supply input end of the driving circuit, the control input end of the driving circuit is connected with the main control module, and the output end of the driving circuit is connected with the LVDS display screen J9.

Preferably, the screen backlight input circuit includes a first backlight circuit, a second backlight circuit and an interface J10, an input terminal of the first backlight circuit is connected to the 3.3V power supply terminal, the 5V power supply terminal and the main control module, an output terminal of the first backlight circuit is connected to the interface J10, an input terminal of the second backlight circuit is connected to the 5V power supply terminal and the main control module, an output terminal of the second backlight circuit is connected to the interface J10, and another terminal of the interface J10 is connected to a power supply input terminal of the driving circuit.

As a preferred scheme, the power amplifier output module includes a power amplifier chip UA1, an audio signal connection port of the power amplifier chip UA1 is connected to the main control module, and an audio signal output port of the power amplifier chip UA1 is connected to a speaker CN 5.

Preferably, the decoding circuit comprises a decoding chip U3, the decoding chip U3 is connected to the main control module, and the decoding chip U3 is connected to the tuning circuit and the CA decryption circuit.

Preferably, the CA decryption circuit includes a decryption chip U15, an interface CON1, and a decryption power supply circuit, an input end of the decryption power supply circuit is connected to the power supply terminal and the decoding chip U3, an output end of the decryption power supply circuit is connected to the interface CON1, and the decryption chip U15 is connected between the decoding chip U3 and the interface CON 1.

Preferably, the tuning circuit includes a tuning chip U4, the tuning chip U4 is electrically connected to the decoding chip U3, and the tuning chip U4 is further connected to the audio/video signal receiving circuit.

Preferably, the audio/video signal receiving circuit includes an external antenna ANT2, and the external antenna ANT2 is connected to an audio/video input terminal of the tuning chip U4.

Preferably, the digital audio/video decoding module further comprises a USB interface circuit and a first storage interface circuit, and both the USB interface circuit and the first storage interface circuit are connected to the decoding chip U3.

As a preferred scheme, the power supply module is further included, the power supply module is connected with the main control module, the input end of the power supply module is connected with a 12V power supply end, and the power supply module comprises a 5V input circuit, a 3.3V input circuit, a 1.8V input circuit and a 1.2V input circuit.

As a preferred scheme, the system also comprises a data debugging interface module, a remote control interface module, a second storage module, a key sampling voltage module, a high-definition input interface module, an external video/audio input module and a key function control module which are connected with the main control module.

The utility model discloses a DTMB high definition digital television all-in-one, audio and video signal receiving circuit are used for receiving high definition digital television signal, and audio and video signal receiving circuit transmits received high definition digital television signal for decoding circuit after tuned circuit demodulation, because decoding circuit is connected with CA declassification circuit, CA declassification circuit can decipher the broadcast television encrypted television program signal, consequently the utility model discloses an audio and video signal receiving circuit can receive local encryption high definition digital television signal. The audio and video signals decoded by the decoding circuit are transmitted to the main control module, the main control module outputs corresponding analog video signals to the LVDS display J9 and controls the LVDS display J9 to display corresponding pictures, and the main control module outputs corresponding analog audio signals to the power amplifier output module and controls the power amplifier output module to play corresponding sounds. The utility model discloses STB and TV set integration increase host system on digital audio and video decoding module's basis to and the LVDS display screen J9 and the power amplifier output module who receives host system control, thereby realize can receiving audio and video signal and can directly carry out the broadcast of audio and video again, and can receive and encrypt high definition digital television signal, support more television programs, have higher price/performance ratio. Additionally, the utility model discloses main control chip U8 supports H.265 to decode, H.264 decodes, AVS + decodes, AVS decodes and MPEG decodes, based on the high compression ratio of H.265 technique, can support the high definition program of 10 sets of 720P image quality or the standard definition program of 24 sets of 576i image qualities under the single frequency point, can solve the problem that program transmission quantity is not enough under the single frequency point mode.

Drawings

Fig. 1 is the module structure schematic diagram of the utility model discloses a DTMB high definition digital television all-in-one machine.

Fig. 2 is the utility model discloses a digital audio frequency and video decoding module's of DTMB high definition digital television all-in-one structural schematic diagram.

Fig. 3 is a schematic structural diagram of an LVDS display screen J9 of a display module of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 4 is a schematic structural diagram of a first backlight circuit of a display module of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 5 is a schematic structural diagram of a second backlight circuit of a display module of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 6 is a schematic structural diagram of a driving circuit of a display module of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 7 is a schematic structural diagram of an interface J10 of a display module of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 8 is the utility model discloses a power amplifier output module's of DTMB high definition digital television all-in-one structural schematic diagram.

Fig. 9 is the utility model discloses a 1.8V step-down circuit's of DTMB high definition digital television all-in-one high definition video input interface module structural schematic diagram.

Fig. 10 is a schematic structural diagram of a power module of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 11 is a schematic structural diagram of a power module of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 12 is a schematic structural diagram of a power module of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 13 is a schematic structural diagram of a CA decryption circuit of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 14 is a schematic structural diagram of a CA decryption circuit of the DTMB high-definition digital television all-in-one machine of the present invention.

Fig. 15 is a schematic structural diagram of a CA decryption circuit of the DTMB high-definition digital television all-in-one machine of the present invention.

Detailed Description

The invention will be further elucidated and described with reference to the following embodiments and drawings in which:

referring to fig. 1 and 2, the DTMB high-definition digital television all-in-one machine comprises a main control module, and further comprises a digital audio and video decoding module, a display module and a power amplifier output module which are connected with the main control module. The main control module comprises a main control chip U8, the model of the main control chip U8 is SPV7050R, and H.265 decoding, H.264 decoding, AVS + decoding, AVS decoding and MPEG decoding are supported.

The decoding circuit comprises a decoding chip U3, the decoding chip U3 is connected with a main control chip U8 of the main control module, the type of the decoding chip U3 is AVL8332, and the decoding chip U3 is connected with the tuning circuit and the CA decryption circuit.

Referring to fig. 3, 4, 5, 6, and 7, the display module includes an LVDS display screen J9, and further includes a screen backlight input circuit and a driving circuit, an input end of the screen backlight input circuit is connected to a power supply end, an output end of the screen backlight input circuit is connected to a power supply input end of the driving circuit, a control input end of the driving circuit is connected to the main control module, and an output end of the driving circuit is connected to the LVDS display screen J9.

The screen backlight input circuit comprises a first backlight circuit, a second backlight circuit and an interface J10, wherein the input end of the first backlight circuit is connected with a 3.3V power supply end, a 5V power supply end and a main control module, the output end of the first backlight circuit is connected with the interface J10, the input end of the second backlight circuit is connected with the 5V power supply end and the main control module, the output end of the second backlight circuit is connected with the interface J10, and the other end of the interface J10 is connected with the power supply input end of the driving circuit.

The first backlight circuit comprises a triode Q19, a resistor R164 is connected in series with the base of the triode Q19, the other end of the resistor R164 is connected with a pin 60 of a main control chip U8, the other end of the resistor R164 is further connected with a resistor R160, the other end of the resistor R160 is connected with a 3.3V power supply end, the emitter of the triode Q19 is grounded, the collector of the triode Q19 is connected with a resistor R162, a resistor R161 and a resistor R163, the other end of the resistor R162 is connected with the resistor R160 and the resistor R164, the other end of the resistor R161 is connected with a 5V power supply end, the other end of the resistor R163 is connected with a pin 3 of an interface J10, a capacitor C152 and a resistor R165 are further connected in parallel between the resistor R163 and the pin 3 of the interface J.

The second backlight circuit comprises a triode Q20, a resistor R172 is connected in series with the base of the triode Q20, the other end of the resistor R172 is connected with a pin 59 of a main control chip U8, the emitter of the triode Q20 is grounded, the collector of the triode Q20 is connected with a resistor R170 and a resistor R171, the other end of the resistor R170 is connected with a 5V power supply end, the other end of the resistor R171 is connected with a pin 4 of an interface J10, and a capacitor C153 is connected in parallel between the resistor R171 and an interface J10.

The driving circuit comprises an interface JP3, an interface JP3 is connected with an interface J10, a field effect tube QL1 is connected with a pin 1, a pin 3 and a pin 5 of the interface JP3, the field effect tube QL1 is an enhanced N-channel field effect tube, a triode Q22 is connected with a gate of the field effect tube QL1, a resistor R173 is connected between a source and a gate of the field effect tube QL1, a resistor R176 is connected between a gate of the field effect tube QL1 and a collector of the triode Q22, a drain of the field effect tube QL1 is connected with an LVDS display screen J9, a capacitor C155 and a capacitor E21 which are connected in parallel are also connected between a drain of the field effect tube QL1 and an emitter of the triode Q22, an emitter of the triode Q22 is also grounded, a resistor R175 is connected in series with a base of the triode Q22, the other end of the resistor R175 is connected with a pin 94 of a main control chip U8, the other end of the resistor R175 is also connected with a, the other terminal of the capacitor C154 is grounded.

The first backlight circuit and the second backlight circuit of the screen backlight input circuit are used for boosting the voltage provided for the LVDS display screen J9 and providing stable voltage, the driving circuit is controlled by the main control chip U8 and controls the on-off of a loop from the screen backlight input circuit to the LVDS display screen J9, and therefore the LVDS display screen J9 is turned on and off.

Referring to fig. 8, the power amplifier output module includes a power amplifier chip UA1, the power amplifier chip UA1 is RT9108NBGCP or TPA3110D2, an audio signal connection port of the power amplifier chip UA1 is connected to the main control module, and an audio signal output port of the power amplifier chip UA1 is connected to the speaker CN 5. The power amplifier output module further comprises a mute circuit connected with a power amplifier chip UA1, the mute circuit comprises a triode QA1 and a triode QA2, a collector of the triode QA1 is connected with the power amplifier chip UA1, an emitter of the triode QA1 is grounded, a base of the triode QA1 is connected with a resistor RA1, the other end of the resistor RA1 is connected with a collector of the triode QA1, a base of the triode QA1 is connected with the resistor RA1, the other end of the resistor RA1 is connected with a capacitor RA1, a diode DA1 and a capacitor CA 1, the other end of the capacitor CA 1 is grounded, a cathode of the diode DA1 and the other end of the resistor RA1 are connected with the power amplifier chip UA1, a cathode of the diode DA1 and the other end of the resistor RA1 are further connected with a diode DA1, a cathode of the diode DA1 and an emitter of the triode QA1 are connected with the resistor RA1 and the other end of the. The power amplifier chip UA1 of the power amplifier output module is used for amplifying the analog audio signal transmitted by the main control chip U8, and the amplified analog audio signal is played through the loudspeaker CN 5.

Referring to fig. 13, 14 and 15, the CA decryption circuit includes a decryption chip U15, an interface CON1 and a decryption power supply circuit, an input terminal of the decryption power supply circuit is connected to the power supply terminal and the decoding chip U3, an output terminal of the decryption power supply circuit is connected to the interface CON1, and the decryption chip U15 is connected between the decoding chip U3 and the interface CON 1. The decryption chip U15 is used for obtaining the encrypted information, the decryption chip U15 feeds the encrypted information back to the main control chip U8, and the main control chip U8 can receive the encrypted television program signals through the digital audio and video decoding module according to the encrypted information.

The tuning circuit comprises a tuning chip U4, the tuning chip U4 is electrically connected with the decoding chip U3, and the tuning chip U4 is further connected with the audio and video signal receiving circuit. The tuning chip U4 is of type Si2151 or Si 2141.

The audio and video signal receiving circuit comprises an external antenna ANT2, and the external antenna ANT2 is connected with an audio and video input end of the tuning chip U4.

The digital audio and video decoding module also comprises a USB interface circuit and a first storage interface circuit, wherein the USB interface circuit and the first storage interface circuit are both connected with the decoding chip U3.

Referring to fig. 10, 11 and 12, the electronic device further includes a power module, the power module is connected to a main control chip U8 of the main control module, an input end of the power module is connected to a 12V power supply end, and the power module includes a 5V input circuit, a 3.3V input circuit, a 1.8V input circuit and a 1.2V input circuit. The power module provides various voltages to ensure the normal work of each module and each chip.

Referring to fig. 1 and 9, the device further includes a data debugging interface module, a remote control interface module, a second storage module, a key voltage sampling module, a high definition input interface module, an external video/audio input module, and a key function control module, which are connected to the main control module. The data debugging interface module is used for adjusting data, the remote control interface module is used for remote control, the second storage module is used for storing audio/video information or parameters, the operation and storage are improved, and the high-definition input interface module and the external video/audio input module are used for transmitting external audio/video signal information. The key function control module is convenient for a user to control and operate.

The utility model discloses a DTMB high definition digital television all-in-one, audio and video signal receiving circuit are used for receiving high definition digital television signal, and audio and video signal receiving circuit transmits received high definition digital television signal for decoding circuit after tuned circuit demodulation, because decoding circuit is connected with CA decryption circuit, consequently the utility model discloses an audio and video signal receiving circuit can receive local encryption high definition digital television signal. The audio and video signals decoded by the decoding circuit are transmitted to the main control module, the main control module outputs corresponding analog video signals to the LVDS display J9 and controls the LVDS display J9 to display corresponding pictures, and the main control module outputs corresponding analog audio signals to the power amplifier output module and controls the power amplifier output module to play corresponding sounds. The utility model discloses STB and TV set integration increase host system on digital audio and video decoding module's basis to and the LVDS display screen J9 and the power amplifier output module who receives host system control, thereby realize can receiving audio and video signal and can directly carry out the broadcast of audio and video again, and can receive encryption high definition digital television signal, the broadcast television program is more, has higher price/performance ratio. The utility model discloses support H.265 simultaneously and decode, H.264 decode, AVS + decode, AVS decode, MPEG decodes, support multiple audio formats such as MP3, AC3, WMA, AAC, DTS. The system supports the broadcasting and television digital television management system and can receive and watch local broadcasting and television encrypted television programs. The utility model discloses based on the high compression ratio of H.265 technique, single frequency point down can support the high definition program of 10 sets of 720P image quality or the standard definition program of 24 sets of 576i image qualities, can solve the problem that program transmission quantity is not enough under the single frequency point mode.

It should be finally noted that the above embodiments are only intended to illustrate the technical solutions of the present invention, and not to limit the scope of the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present invention can be modified or replaced with equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. The utility model provides a DTMB high definition digital television all-in-one which characterized in that: the digital audio and video decoding system comprises a main control module, wherein the main control module comprises a main control chip U8, the main control chip U8 supports H.265 decoding, H.264 decoding, AVS + decoding, AVS decoding and MPEG decoding, and the digital audio and video decoding module, a display module and a power amplifier output module are connected with the main control module;

the digital audio and video decoding module comprises a decoding circuit, the decoding circuit is connected with the main control module, the digital audio and video decoding module also comprises a tuning circuit and a CA decryption circuit which are connected with the decoding circuit, and the other end of the tuning circuit is connected with an audio and video signal receiving circuit;

2. The DTMB high-definition digital television all-in-one machine of claim 1, wherein: the screen backlight input circuit comprises a first backlight circuit, a second backlight circuit and an interface J10, wherein the input end of the first backlight circuit is connected with a 3.3V power supply end, a 5V power supply end and a main control module, the output end of the first backlight circuit is connected with the interface J10, the input end of the second backlight circuit is connected with the 5V power supply end and the main control module, the output end of the second backlight circuit is connected with the interface J10, and the other end of the interface J10 is connected with the power supply input end of the driving circuit.

3. The DTMB high-definition digital television all-in-one machine of claim 1, wherein: the power amplifier output module comprises a power amplifier chip UA1, an audio signal connection port of the power amplifier chip UA1 is connected with the main control module, and an audio signal output port of the power amplifier chip UA1 is connected with a loudspeaker CN 5.

4. The DTMB high-definition digital television all-in-one machine of claim 1, wherein: the decoding circuit comprises a decoding chip U3, the decoding chip U3 is connected with the main control module, and the decoding chip U3 is connected with the tuning circuit and the CA decryption circuit.

5. The DTMB high-definition digital television all-in-one machine of claim 4, wherein: the CA decryption circuit comprises a decryption chip U15, an interface CON1 and a decryption power supply circuit, wherein the input end of the decryption power supply circuit is connected with a power supply end and the decoding chip U3, the output end of the decryption power supply circuit is connected with the interface CON1, and the decryption chip U15 is connected between the decoding chip U3 and the interface CON 1.

6. The DTMB high-definition digital television all-in-one machine of claim 4, wherein: the tuning circuit comprises a tuning chip U4, the tuning chip U4 is electrically connected with the decoding chip U3, and the tuning chip U4 is further connected with the audio and video signal receiving circuit.

7. The DTMB high-definition digital television all-in-one machine of claim 6, wherein: the audio and video signal receiving circuit comprises an external antenna ANT2, and the external antenna ANT2 is connected with an audio and video input end of the tuning chip U4.

8. The DTMB high-definition digital television all-in-one machine of claim 4, wherein: the digital audio and video decoding module also comprises a USB interface circuit and a first storage interface circuit, wherein the USB interface circuit and the first storage interface circuit are both connected with the decoding chip U3.

9. The DTMB high-definition digital television all-in-one machine of claim 1, wherein: still including power module, power module connects host system, power module's input is connected 12V supply terminal, power module includes 5V input circuit, 3.3V input circuit, 1.8V input circuit and 1.2V input circuit.

10. The DTMB high-definition digital television all-in-one machine of claim 1, wherein: the remote control device also comprises a data debugging interface module, a remote control interface module, a second storage module, a key sampling voltage module, a high-definition input interface module, an external video/audio input module and a key function control module which are connected with the main control module.