CN210223521U - Double-loop display output circuit of intelligent instrument - Google Patents
Double-loop display output circuit of intelligent instrument Download PDFInfo
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- CN210223521U CN210223521U CN201921736967.0U CN201921736967U CN210223521U CN 210223521 U CN210223521 U CN 210223521U CN 201921736967 U CN201921736967 U CN 201921736967U CN 210223521 U CN210223521 U CN 210223521U
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Abstract
A double-loop display output circuit of an intelligent instrument comprises a main control CPU, a first display control chip and a second display control chip; the master control CPU comprises a first output pin, a second output pin, a third output pin, a fourth output pin, a fifth output pin and a sixth output pin; the first display control chip comprises a first chip selection port, a first clock port and a first input port; the second display control chip comprises a second chip selection port, a second clock port and a second input port; the first output pin is connected with the first chip selection port through a first chip selection signal line, the second output pin is connected with the first clock port through a first clock line, and the third output pin is connected with the first input port through a first output bus; the fourth output pin is connected with the second chip selection port through a second chip selection signal line, the fifth output pin is connected with the second clock port through a second clock line, and the sixth output pin is connected with the second input port through a second output bus.
Description
Technical Field
The utility model relates to an electron device field especially relates to a two return circuits of intelligent instrument show output circuit.
Background
The display interface refreshing work of the existing intelligent instrument generally adopts a mode of adding two chip selection signal lines to a group of communication buses to control a display chip, namely, when display information needs to be refreshed, a first display control chip is selected first, the content needing to be displayed is sent to the first display control chip through the communication buses, then the first display control chip is released, then a second display control chip is selected, the operation same as that of the first display control chip is executed, and then the second display control chip is released. When the content of the display interface is refreshed, the refreshing of the display content of the display control chip must be completed piece by piece, and the refreshing of the display interface can be completed within twice of the time, so that the working efficiency of the system is greatly reduced.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to the defect in the background art, provide a two return circuits of intelligent instrument and show output circuit, realize exporting simultaneously and refresh control the parallel of demonstration interface, improve the efficiency of showing output, reduce master control CPU's invalid expense.
To achieve the purpose, the utility model adopts the following technical proposal:
a double-loop display output circuit of an intelligent instrument comprises a main control CPU, a first display control chip and a second display control chip;
the master control CPU comprises a first output pin, a second output pin, a third output pin, a fourth output pin, a fifth output pin and a sixth output pin;
the first display control chip comprises a first chip selection port, a first clock port and a first input port;
the second display control chip comprises a second chip selection port, a second clock port and a second input port;
the first output pin is connected with the first chip selection port through a first chip selection signal line, the second output pin is connected with the first clock port through a first clock line, and the third output pin is connected with the first input port through a first output bus;
the fourth output pin is connected with the second chip selection port through a second chip selection signal line, the fifth output pin is connected with the second clock port through a second clock line, and the sixth output pin is connected with the second input port through a second output bus.
Preferably, the LED nixie tube comprises an LED nixie tube, wherein the LED nixie tube comprises a first LED nixie tube, a second LED nixie tube and a third LED nixie tube; the LED nixie tubes are provided with a plurality of pins;
the first display control chip and the second display control chip are both provided with end ports with the same name as the pins on the LED nixie tube;
and the ports of the same-name end on the first display control chip are respectively connected with the pins of the first LED nixie tube and the second LED nixie tube in a one-to-one correspondence manner to form a loop.
Preferably, the ports of the same-name ends of the second display control chip are respectively connected with the pins of the third LED nixie tubes in a one-to-one correspondence manner to form a loop.
Preferably, the LED digital tube comprises a plurality of groups of LED lamps, and the LED lamps are respectively connected with the pins of the third LED digital tube in a one-to-one correspondence manner;
and the LED lamps are respectively connected with the ports of the same-name ends of the second display control chip in a one-to-one correspondence manner.
Preferably, the main control CPU further includes a first electrolytic capacitor, a first capacitor, an AV port, and an AGND analog ground port;
one end of the first electrolytic capacitor is connected with the AV port, and the other end of the first electrolytic capacitor is connected with the AGND analog ground port; one end of the first capacitor is connected with the AV port, and the other end of the first capacitor is connected with the AGND analog ground port.
Preferably, the main control CPU further includes a second electrolytic capacitor, a second capacitor, a ground port, and a reference voltage port; one end of the second electrolytic capacitor is connected with the reference voltage port, and the other end of the second electrolytic capacitor is connected with the grounding port;
one end of the second capacitor is connected with the reference voltage port, and the other end of the second capacitor is connected with the grounding port.
Has the advantages that:
1. by adopting an independent double-loop control communication bus design mode on hardware, parallel and simultaneous output refreshing control of the display interfaces is realized, the second group of display contents can be refreshed simultaneously while the first group of display contents are refreshed, the display output efficiency is improved, and the invalid overhead of the main control CPU is reduced.
Drawings
Fig. 1 is a circuit diagram of a main control CPU of the present invention;
fig. 2 is a circuit connection diagram of the first display control chip and the LED nixie tube according to the present invention;
fig. 3 is a circuit connection diagram of the second display control chip, the LED nixie tube and the LED lamp of the present invention;
fig. 4 is a circuit connection diagram of the main control CPU, the first display control chip and the second display control chip.
Wherein: the LED digital display system comprises a main control CPU-1, a first display control chip-2, a second display control chip-3, a first LED digital tube-4, a second LED digital tube-5, a third LED digital tube-6 and an LED lamp-7.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.
The orientation of the embodiment is based on the attached drawings of the specification.
In the prior art, a mode of adding two chip selection signal lines to a group of communication buses is adopted to control a display chip, namely, when display information needs to be refreshed each time, a first display control chip is selected, the content needing to be displayed is sent to the first display control chip through the communication buses, then the first display control chip is released, then a second display control chip is selected, the content needing to be displayed is sent to the second display control chip through the communication buses, and then the second display control chip is released, so that the display content is updated.
As described above, in the prior art, when the content of the display interface is refreshed, the content of the display control chip must be updated piece by piece, that is, it takes twice as long to complete the refreshing of the display interface, which reduces the system operating efficiency.
The utility model discloses a double-circuit display output circuit of an intelligent instrument, as shown in fig. 1-4, comprising a main control CPU1, a first display control chip 2 and a second display control chip 3;
the master control CPU1 includes a first output pin, a second output pin, a third output pin, a fourth output pin, a fifth output pin, and a sixth output pin;
the first display control chip 2 comprises a first chip selection port, a first clock port and a first input port;
the second display control chip 3 comprises a second chip selection port, a second clock port and a second input port;
the first output pin is connected with the first chip selection port through a first chip selection signal line, the second output pin is connected with the first clock port through a first clock line, and the third output pin is connected with the first input port through a first output bus;
the fourth output pin is connected with the second chip selection port through a second chip selection signal line, the fifth output pin is connected with the second clock port through a second clock line, and the sixth output pin is connected with the second input port through a second output bus.
As shown in fig. 1-3, the first output pin is p2.0, the second output pin is p2.1, the third output pin is p2.2, the fourth output pin is p2.3, the fifth output pin is p2.4, and the sixth output pin is p 2.5;
the first chip selection port corresponds to the icon 6-CS of the first display control chip 2;
the first clock port corresponds to the icon 7-CLK of the first display control chip 2;
the first input port corresponds to the icon 8-DATA of the first display control chip 2;
the second chip selection port corresponds to an icon CS-6 of the second display control chip 3;
the second clock port corresponds to an icon CLK-7 of the second display control chip 3;
the second input port corresponds to the icon DATA-8 of the second display control chip 3;
a first chip selection signal line CS1, a second chip selection signal line CS2, a first clock line CLK1, a second clock line CLK2, a first output bus data1, a second output bus data 2;
as shown in fig. 4, the first output pin p2.0 is connected to the first chip select port 6-CS through a first chip select signal line CS1, the second output pin p2.1 is connected to the first clock port 7-CLK through a first clock line CLK1, and the third output pin p2.2 is connected to the first input port 8-DATA through a first output bus DATA 1;
the fourth output pin p2.3 is connected to the second chip selection port CS-6 through a second chip selection signal line CS2, the fifth output pin p2.4 is connected to the second clock port CLK-7 through a second clock line CLK2, and the sixth output pin p2.5 is connected to the second input port DATA-8 through a second output bus DATA 2.
Through two groups of completely independent chip selection and communication bus connection modes, the main control CPU1 is respectively connected with the two display control chips, so that the main control CPU1 can simultaneously control the two display function chips when the output control of the display content is carried out, and the display output efficiency is improved;
when the first display control chip is controlled to refresh data, the second display control chip can be simultaneously controlled without waiting for the completion of the first chip operation in situ, so that the display content can be synchronously output in parallel, the interaction stability of serial communication is fully utilized, and the display interaction efficiency is improved.
The two display control chips are adopted for display control, so that the power consumption load of the single display control chip is reduced, the abnormal range is reduced when abnormality occurs, and the abnormal working condition can be conveniently checked and analyzed;
preferably, as shown in fig. 3, the LED digital tube comprises a first LED digital tube 4, a second LED digital tube 5 and a third LED digital tube 6; the LED nixie tubes are provided with a plurality of pins;
the first display control chip 2 and the second display control chip 3 are both provided with end ports with the same name as the pins on the LED nixie tube;
the ports of the same name end on the first display control chip 2 are respectively connected with the pins of the first LED nixie tube 4 and the second LED nixie tube 5 in a one-to-one correspondence manner to form a loop.
Preferably, the ports of the same-name ends of the second display control chip 3 are respectively connected with the pins of the third LED nixie tubes 6 in a one-to-one correspondence manner to form a loop.
Preferably, the LED digital tube comprises a plurality of groups of LED lamps 7, and the LED lamps 7 are respectively connected with the pins of the third LED digital tubes 6 in a one-to-one correspondence manner;
the LED lamps 7 are respectively connected with the ports of the same-name ends of the second display control chip 3 in a one-to-one correspondence mode.
Pins of the LED nixie tube comprise A, B, C, D, E, F, G, DP;
the homonymous terminal ports of the first display control chip 2 and the second display control chip 3 comprise an SA terminal, an SB terminal, an SC terminal, an SE terminal, an SF terminal, an SG terminal and a DP terminal;
the pin A of the LED nixie tube is connected with the SA ends of the first display control chip 2 and the second display control chip 3; the pin B is connected with SB ends of the first display control chip 2 and the second display control chip 3; by analogy, the purpose that the first display control chip 2 and the second display control chip 3 control the output LED nixie tube is achieved.
Preferably, as shown in FIG. 1, the master CPU1 further includes a first electrolytic capacitor C1, a first capacitor C2, AV ports 14-AV + and 11-AV +, AGND analog ground ports 10-AGND and 13-AGND;
one end of the first electrolytic capacitor C1 is connected to the AV ports 14-AV + and 11-AV + and the other end is connected to the AGND analog ground ports 10-AGND and 13-AGND; one end of the first capacitor C2 is connected to the AV ports 14-AV + and 11-AV + and the other end is connected to the AGND analog ground ports 10-AGND and 13-AGND.
Preferably, the main control CPU1 further includes a second electrolytic capacitor C4, a second capacitor C3, a ground port GND and a reference voltage port AVEF; one end of the second electrolytic capacitor C4 is connected to the reference voltage port AVEF, and the other end is connected to the ground port GND;
one end of the second capacitor C3 is connected to the reference voltage port AVEF, and the other end is connected to the ground port GND.
The technical principle of the present invention is described above with reference to specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without any inventive effort, which would fall within the scope of the present invention.
Claims (6)
1. The utility model provides a two return circuits of smart meter show output circuit which characterized in that: the display control system comprises a master control CPU, a first display control chip and a second display control chip;
the master control CPU comprises a first output pin, a second output pin, a third output pin, a fourth output pin, a fifth output pin and a sixth output pin;
the first display control chip comprises a first chip selection port, a first clock port and a first input port;
the second display control chip comprises a second chip selection port, a second clock port and a second input port;
the first output pin is connected with the first chip selection port through a first chip selection signal line, the second output pin is connected with the first clock port through a first clock line, and the third output pin is connected with the first input port through a first output bus;
the fourth output pin is connected with the second chip selection port through a second chip selection signal line, the fifth output pin is connected with the second clock port through a second clock line, and the sixth output pin is connected with the second input port through a second output bus.
2. The dual-loop display output circuit of the intelligent instrument according to claim 1, wherein:
the LED nixie tube comprises an LED nixie tube, wherein the LED nixie tube comprises a first LED nixie tube, a second LED nixie tube and a third LED nixie tube; the LED nixie tubes are provided with a plurality of pins;
the first display control chip and the second display control chip are both provided with end ports with the same name as the pins on the LED nixie tube;
and the ports of the same-name end on the first display control chip are respectively connected with the pins of the first LED nixie tube and the second LED nixie tube in a one-to-one correspondence manner to form a loop.
3. The dual-loop display output circuit of the intelligent instrument according to claim 2, wherein:
and the homonymous end ports of the second display control chip are respectively connected with the pins of the third LED nixie tubes in a one-to-one correspondence manner to form a loop.
4. The dual-loop display output circuit of the intelligent instrument according to claim 3, wherein:
the LED digital tubes are connected with the base pins of the third LED digital tubes in a one-to-one correspondence manner;
and the LED lamps are respectively connected with the ports of the same-name ends of the second display control chip in a one-to-one correspondence manner.
5. The dual-loop display output circuit of the intelligent instrument according to claim 1, wherein:
the main control CPU also comprises a first electrolytic capacitor, a first capacitor, an AV port and an AGND analog ground port;
one end of the first electrolytic capacitor is connected with the AV port, and the other end of the first electrolytic capacitor is connected with the AGND analog ground port; one end of the first capacitor is connected with the AV port, and the other end of the first capacitor is connected with the AGND analog ground port.
6. The dual-circuit display output circuit of the intelligent instrument according to claim 5, wherein:
the main control CPU also comprises a second electrolytic capacitor, a second capacitor, a grounding port and a reference voltage port; one end of the second electrolytic capacitor is connected with the reference voltage port, and the other end of the second electrolytic capacitor is connected with the grounding port;
one end of the second capacitor is connected with the reference voltage port, and the other end of the second capacitor is connected with the grounding port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921736967.0U CN210223521U (en) | 2019-10-16 | 2019-10-16 | Double-loop display output circuit of intelligent instrument |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921736967.0U CN210223521U (en) | 2019-10-16 | 2019-10-16 | Double-loop display output circuit of intelligent instrument |
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| Publication Number | Publication Date |
|---|---|
| CN210223521U true CN210223521U (en) | 2020-03-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921736967.0U Withdrawn - After Issue CN210223521U (en) | 2019-10-16 | 2019-10-16 | Double-loop display output circuit of intelligent instrument |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110544462A (en) * | 2019-10-16 | 2019-12-06 | 广东科瑞德电气科技有限公司 | Double-loop display output circuit of intelligent instrument |
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2019
- 2019-10-16 CN CN201921736967.0U patent/CN210223521U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110544462A (en) * | 2019-10-16 | 2019-12-06 | 广东科瑞德电气科技有限公司 | Double-loop display output circuit of intelligent instrument |
| CN110544462B (en) * | 2019-10-16 | 2024-06-11 | 广东科瑞德电气科技有限公司 | Dual-circuit display output circuit of intelligent instrument |
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