CN210200711U - Chip, input/output structure and pad layer - Google Patents
Chip, input/output structure and pad layer Download PDFInfo
- Publication number
- CN210200711U CN210200711U CN201921138190.8U CN201921138190U CN210200711U CN 210200711 U CN210200711 U CN 210200711U CN 201921138190 U CN201921138190 U CN 201921138190U CN 210200711 U CN210200711 U CN 210200711U
- Authority
- CN
- China
- Prior art keywords
- metal layer
- input
- region
- layer
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002184 metal Substances 0.000 claims abstract description 194
- 230000005669 field effect Effects 0.000 claims abstract description 29
- 238000002161 passivation Methods 0.000 claims description 9
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 abstract description 12
- 238000013461 design Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 3
- 230000002180 anti-stress Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000000740 bleeding effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model relates to a chip, an input/output structure and a cushion layer, wherein the cushion layer comprises a first metal layer, a second metal layer group and a third metal layer group which are arranged in sequence along the direction close to a chip device; the second metal layer group comprises mutually independent through regions, an input and output power supply region and an input and output region, the through regions are respectively connected with the first metal layer and the third metal layer group through the through hole layers, the first metal layer is connected with the packaging frame, and the third metal layer group is respectively communicated with the input and output power supply region and the input and output region through anti-static MOS field effect transistors in the chip. The input and output power supply area and the input and output area are released to form power supply and ground routing respectively, so that the resistance of the power supply and the ground is reduced, the leakage path of the anti-static MOS field effect transistor is enhanced, and the anti-static capability of the input and output structure is improved; the design of the cushion layer is simplified, the area of the input and output structure is reduced, and the packaging convenience of the chip is greatly improved.
Description
Technical Field
The utility model relates to a semiconductor device technical field especially relates to a chip, input/output structure and bed course.
Background
In an integrated circuit, the size of a die (die) determines the cost of the chip, and the size of an input/output structure (IO) particularly in the case of an IO limited chip (PAD limit) directly affects the size of the die (die), and the IO structure needs to reduce the area as much as possible while meeting design indexes of performance such as sequential logic, electrostatic discharge (ESD) prevention, and the like, thereby increasing design margins for layout of a top layer, placement of PADs, and selection of packages. The chip device is arranged on a CUP (circuit under PAD) IO in a mode of being arranged below the bonding PAD, the bonding PAD (PAD) is stacked on an anti-static Electricity (ESD) device of an input/output structure (IO), compared with the common mode, the extra occupied area for arranging the bonding PAD (PAD) is saved, the area of the input/output structure (IO) is reduced, and the use is wide. The CUP scheme of the existing chip below the bonding pad mostly adopts a multilayer metal cushion layer (more than or equal to 2), a large amount of metal resources are only used for stress support, metal resources of an anti-static (ESD) discharge channel are limited, and the anti-static (ESD) capacity is weak.
Therefore, it is desirable to provide a chip, an input-output structure and a pad layer to solve the deficiencies of the prior art.
SUMMERY OF THE UTILITY MODEL
In order to solve the problems in the prior art, the utility model provides a chip, input/output structure and bed course.
A cushion layer of a chip input and output structure comprises a first metal layer, a second metal layer group and a third metal layer group which are sequentially arranged along the direction close to a chip device;
the second metal layer group comprises mutually independent through regions, an input and output power supply region and an input and output region, the through regions are respectively connected with the first metal layer and the third metal layer group through the through hole layers, the first metal layer is connected with the packaging frame, and the third metal layer group is respectively communicated with the input and output power supply region and the input and output region through anti-static MOS field effect transistors in the chip.
Furthermore, the second metal layer group comprises at least two metal layers which are connected in sequence through hole layers in the thickness direction, the through hole layer and the at least two metal layers respectively comprise mutually independent through areas, input and output power supply areas and input and output areas, the through areas of the through hole layer and the at least two through areas of the metal layers form the through areas of the second metal layer group, the input and output power supply areas of the through hole layer and the at least two input and output power supply areas of the metal layers form the input and output power supply areas of the second metal layer group, and the input and output areas of the through hole layer and the at least two input and output areas of the metal layers form the input and output areas of the second metal layer group.
Furthermore, the third metal layer group is respectively connected with the D end of the N-type anti-static MOS field effect transistor and the D end of the P-type anti-static MOS field effect transistor.
Furthermore, the input and output power supply area is connected with the S end of the P-type anti-static MOS field effect transistor.
Furthermore, the input and output area is connected with the S end of the N-type anti-static MOS field effect transistor.
Further, the second metal layer group further includes a logic power supply area and a logic area which are independent from the conduction area, the input/output power supply area and the input/output area, and the logic power supply area and the logic area are also independent from each other;
the logic power supply area and the logic area are respectively connected with a logic area in a chip.
Furthermore, the through hole layer and the at least two metal layers respectively comprise a logic power supply area and a logic area which are mutually independent from the conducting area, the input and output power supply area and the input and output area, the logic power supply area of the through hole layer and the logic power supply area of the at least two metal layers form a logic power supply area of the second metal layer group, and the logic area of the through hole layer and the logic area of the at least two metal layers form a logic area of the second metal layer group.
Furthermore, the third metal layer group comprises a metal layer or at least two metal layers connected through the through hole layer in sequence according to the thickness direction of the third metal layer group.
Further, the thickness of the first metal layer is respectively greater than the thickness of the metal layer of the second metal layer group and the thickness of the metal layer of the third metal layer group.
Furthermore, a passivation layer is further arranged on one side, far away from the second metal layer group, of the first metal layer.
Furthermore, the passivation layer is provided with a wiring window, the first metal layer is exposed at the wiring window, and the exposed first metal layer is connected with the packaging frame through a bonding wire.
Furthermore, the first metal layer is provided with at least one anti-stress hole.
Furthermore, the first metal layer, the second metal layer group, the third metal layer group and the through hole layer are all embedded in the dielectric layer; the via layer includes at least one alloy post embedded within the dielectric layer.
The second metal layer group comprises one conducting area or a plurality of mutually independent conducting areas.
Based on the same invention thought, the utility model also provides a chip input/output structure, including the cushion layer of the chip input/output structure.
Based on the same invention thought, the utility model provides a chip, including chip input/output structure.
The technical scheme of the utility model compare with closest prior art and have following advantage:
the utility model provides a technical scheme provides a chip input/output structure's bed course, through dividing into independent conducting area, input/output power supply area and input/output area with the second metal layer group, and only the conducting area is used for combining first metal layer and the third metal layer group anti-static MOS field effect transistor and the encapsulation frame in the chip, and the input/output power supply area and the input/output area independent with the conducting area are released respectively, form the line of walking of power and ground respectively, effectively reduce the resistance of power and ground, the route of bleeding of anti-static MOS field effect transistor has been strengthened, and then the anti-static ability of input/output structure has been promoted; and the first metal layer window area for being directly connected with the packaging frame is used as a bonding pad, and the chip device and other layers of the cushion layer are positioned below the bonding pad and distributed in a layered manner with the bonding pad, so that the design of the cushion layer is simplified, the area of an input-output structure is reduced, and the packaging convenience of the chip is greatly improved.
Drawings
Fig. 1 is a top view of a pad layer of a first form of a chip input/output structure provided in the present invention;
FIG. 2 is a cross-sectional view taken at the location of line AB of FIG. 1;
fig. 3 is a schematic circuit diagram of a pad layer of a first form of the chip input/output structure provided in the present invention;
fig. 4 is a top view of a pad layer of a second chip input/output structure according to the present invention.
Wherein, 1-a first metal layer; 2-a second metal layer group; 3-a third metal layer group; 4-a via layer; 5-a conducting region; 6-input/output area; 7-input/output power supply area; 8-logical area; 9-logic power supply area; a 10-alloy post; 11-a metal layer; 12-a passivation layer; 13-a wiring window; 14-stress-proof holes; 15-welding wires; 16-N type anti-static MOS field effect transistor; 17-P type anti-static MOS field effect transistor; 18-logical area.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this application, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.
Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.
Furthermore, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail with reference to the accompanying examples and figures 1-4. Fig. 1 is a top view of a pad layer of a chip input/output structure provided by the present invention; FIG. 2 is a cross-sectional view taken along line AB of FIG. 1; fig. 3 is a schematic circuit diagram of a pad layer of a chip input/output structure provided by the present invention; and fig. 4 is a plan view of a pad layer of a chip input/output structure according to a second embodiment of the present invention.
The utility model provides a cushion layer of a chip input/output structure, which comprises a first Metal layer (Top Metal)1, a second Metal layer group 2 and a third Metal layer group 3 which are arranged in sequence along the direction close to a chip device; the second metal layer group 2 comprises mutually independent through areas 5, input and output power supply areas 7 and input and output areas 6, the through areas 5 are respectively connected with the first metal layer 1 and the third metal layer group 3 through the through hole layers 4, the first metal layer 1 is connected with a packaging frame, and the third metal layer group 3 is connected with the input and output power supply areas 7 and the input and output areas 6 respectively communicated with anti-static MOS field effect transistors in the chip.
The second metal layer group 2 is divided into an independent conduction region 5, an input/output power supply region 7 and an input/output region 6, only the conduction region 5 is used for connecting the anti-static MOS field effect transistor in the chip and the packaging frame in combination with the first metal layer 1 and the third metal layer group 3, the packaging frame can reserve an exposed part in the subsequent packaging process, then the exposed part is bent to form a pin of the chip, and the pin is communicated with the first metal layer 1 packaged in the chip; the input/output power supply area 7 and the input/output area 6 which are respectively independent from the conducting area 5 are released to respectively form power supply and ground wiring, so that the resistance of the power supply and the ground is effectively reduced, the leakage path of the anti-static MOS field effect transistor is enhanced, and the anti-static capability of the input/output structure is further improved; and the window area of the first metal layer 1 directly connected with the packaging frame is used as a bonding pad, and other layers of the chip device and the cushion layer are arranged below the bonding pad and distributed in a layered manner with the bonding pad, so that the design of the cushion layer is simplified, the area of an input-output structure is reduced, and the packaging convenience of the chip is greatly improved.
The utility model discloses an in some embodiments, second metal layer group 2 is including looping through at least two-layer metal level 11 that through via layer 4 connects according to its thickness direction, via layer 4 and at least two-layer metal level 11 all includes mutually independent conduction area 5, input/output power supply area 7 and input/output area 6, conduction area 5 and at least two-layer of via layer 4 conduction area 5 of metal level 11 is constituteed conduction area 5 of second metal layer group 2, input/output power supply area 7 and at least two-layer of via layer 4 the input/output power supply area 7 of metal level 11 is constituteed the input/output power supply area 7 of second metal layer group 2, input/output area 6 and at least two-layer of via layer 4 input/output area 6 of metal level 11 is constituteed the input/output area 6 of second metal layer group 2.
The cushion layer is a multilayer structure and is a metal layer 11 and through hole layer 4 alternate structure, and the preparation is completed according to the sequence of one layer and one layer, so the second metal layer group 2 is a metal layer 11 and through hole layer 4 alternate structure, and the whole second metal layer group 2 is divided into a plurality of independent areas by a dielectric layer, wherein the independent areas comprise a conducting area 5, an input and output power supply area 7 and an input and output area 6, the structures of the previous layers are divided into three parts corresponding to the conducting area 5, the input and output power supply area 7 and the input and output area 6, the conducting area 5 of each layer structure forms a complete conducting area 5, the input and output power supply area 7 of each layer structure forms a complete input and output power supply area 7, and the input and output area 6 of each layer structure forms a complete input and output area 6.
In some embodiments of the present invention, the third metal layer group 3 is respectively connected to the D terminal of the N-type anti-static MOS field effect transistor 16 and the D terminal of the P-type anti-static MOS field effect transistor 17. The D end of the N-type anti-static MOS field effect transistor 16 and the D end of the P-type anti-static MOS field effect transistor 17 are connected with the PAD area of the first metal layer 1 through the third metal layer group 3 and the conduction area 5 of the second metal layer group 2, so that static (ESD) voltage introduced by the PAD (PAD) can rapidly reach the static discharge channel of the anti-static MOS field effect transistor, the static (ESD) voltage is prevented from entering other circuits of the input-output structure, and other functional devices are prevented from being damaged.
In some embodiments of the present invention, the input/output power region 7 is connected to the S terminal of the P-type anti-static MOS fet 17. The input and output power supply area 7 is a metal resource released from the second metal layer group 2 and is used for power supply wiring, when a plurality of input and output structures are sequentially spliced together to form a ring, a power supply loop of a chip level can be formed, and the resistance from an input and output structure (IO) to a power supply can be greatly reduced through the power supply wiring channel, so that the antistatic (ESD) capability of the chip level is improved.
In some embodiments of the present invention, the input/output area 6 is connected to the S terminal of the N-type anti-static MOS fet 16. The input/output area 6 is a metal resource released from the second metal layer group 2, is used for wiring the ground, and when a plurality of input/output structures are spliced together at one time to form a ring, a loop of the ground of a chip level can be formed, and the wiring channel of the ground can greatly reduce the resistance from the input/output structure (IO) to the ground, so that the antistatic (ESD) capability of the chip level is improved.
In some embodiments of the present invention, the second metal layer group 2 further includes a logic power region 9 and a logic region 8 which are independent from the conducting region 5, the input/output power region 7 and the input/output region 6, and the logic power region 9 and the logic region 8 are also independent from each other; the logic power supply area 9 and the logic area 8 are respectively connected with a logic area 18 in the chip.
Only the conducting area 5 in the second metal layer group 2 is used for connecting the first metal layer 1 and the third metal layer group 3, and further is used for connecting the packaging frame and the anti-static MOS field effect transistor, so that a large amount of metal resources can be released for other purposes, and besides the input/output power supply area 7 and the input/output area 6 which are independently formed by the released metal resources, another group of power supplies and areas can be formed, wherein the group of power supplies and areas correspond to the logic area 18 in the chip, and are the logic power supply area 9 and the logic area 8 which are respectively connected with the logic area 18.
The utility model discloses an in some embodiments, through-hole layer 4 and at least two-layer the metal layer all include respectively with the through-hole district 5 the input/output power supply area 7 with the mutually independent logic power supply area 9 and the logic area 8 in input/output area 6, the logic power supply area 9 and at least two-layer of through-hole layer 4 the logic power supply area 9 of metal layer is constituteed the logic power supply area 9 of second metal layer group 2, the logic area 8 and at least two-layer of through-hole layer 4 the logic area 8 of metal layer is constituteed the logic area 8 of second metal layer group 2. The cushion layer is a multilayer structure and is a metal layer 11 and through hole layer 4 alternate structure, and the preparation is completed according to the preparation of one layer in sequence, so the second metal layer group 2 is a metal layer 11 and through hole layer 4 alternate structure, and the whole second metal layer group 2 is divided into a plurality of independent areas by a dielectric layer, and comprises a conduction area 5, an input and output power area 7 and an input and output area 6, and also comprises an independent logic power area 9 and a logic area 8, besides the aforementioned each layer structure is divided into three parts corresponding to the conduction area 5, the input and output power area 7 and the input and output area 6, the logic power area 9 and the logic area 8 are also provided, the logic power area 9 of each layer structure forms a complete logic power area 9, and the input logic area 8 of each layer structure forms a complete input logic area 8.
In some embodiments of the present invention, the third metal layer group 3 includes one metal layer 11 or at least two metal layers 11 connected sequentially through the via layer 4 in the thickness direction. The third metal layer group 3 is directly connected with the anti-static MOS field effect transistor in the chip, and the number of the metal layers 11 of the third metal layer group 3 can be selected according to the voltage release requirement.
In some embodiments of the present invention, the thickness of the first metal layer 1 is greater than the thickness of the metal layer 11 of the second metal layer group 2 and the thickness of the metal layer 11 of the third metal layer group 3, respectively. The window region of first metal level 1 is as the pad, through increasing its thickness, can simplify the number of piles of metal layer 11 in the whole bed course, and great thickness also can make other parts of the bed course of its below and other parts of input-output structure (IO) not receive routing pressure and the influence of pulling stress moreover, and then guarantees the electric connection between the anti-static MOS field effect transistor of pad to the chip.
In some embodiments of the present invention, a passivation layer 12 is further disposed on one side of the first metal layer 1 away from the second metal layer group 2. The passivation layer 12 can protect the first metal layer 1, the second metal layer group 2, and the third metal layer group 3.
In some embodiments of the present invention, the passivation layer 12 is provided with a wire window 13, the wire window 13 exposes the first metal layer 1, and the exposed first metal layer 1, i.e. the pad, is connected to the package frame through a bonding wire 15. The passivation layer 12 is provided with a wiring window 13 for routing, a lead is pulled out through the first metal layer 1 leaked from the wiring window 13, and the lead is far away from the stress area of the bonding pad and is wired outside the input and output area 6, the input and output power area 7, the logic area 8 and the logic power area 9 of the second metal layer group 2.
In some embodiments of the present invention, the first metal layer 1 is provided with at least one stress-proof hole 14. The area of a wiring window 13 of the first metal layer 1 is used as a bonding pad, if the bonding pad is deformed, the electric connection between a bonding wire and an anti-static MOS field effect tube in a chip is influenced, the anti-static capability of the bonding pad is influenced, the first metal layer 1 is easily deformed due to stress generated by expansion with heat and contraction with cold or other influences, and the anti-stress hole 14 is arranged, so that the stress can be eliminated when the stress and the deformation are generated, and the influence of the deformation on the electric connection between a welding pin and the anti-static MOS field effect tube in the chip is avoided; preferably, the stress-proof hole 14 is designed to have a rectangular or elongated cross section.
In some embodiments of the present invention, the first metal layer 1, the second metal layer group 2, the third metal layer group 3, and the via layer 4 are all embedded in a dielectric layer; the via layer 4 includes at least one alloy pillar 10 embedded within the dielectric layer. The alloy columns 10 form a through hole group for connecting different metal layers 11, wherein the through hole group comprises different metal layers 11 connected in the second metal layer group 2, metal layers 11 connected in the first metal layer 1 and the second metal layer group 2, and metal layers 11 connected in the second metal layer group 2 and metal layers 11 connected in the third metal layer group 3.
In some embodiments of the present invention, the second metal layer group 2 includes one conducting area 5 or a plurality of mutually independent conducting areas 5. As shown in fig. 1 to 3, the second metal layer sequence 2 is provided with one conducting region 5, and as shown in fig. 4, the second metal layer sequence 2 is provided with two conducting regions 5. Of course, by dividing the second metal layer group 2 more finely, a plurality of conducting regions 5 can be provided, which is in communication with the provision of one conducting region 5 and the provision of two conducting regions 5, and the manufacturing process is the same.
The utility model provides a chip input/output structure's bed course has reduced the chip area, in the actual encapsulation test moreover, accords with the encapsulation requirement, prevents static (ESD) ability moreover and has passed through and be greater than 8KV HBM ESD test.
Based on the same invention thought, the utility model also provides a chip input/output structure, including the cushion layer of the chip input/output structure.
Based on the same invention thought, the utility model provides a chip, including chip input/output structure.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (16)
1. A cushion layer of a chip input and output structure is characterized by comprising a first metal layer (1), a second metal layer group (2) and a third metal layer group (3) which are sequentially arranged along the direction close to a chip device;
the second metal layer group (2) includes mutually independent conducting region (5), input/output power supply region (7) and input/output area (6), conducting region (5) respectively through-hole layer (4) with first metal layer (1) with third metal layer group (3) are connected, first metal layer (1) is connected with the encapsulation frame, third metal layer group (3) input/output power supply region (7) with input/output area (6) communicate with the antistatic MOS field effect transistor in the chip respectively.
2. The pad layer of the chip i/o structure of claim 1, wherein the second metal layer group (2) includes at least two metal layers (11) connected sequentially through a via layer (4) in a thickness direction thereof, the via layer (4) and the at least two metal layers (11) each include a via region (5), an i/o power supply region (7), and an i/o area (6) that are independent of each other, the via region (5) of the via layer (4) and the via region (5) of the at least two metal layers (11) constitute the via region (5) of the second metal layer group (2), the i/o power supply region (7) of the via layer (4) and the i/o power supply region (7) of the at least two metal layers (11) constitute the i/o power supply region (7) of the second metal layer group (2), the i/o area (6) of the via layer (4) and the i/o power supply region (7) of the at least two metal layers (11) constitute the i/o power supply region (7 The outlet area (6) forms an input/output area (6) of the second metal layer group (2).
3. The pad layer of the chip input-output structure of claim 1, wherein the third metal layer group (3) is connected to the D terminal of the N-type anti-static MOS field effect transistor (16) and the D terminal of the P-type anti-static MOS field effect transistor (17), respectively.
4. The pad layer of the chip input-output structure of claim 1, wherein the input-output power region (7) is connected to the S terminal of the P-type anti-static MOS field effect transistor (17).
5. The pad layer of the chip input-output structure of claim 1, wherein the input-output region (6) is connected with the S terminal of an N-type anti-static MOS field effect transistor (16).
6. The pad layer of the chip input-output structure of claim 2, wherein the second metal layer group (2) further comprises a logic power region (9) and a logic region (8) which are independent from the conduction region (5), the input-output power region (7) and the input-output region (6), and the logic power region (9) and the logic region (8) are also independent from each other;
the logic power supply area (9) and the logic area (8) are respectively connected with a logic area (18) in the chip.
7. The pad layer of the chip i/o structure of claim 6, wherein the via layer (4) and the at least two metal layers each include a logic power region (9) and a logic region (8) that are independent of the via region (5), the i/o power region (7), and the i/o region (6), respectively, the logic power region (9) of the via layer (4) and the logic power region (9) of the at least two metal layers (11) constitute the logic power region (9) of the second metal layer group (2), and the logic region (8) of the via layer (4) and the logic region (8) of the at least two metal layers (11) constitute the logic region (8) of the second metal layer group (2).
8. Pad layer of a chip input output structure according to claim 2, characterized in that the third metal layer group (3) comprises one metal layer (11) or at least two metal layers (11) connected in sequence through via layers (4) in its thickness direction.
9. Pad layer of a chip input-output structure according to claim 8, characterized in that the thickness of the first metal layer (1) is larger than the thickness of the metal layer (11) of the second metal layer group (2) and the thickness of the metal layer (11) of the third metal layer group (3), respectively.
10. Pad layer of a chip input and output structure according to claim 9, characterized in that the side of the first metal layer (1) remote from the group of second metal layers (2) is further provided with a passivation layer (12).
11. The pad layer of the chip input-output structure of claim 10, wherein the passivation layer (12) is provided with a wire window (13), the first metal layer (1) is exposed at the wire window (13), and the exposed first metal layer (1) is connected to a package frame through a bonding wire (15).
12. Pad layer of a chip input-output structure according to claim 1, characterized in that the first metal layer (1) is provided with at least one stress-proof hole (14).
13. The pad layer of the chip input-output structure according to any one of claims 1 to 12, wherein the first metal layer (1), the second metal layer group (2), the third metal layer group (3) and the via layer (4) are embedded in a dielectric layer; the via layer (4) comprises at least one alloy pillar (10) embedded in the dielectric layer.
14. Pad layer of a chip input output structure according to any of claims 1 to 12, characterized in that the second metal layer group (2) comprises one said conductive region (5) or a plurality of said conductive regions (5) independent of each other.
15. A chip input/output structure comprising the pad layer of the chip input/output structure of any one of claims 1 to 14.
16. A chip comprising the chip input-output structure of claim 15.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921138190.8U CN210200711U (en) | 2019-07-18 | 2019-07-18 | Chip, input/output structure and pad layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921138190.8U CN210200711U (en) | 2019-07-18 | 2019-07-18 | Chip, input/output structure and pad layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210200711U true CN210200711U (en) | 2020-03-27 |
Family
ID=69868138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921138190.8U Active CN210200711U (en) | 2019-07-18 | 2019-07-18 | Chip, input/output structure and pad layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210200711U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491849A (en) * | 2019-07-18 | 2019-11-22 | 珠海格力电器股份有限公司 | Chip, input/output structure and bed course |
-
2019
- 2019-07-18 CN CN201921138190.8U patent/CN210200711U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491849A (en) * | 2019-07-18 | 2019-11-22 | 珠海格力电器股份有限公司 | Chip, input/output structure and bed course |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101388385B (en) | Semiconductor device | |
| US20050200017A1 (en) | Integrated circuit bond pad structures and methods of making | |
| CN108695264B (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| KR20060130125A (en) | Semiconductor package and semiconductor device | |
| KR20060004930A (en) | Integrated circuit die i/o cells | |
| JP2008147604A (en) | Semiconductor device package featuring encapsulated leadframe with projecting bumps or balls | |
| CN107256831A (en) | The method for manufacturing semiconductor packages | |
| US20170179059A1 (en) | Semiconductor device having conductive bump with improved reliability | |
| CN101383333A (en) | Semiconductor package | |
| CN210200711U (en) | Chip, input/output structure and pad layer | |
| CN107146780B (en) | Semiconductor chip and semiconductor device | |
| US7554133B1 (en) | Pad current splitting | |
| TWI397163B (en) | Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package | |
| CN101517733B (en) | Stacked integrated circuit chip assembly | |
| KR101355274B1 (en) | Integrated circuit having second substrate to facilitate core power and ground distribution | |
| WO2006023034A2 (en) | Probe pad arrangement for an integrated circuit and method of forming | |
| US20100171211A1 (en) | Semiconductor device | |
| US20170179049A1 (en) | Power grid balancing apparatus, system and method | |
| CN103337486B (en) | Semiconductor packaging structure and manufacture method thereof | |
| TW201244037A (en) | Integrated circuit chip package and manufacturing method thereof | |
| KR20060052876A (en) | Semiconductor device and method for making the same | |
| US8664776B2 (en) | Interconnection tape providing a serial electrode pad connection in a semiconductor device | |
| CN110491849A (en) | Chip, input/output structure and bed course | |
| US7242083B2 (en) | Substrate for IC package | |
| CN103531580A (en) | Chip packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200917 Address after: 519015 Room 1001, Lianshan Lane, Jida Jingshan Road, Xiangzhou District, Zhuhai City, Guangdong Province Patentee after: Zhuhai Zero Boundary Integrated Circuit Co.,Ltd. Patentee after: GREE ELECTRIC APPLIANCES,Inc.OF ZHUHAI Address before: 519070 Guangdong city of Zhuhai Province Qianshan Patentee before: GREE ELECTRIC APPLIANCES,Inc.OF ZHUHAI |