CN210182389U

CN210182389U - OLED panel

Info

Publication number: CN210182389U
Application number: CN201921363306.8U
Authority: CN
Inventors: Yuhuai Chen; 陈宇怀
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2019-08-21
Filing date: 2019-08-21
Publication date: 2020-03-24
Anticipated expiration: 2029-08-21

Abstract

An OLED panel and a manufacturing method thereof are provided, wherein the method comprises the following steps of preparing a substrate, sequentially forming a first conductive film layer and a gate electrode layer on the substrate, etching all gate metal in a capacitance area, reserving the gate metal and the first conductive film layer in a thin film transistor area, and etching the gate metal and the conductive film layer in other areas according to patterning requirements; and then, manufacturing a gate insulating layer, manufacturing an active layer in a thin film transistor area, manufacturing an etching barrier layer and reserving a via hole, sequentially forming a second conductive film layer and an electrode layer, etching all electrode metal in a capacitor area, reserving a source drain electrode and the second conductive film layer in the thin film transistor area, and enabling the source drain electrode to be in contact with the active layer through the second conductive film layer. The utility model discloses a transparent conductive film of filming and metal film layer to combine the grey scale light shield, only remain transparent conductive film in picture element electric capacity district, make the area of panel metal film layer further reduce, increase the light transmissivity of panel.

Description

OLED panel

Technical Field

The utility model relates to a new OLED's panel design especially relates to an increase transparent OLED panel design of luminousness.

Background

With the development of display technology, various new technologies are emerging, and the transparent display technology is receiving more and more attention due to the characteristic of the transparent display panel and its unique application.

The core of the transparent display technology is a transparent display panel, which is a transparent panel capable of displaying images, unlike a double-sided display panel, which is a display device capable of displaying images on both sides of a display panel simultaneously. When the transparent display panel is closed, the panel is like a piece of transparent glass, and when the transparent display panel works, a viewer can view the content displayed on the panel and can see objects behind the panel through the panel.

In recent years, researchers have conducted extensive research on transparent display technologies, and have tried various display technologies, such as liquid crystal display technologies, organic light emitting diode display technologies, plasma display technologies, and the like. In general, the transparent display technology can be classified into two types according to the display. For a non-self-luminous display device such as a liquid crystal display, a transparent display technology mainly utilizes external light or rearranges a backlight source to achieve transparent display; for the self-luminous display devices such as OLED and PDP, the transparent display technology mainly means that the opaque part in the original device is replaced or removed by adopting a material with high transparency through technical improvement, and the overall transparency of the device is continuously improved to realize transparent display.

Disclosure of Invention

Therefore, it is necessary to provide a new OLED panel structure design to achieve the technical effects of improving the light transmittance of the capacitor region and further improving the transparency of the product.

In order to achieve the above object, the present invention provides an OLED panel, which includes a thin film transistor region and a capacitor region, wherein the capacitor region includes a capacitor plate, the capacitor region does not include a metal layer, the capacitor plate is connected to an electrode layer of the thin film transistor region, and the capacitor plate is a transparent conductive film layer.

Specifically, the capacitor plates comprise a gate insulating layer or an etching barrier layer.

Specifically, the capacitor area comprises a substrate, a capacitor lower electrode plate, a grid electrode insulating layer, an etching barrier layer, a capacitor upper electrode plate, a passivation layer and a flat layer which are arranged from bottom to top.

Further, the thin film transistor region comprises a substrate, a first conductive film layer, a gate electrode layer, a gate insulating layer, an active layer, a second conductive film layer, an etching barrier layer, a source drain electrode layer, a passivation layer and a flat layer which are arranged from bottom to top.

The utility model discloses a transparent conductive film of filming and metal film layer to combine the grey scale light shield, only remain transparent conductive film in picture element electric capacity district, make the area of panel metal film layer further reduce, increase the light transmissivity of panel.

Drawings

FIG. 1 is a schematic cross-sectional view of an OLED panel according to an embodiment;

FIG. 2 is a schematic diagram comparing the prior art with the present embodiment;

FIG. 3 is a schematic diagram of a pixel design according to an embodiment;

fig. 4 is a schematic structural diagram of an array substrate according to an embodiment;

FIG. 5 is a schematic diagram of a panel manufacturing process according to an embodiment;

FIG. 6 is an embodiment of a transparent capacitor plate according to an embodiment;

fig. 7 is a schematic structural diagram of an array substrate according to an embodiment;

FIG. 8 is a schematic structural diagram of an array substrate according to an embodiment;

fig. 9 is a manufacturing process of the panel according to the embodiment.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Fig. 1 is a design diagram of the novel OLED panel of the present invention, an OLED panel, including a thin film transistor region and a capacitor region, as shown in the figure, the thin film transistor region (hereinafter referred to as TFT region) is located at the center of the cross-sectional view, i.e. used for arranging the wire routing portion, the left side in the figure shows the structure of the capacitor region portion, and the right side is a light transmission region. From the figure we can see. The capacitor region includes capacitor plates, which can be used to stabilize the electrical operation of the TFT. In the technical scheme, the capacitor area does not comprise a metal layer, and the polar plates of the capacitor area are changed into transparent conductive film layers by not arranging the light-shielding metal layer. The utility model discloses the scheme still makes the source drain pass through transparent conductive film and active layer overlap joint, can reduce ohmic impedance, further improves thin film transistor's electrical characteristic.

Fig. 2 further shows the utility model discloses with the contrast effect of conventional design, the electric capacity metal level among the conventional technical scheme, in the preparation technology with source drain metal, the grid metal compatibility on the TFT board, the patterning is comparatively simple and convenient, but under the condition that the electric capacity district accounts for the very big position of pixel, it is not enough only to lean on the transparency that transmission window improves the panel. FIG. 3 shows some embodiments of pixel designs, in which the transparency of the whole panel is greatly improved when the capacitor region is designed to be transparent.

Fig. 4 shows an embodiment of the present invention, which shows a specific structure of the array substrate in the panel. The film layer structure of the TFT area sequentially comprises a transparent substrate as a base, a grid scanning line GE, a grid insulating layer GI, an active layer IGZO, an etching barrier layer ES, a source and drain signal line SD and a passivation layer PV from bottom to top. In a specific design, we can see that the capacitor plates include a gate insulating layer or an etching barrier layer therebetween. The capacitor area comprises a substrate, a capacitor lower electrode plate, a grid electrode insulating layer, an etching barrier layer, a capacitor upper electrode plate, a passivation layer and a flat layer which are arranged from bottom to top. And in the thin film transistor area, the conductive film layers are arranged between the source and drain electrodes and the active layer and between the grid scanning line and the substrate. Besides the passivation layer, a flat layer is arranged. The thin film transistor area comprises a substrate, a first conductive film layer, a grid electrode insulating layer, an active layer, a second conductive film layer, an etching barrier layer, a source drain electrode layer, a passivation layer and a flat layer which are arranged from bottom to top. The panel structure designed by the scheme can increase the transmissivity of the capacitor and simultaneously improve the electrical property of the active layer.

In order to manufacture the panel of the transparent capacitor, the method for manufacturing the OLED panel comprises the following steps of preparing a substrate, sequentially forming a first conductive film layer and a gate electrode layer on the substrate, etching all gate metal in a capacitor area, reserving the gate metal and the first conductive film layer in a thin film transistor area, and etching the gate metal and the conductive film layer in other areas according to patterning requirements;

and then, manufacturing a gate insulating layer, manufacturing an active layer in a thin film transistor area, manufacturing an etching barrier layer and reserving a via hole, sequentially forming a second conductive film layer and an electrode layer, etching all electrode metal in a capacitor area, reserving a source drain electrode and the second conductive film layer in the thin film transistor area, and enabling the source drain electrode to be in contact with the active layer through the second conductive film layer. Further, the method comprises the step of manufacturing a flat layer and a pixel definition layer.

Specific implementation details we can look from one of fig. 5. As shown in fig. 5, the preparation of the OLED panel in the solution of the present invention includes the following steps:

01. GE: forming a first metal layer on a substrate to manufacture a gate drive circuit and a first electrode plate of a capacitor area;

02. GI: manufacturing a grid electrode insulating layer on the grid electrode;

03. and SE: manufacturing an active layer IGZO or other metal oxides and other materials on the grid;

04. ES: manufacturing an etching barrier layer on the active layer, protecting a channel of the active layer, and etching a via hole to connect the active layer with a source/drain;

05. SD: manufacturing a source/drain circuit and a second electrode plate of the capacitor area, wherein the flow is consistent with GE;

06. PV: manufacturing a passivation layer on the source/drain electrode, etching a through hole to expose the surface of the drain electrode, and etching a through hole at the transmission window to expose the surface of the substrate to increase the transparency of the panel;

07. OP: manufacturing an organic flat layer on the passivation layer, developing an OP through hole exposed drain electrode on the PV through hole, and exposing the surface of the substrate at the projection window;

08. AN: manufacturing transparent anodes such as ITO on the flat layer and patterning, wherein the anode AN is connected with the drain electrode through the OP/IP through hole;

09. PD: manufacturing an organic pixel definition layer, and developing an RGB pattern opening and a transmission window through hole;

10. PS: patterning the PS layer of the supporting substrate and the packaging cover plate;

11. an OLED light emitting layer: an organic light-emitting layer is evaporated on the anode at the PD via hole;

12. metal cathode: and evaporating a transparent metal cathode.

An embodiment of the fabrication of transparent capacitor plates on a substrate is shown in the example of fig. 6, comprising the steps of,

step1, continuously forming a transparent conductive layer and a metal film layer, wherein the transparent conductive layer can be preferably ITO (indium tin oxide), the material is not particularly limited, and the metal film layer can be one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with excellent conductivity and alloys;

step2, exposing by using a half-color mask, wherein the light transmittance of the capacitor area is 50%, the transmittance of the grid wiring area is 0%, and the transmittance of the other areas is 100%;

step3, developing the photoresist layer by using a developing solution after exposure, completely removing the photoresist in the 100% transmittance area of the photomask, keeping the photoresist in the 50% and 0% transmittance areas, and thinning the photoresist in the 50% transmittance area compared with the photoresist in the 0% transmittance area;

step4, etching the film layer to primarily transfer the photomask pattern, wherein the metal and ITO etching can be performed for one-time etching or secondary etching according to the film material;

step5, removing the 50% light transmittance area light resistance through ashing treatment;

and step6, etching is carried out again after ashing treatment, metal above the 50% light transmittance area is removed through etching time control or selectivity of etching liquid medicine, square ITO is remained, and then residual photoresist is removed to finish pattern transfer.

Therefore, referring to fig. 6, all the gate metal is etched in the capacitor region, the gate metal and the first conductive film layer remain in the tft region, and the gate metal and the conductive film layer are etched in other regions according to the patterning requirement, specifically,

coating a photoresist on a grid layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a grid wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the grid metal and the first conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the grid metal of the capacitance area and the photoresist of the grid wiring part.

On the other hand, all electrode metals are etched in the capacitor area, and a source drain and a second conductive film layer are reserved in the thin film transistor area, which is also basically similar, and the method comprises the following steps:

coating a photoresist on an electrode layer, exposing by using a half-color mask plate, setting the light transmittance of a capacitance area to be 50%, setting the light transmittance of a source drain wiring part of a thin film transistor to be 100%, setting the light transmittance of other parts to be 100%, developing by using a developing solution, removing the photoresist of other parts, etching and transferring a photomask pattern, completely removing the electrode metal and the second conductive film layer of other parts, removing the photoresist of the capacitance area through ashing treatment, then etching again, and removing the electrode metal of the capacitance area and the photoresist of the electrode wiring part.

In other preferred embodiments, when the metal cathode is evaporated, the light transmittance can be further increased by adopting a mask plate for evaporation, and a cathode metal film layer structure is not remained in the transmission window area.

In the embodiment shown in fig. 7, another structural scheme of the array substrate is shown, and a film structure in a TFT thin film transistor region is formed by sequentially forming a gate scan line GE, a gate insulating layer GI (first insulating layer), an active layer SE, a source/drain signal line SD, and a passivation layer PV on a transparent substrate. The transparent capacitor region also includes first and second conductive film layers sandwiching the first insulating layer therebetween in this configuration.

Fig. 8 shows another structure of an array substrate in the embodiment, the TFT film structure of the present invention sequentially includes, from bottom to top:

BF: buffer layer

2, SE: active layer (Metal oxide)

3, GI: gate insulating layer (first insulating layer)

4, GE: metal grid (first metal layer)

IL: a second insulating layer

SD: metal source drain (second metal layer)

PV: a passivation layer (third insulating layer).

Fig. 9 illustrates a corresponding method of making the configuration of fig. 8, including the steps of:

01. BF: forming a film buffer layer on the glass substrate, wherein the optional material is organic material, SiOx, SiNx, titanium oxide, aluminum oxide and the like;

02. and SE: forming a film on the buffer layer and patterning the active layer IGZO or other metal oxide materials;

03. GI: forming a film on the active layer and patterning a gate insulating layer, wherein SiOx, SiNx, titanium oxide, aluminum oxide and the like can be selected;

04. GE: forming a first metal layer on the gate insulating layer to manufacture a gate drive circuit and a first electrode plate of the capacitor region, wherein one or more metals with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium and the like and alloys are adopted;

05. IL: forming a film on the grid metal layer and patterning a second insulating layer, wherein SiOx, SiNx, titanium oxide, aluminum oxide and the like can be selected;

06. SD: manufacturing a source/drain circuit and a second electrode plate of the capacitor area, wherein the flow is consistent with GE;

07. PV: and forming a film on the source/drain electrode and patterning a passivation layer, wherein the metal surface of the drain electrode and the surface of the glass substrate are exposed and made of organic materials, SiOx, SiNx, titanium oxide, aluminum oxide and the like.

By the scheme, the OLED panel structure with the transparent capacitor area can be manufactured.

Therefore, the scheme also comprises the following steps of forming a buffer layer on the substrate, patterning an active layer on the buffer layer in the thin film transistor area, patterning a grid insulation layer on the active layer, integrally forming a first conductive film layer and a grid layer, etching all grid metal in the capacitor area, reserving the grid metal and the first conductive film layer in the thin film transistor area, and etching the grid metal and the conductive film layer in other areas according to the patterning requirement; patterning the second insulating layer to expose the active layer in the thin film transistor region and cover the first conductive film layer in the capacitor region; and sequentially forming a second conductive film layer and an electrode layer, etching all electrode metals in the capacitor area, and reserving a source drain electrode and the second conductive film layer in the thin film transistor area, wherein the source drain electrode is in contact with the active layer through the second conductive film layer.

Specifically, the method further comprises the steps of manufacturing a passivation layer, etching to expose the drain metal, and arranging a flat layer and a pixel defining layer.

Further, all the gate metal is etched in the capacitor region, the gate metal and the first conductive film layer are remained in the thin film transistor region, and the gate metal and the conductive film layer are etched in other regions according to the patterning requirement, specifically,

Further, all electrode metal is etched in the capacitor area, and a source drain and a second conductive film layer are reserved in the thin film transistor area, specifically,

In the method, the transparent conductive film and the metal film layer are formed, and the gray-scale photomask is combined, so that only the transparent conductive film is reserved in the pixel capacitance area, the area of the metal film layer of the panel is further reduced, and the light transmittance of the panel is increased.

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims

1. The OLED panel is characterized by comprising a thin film transistor area and a capacitor area, wherein the capacitor area comprises a capacitor plate, the capacitor area does not comprise a metal layer, the capacitor plate is connected with an electrode layer in the thin film transistor area, and the capacitor plate is a transparent conductive film layer.

2. The OLED panel of claim 1, wherein the capacitor plates include a gate insulating layer or an etch stop layer therebetween.

3. The OLED panel of claim 1, wherein the capacitor region comprises a substrate, a capacitor lower electrode plate, a gate insulating layer, an etching barrier layer, a capacitor upper electrode plate, a passivation layer and a planarization layer arranged from bottom to top.

4. The OLED panel of claim 1, wherein the thin film transistor region comprises a substrate, a first conductive film layer, a gate insulating layer, an active layer, a second conductive film layer, an etching stop layer, a source drain layer, a passivation layer and a planarization layer, which are arranged from bottom to top.