CN210005942U

CN210005942U - kinds of hysteresis voltage comparators

Info

Publication number: CN210005942U
Application number: CN201921179008.3U
Authority: CN
Inventors: 伍滔; 金学成; 潘思铭
Original assignee: Chengdu Yichong Semiconductor Co Ltd
Current assignee: Chengdu Yichong Semiconductor Co Ltd
Priority date: 2019-07-25
Filing date: 2019-07-25
Publication date: 2020-01-31
Anticipated expiration: 2029-07-25

Abstract

The utility model relates to a comparator technical field discloses hysteresis voltage comparators, including adjustable reference voltage produces the module, the offset current produces the module, the comparator module, MOS pipe is added to input voltage's geminate transistors department through the switch tube in the comparator module and produces hysteresis voltage, and the charge injection of switch tube can not influence the voltage reference, the current that rethread offset current produced specific temperature coefficient and technological parameter is as the tail current of comparator, thereby it produces temperature coefficient and technological parameter that hysteresis voltage brought to eliminate to add MOS pipe with this tail current, and can image out the current mirror that this current passes through different coefficients and give N this kind of comparator module as the tail current, the comparator that arbitrary different accurate hysteresis voltage can be realized to the width length ratio that changes different comparator input MOS pipe simultaneously, consequently only need N reference comparison voltage, match fairly simplely, when the system needs a plurality of this kind of comparators, the circuit realizes fairly simplely.

Description

kinds of hysteresis voltage comparators

Technical Field

The utility model relates to a comparator technical field, especially kinds of hysteresis voltage comparators.

Background

For example, when the chips need to use N precise hysteresis voltage comparators, the conventional precise hysteresis voltage comparator needs 2N reference voltages to implement, because the requirements of the hysteresis voltages of the different precise hysteresis voltage comparators are different, the proportional difference of the reference voltages is very large, in order to implement the accuracy of the reference voltages, the matching of each voltage dividing resistor needs to be ensured, which consumes a large amount of area, and the accuracy of the comparison is poor, and the switching accuracy of the hysteresis voltage switch is affected when the switching accuracy of the hysteresis voltage switch is affected.

SUMMERY OF THE UTILITY MODEL

The invention aims to provide hysteresis voltage comparators aiming at the problems.

The utility model adopts the technical proposal that hysteresis voltage comparators comprise an adjustable reference voltage generating module, a bias current generating module and a comparator module;

the adjustable reference voltage generating module generates th current, the th current flows into a terminal of a third resistor of the adjustable reference voltage generating module, the other terminal of the third resistor is connected with a power supply terminal, and a terminal of the third resistor forms a voltage point;

the bias current generating module comprises a drain voltage clamping circuit, a MOS transistor M20, a MOS transistor M19, a th current mirror and a second current mirror, the drain voltage clamping circuit comprises an operational amplifier a1, a th resistor, a second resistor, a MOS transistor M15, a MOS transistor M16, a MOS transistor M17 and a MOS transistor M18, drain currents of the MOS transistor M20 and the MOS transistor M19 are equal to a current of an 0, an 1 end of the second resistor is connected with a power supply end, another 2 end of the second resistor is connected with a drain of the MOS transistor M20 and a gate of the MOS transistor M18, a source and a drain of the MOS transistor M18 are respectively connected with the power supply end and a source of the MOS transistor M18, a drain of the MOS transistor M18 is connected with 18 drains of the current mirror 18 th current mirror, an output end of the operational amplifier a 18 is connected with the drains of the MOS transistor M18 and the gate of the MOS transistor M18, an adjustable drain voltage of the operational amplifier a drain of the operational amplifier a transistor M18 is connected with the drain current of the drain of the second transistor M18, a drain voltage clamping circuit, a drain voltage generating source of the second transistor M18, a drain voltage of the second transistor M18 and a drain voltage generating module 18, a drain voltage of the drain of the transistor M18, a drain voltage, a drain of the transistor M18, a drain voltage generating module is connected with a drain of the transistor M18, a drain voltage generating a drain current, a drain voltage, a drain of the transistor M18, a drain voltage;

the comparator module comprises a transistor pair transistor, the grid electrodes of the MOS transistor pair transistor are respectively connected with an input voltage end and a reference voltage end, MOS transistors M3 are arranged at the MOS transistor pair transistor through switching tubes to generate hysteresis voltage, and the bias current generates mirror current through a third current mirror and is input to the source electrode of the MOS transistor M3.

Further , the mirror ratio of the second current mirror is adjustable.

Further , the comparator module includes a pair of MOS transistor M6, MOS transistor M5, MOS transistor M2 and MOS transistor M1, a pair of MOS transistor M4 with a switching transistor M4, a third current mirror composed of MOS transistor M4 and MOS transistor M4, and MOS transistor M4, the bias current is connected to the drain of MOS transistor M4, the source of MOS transistor M4 is connected to a power supply terminal, the gates of MOS transistor M4 and MOS transistor M4 are connected to the power supply terminal, the source of MOS transistor M4 is connected to the power supply terminal, the drain of MOS transistor M4 is connected to the drains of MOS transistor M4, MOS transistor M4 and MOS transistor M4, the sources of MOS transistor M4 and MOS transistor M4 are connected to the power supply terminal, the drains of MOS transistor M4 and MOS transistor M4 are connected to the drain of MOS transistor M4 and MOS transistor M4, the drains of MOS transistor M4 and MOS transistor M4 are connected to the source of the MOS transistor M4, the MOS transistor M4 and the drain of the MOS transistor M4 are connected to the source of the MOS transistor M4, the drain of the MOS transistor M4, the source of the MOS transistor M4, the MOS transistor M4 and the MOS transistor M4, the MOS transistor M4 is connected to the drain of the MOS transistor M4, the source of the MOS transistor M4, the drain of the MOS transistor M4, the MOS transistor M4 is connected to the source of the MOS transistor M4, the drain of the source of the MOS transistor M4, the,

, the length-width ratio of MOS transistor M9 and MOS transistor M10 in the third current mirror is adjustable.

And , using PMOS input pair tube or dual NMOS input pair tube as MOS pair tube.

, the adjustable reference voltage generating module includes an operational amplifier a0, an MOS transistor M21, an MOS transistor M22, an MOS transistor M23, an MOS transistor M24, an MOS transistor M25, a third resistor, and a fourth resistor, an input end of the operational amplifier a 25 is connected to a divided voltage of a reference voltage and a source of the MOS transistor M25, an output end of the operational amplifier a 25 is connected to a gate of the MOS transistor M25, a source and a drain of the MOS transistor M25 are respectively connected to a 25 end of the fourth resistor and a drain of the MOS transistor M25, the source of the MOS transistor M25 is connected to a power supply terminal, the gate and the drain of the MOS transistor M25 are shorted, the gate of the MOS transistor M25 and the gate of the MOS transistor M25 are connected, the source and the drain of the MOS transistor M25 are respectively connected to the power supply terminal and the drain of the MOS transistor M25, the gate of the MOS transistor M25 and the drain of the MOS transistor M25 are connected to another source of the MOS transistor M25, the third resistor and the drain of the MOS transistor M25 are connected to another source of the MOS transistor M25, and the MOS transistor 25.

Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows:

1. the hysteresis voltage does not contain parameters related to a process angle, the temperature coefficient of the resistor is eliminated, the band gap reference voltage basically does not change along with the process and the temperature, and the hysteresis voltage can be ensured to be unrelated to the process parameters and the temperature only by matching a small number of resistors and matching input geminate transistors of a comparator (any precise comparator can be matched);

2. if adopt N accurate hysteresis comparator in the chip, traditional accurate hysteresis voltage comparator needs 2N reference voltage, and hysteresis voltage's size often is not fixed proportion with the reference voltage of comparator in practical application, in order to realize output voltage's precision, every divider resistance must guarantee to match, this brings very big degree of difficulty to resistance voltage division, the circuit of this application only needs N reference voltage division and becomes fixed proportion basically, the partial pressure degree of difficulty that reduces reference voltage greatly

3. The circuit can realize the hysteresis voltage with any size by setting different current mirror image proportionality coefficients and the width-length ratio of the hysteresis MOS tube; therefore, the problem that the reference voltage divider resistors are difficult to match due to the fact that a plurality of small hysteresis voltages are achieved by a traditional precise hysteresis comparator is solved.

4. Compared with a traditional accurate comparator, the circuit does not add a switching tube at the reference voltage input end of the comparator, so that the influence of charge injection of the switching tube on the reference voltage when the comparator is turned over is eliminated, and the accuracy of the reference voltage for other purposes is ensured.

Drawings

Fig. 1 is a schematic structural diagram of the hysteresis voltage comparator of the present invention.

Fig. 2 is a schematic diagram of a circuit structure of the bias current generating module of the present invention.

Fig. 3 is a schematic diagram of a circuit structure of the comparator module according to the present invention.

Fig. 4 is a schematic diagram of a circuit structure of the middle adjustable reference voltage generating module of the present invention.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in detail below in with reference to the accompanying drawings and embodiments.

Embodiment 1 as shown in fig. 1, hysteresis voltage comparators comprise an adjustable reference voltage generating module, a bias current generating module and a comparator module;

the adjustable reference voltage generating module generates th current I₁Said current I at th₁The current flows into end of a third resistor R3 of the adjustable reference voltage generating module, the other end of the third resistor R3 is connected with a power supply end, end of the third resistor R3 forms a voltage point V_R3；

As shown in fig. 2, the bias current generating module includes a drain voltage clamp circuit, a MOS transistor M20, a MOS transistor M19, a th current mirror, and a second current mirror, the drain voltage clamp circuit includes an operational amplifier a1, a th resistor, a second resistor, a MOS transistor M15, a MOS transistor M16, a MOS transistor M17, and a MOS transistor M18, and a drain current I of the MOS transistor M20₂Drain current I of MOS transistor M19₃And current I at ₁Equally, a end of the second resistor R2 is connected to a power supply end, another end of the second resistor R2 is connected to a drain of the MOS transistor M20 and a gate of the MOS transistor M18, a source and a drain of the MOS transistor M18 are connected to the power supply end and a source of the MOS transistor M17, a drain of the MOS transistor M17 is connected to drains of the th current mirror, the th current mirror includes the MOS transistor M14 and the MOS transistor M13, the second current mirror includes the MOS transistor M12 and the MOS transistor M11, and a drain of the MOS transistor M17 (the current is I) is connected to a drain of the MOS transistor M17₄) The drain electrode of the MOS tube M14 is connected, the grid electrodes of the MOS tube M14 and the MOS tube M13 are connected, the grid electrode and the drain electrode of the MOS tube M14 are in short circuit, and the output end of the operational amplifier A1The input end of the operational amplifier a1 is connected with a voltage point formed by the adjustable reference voltage generating module and the source of the MOS transistor M17, the end of the th resistor R1 is connected with a power supply end, the other end of the th resistor R1 is respectively connected with the drain of the MOS transistor M19 and the gate of the MOS transistor M16, the source and the drain of the MOS transistor M16 are respectively connected with the power supply end and the source of the MOS transistor M15, and the drain of the MOS transistor M15 (the current is I)₅) Respectively connected with the drain electrodes of the MOS tubes M13 (the current is I)₆) And the drain electrode of the second current mirror MOS transistor M13 (the current is I)₇) The MOS transistor M12 and the MOS transistor M11 are connected with each other by a grid, the MOS transistor M12 is in short circuit with a grid and a drain, the MOS transistor M14, the MOS transistor M13, the MOS transistor M12 and the MOS transistor M11 are connected with the source of the MOS transistor M19 and the source of the MOS transistor M20, and the drain current of the MOS transistor M11 is the generated bias current I₈The th current mirror has a mirror image proportionality coefficient of 1:1, and the second current mirror has a mirror image proportionality coefficient of 1: k;

the comparator module comprises transistor pair transistors, and the grids of the MOS transistor pair transistors are respectively connected with an input voltage end V_INAnd a reference voltage terminal V_REFThe scheme of the embodiment does not need two reference voltages, the bias current is used as tail current of a comparator, so that the temperature coefficient and the process parameter caused by the added hysteresis voltage generated by the MOS tube are eliminated, accurate hysteresis voltage is realized, the hysteresis voltage does not change along with the change of temperature and process angle, the tail current is mirrored through the current mirrors with different coefficients to be used as tail current for a plurality of comparators, and the comparator with any different accurate hysteresis voltage can be realized by changing the width-length ratio of the MOS tubes input by different comparators, so that the matching and comparison are simple, and only N reference voltages are needed.

Example 2: on the basis of embodiment 1, as shown in fig. 3, the comparator module includes a pair transistor formed by a MOS transistor M6, a MOS transistor M5, a MOS transistor M2 and a MOS transistor M1A third current mirror composed of a MOS tube M3 with a switching tube M4, a MOS tube M9 and a MOS tube M10, a MOS tube M7 and a MOS tube M8, wherein the bias current is connected with the drain of the MOS tube M10, the source of the MOS tube M10 is connected with a power supply end, the MOS tube M9 is connected with the gate of the MOS tube M10, the mirror proportionality coefficient of the third current mirror in the embodiment is 1:2, the source of the MOS tube M9 is connected with the power supply end, the drain of the MOS tube M9 is connected with the sources of the MOS tube M3, the MOS tube M2 and the MOS tube M1, and the gates of the MOS tube M2 and the MOS tube M1 are respectively connected with an input voltage end V1_INAnd a reference voltage terminal V_REFThe drains of the MOS transistors M2 and M1 are respectively connected to the drains of the MOS transistors M6 and M5, the sources of the MOS transistors M6 and M5 are connected to the sources of the MOS transistors M19 and M20, the gates of the MOS transistors M6 and M5 are connected, the gate and the drain of the MOS transistor M5 are shorted, the gate of the MOS transistor M3 is connected to the input voltage terminal, the drain of the MOS transistor M3 is connected to the source of the switching transistor M4, the drain of the switching transistor M4 is connected to the gate of the MOS transistor M5, the gate of the switching transistor M4 is connected to the output voltage terminal, the drain of the MOS transistor M6 is connected to the gate of the MOS transistor M7, the source and the gate of the MOS transistor M8 are respectively connected to the power supply terminal and the bias current, the source of the MOS transistor M7 is connected to the sources of the MOS transistors M19 and M20, and the drains of the MOS transistors M7 and M8 are connected to the output voltage terminal,

the MOS tube pair transistors adopt PMOS input pair transistors or dual NMOS input pair transistors.

Embodiment 3, based on embodiment 2, as shown in fig. 4, the adjustable reference voltage generating module includes: operational amplifier A0, MOS pipe M21, MOS pipe M22, MOS pipe M23, MOS pipe M24, MOS pipe M25, third resistor R3 and fourth resistor R4, wherein the input end of the operational amplifier A0 is connected with the divided voltage V of the reference voltage_RAnd a source of a MOS tube M25, an output end of the operational amplifier A0 is connected with a grid of a MOS tube M25, a source and a drain of the MOS tube M25 are respectively connected with a end of a fourth resistor R4 and a drain of the MOS tube M24, a source of the MOS tube M24 is connected with a power supply end, a grid and a drain of the MOS tube M24 are in short circuit, grids of the MOS tube M24 and the MOS tube M23 are connected, a source and a drain of the MOS tube M23 are respectively connected with a power supply end and a drain of the MOS tube M22, grids of the MOS tube M22 and the MOS tube M21 are connected, and a grid of the MOS tube M21 isThe grid and the drain of the MOS transistor M22 are in short circuit, the grid of the MOS transistor M22 is connected with the grids of the MOS transistor M19 and the MOS transistor M20, the sources of the MOS transistor M22 and the MOS transistor M21 are connected with the other end of the fourth resistor R4 and are simultaneously connected with the sources of the MOS transistor M19 and the MOS transistor M20, and the drain current of the MOS transistor M21 is the current I of the fourth transistor M ₁And is connected with a power supply end after being connected with a third resistor R3, and a voltage point V is formed between the MOS tube M21 and the third resistor R3_R3. In the structure of this embodiment, the different reference voltages V can be realized by changing the mirror proportionality coefficients of the current mirror MOS transistor M21 and the MOS transistor M22, the mirror proportionality coefficients of the current mirror MOS transistor M23 and the MOS transistor M24, and changing the resistances of the resistors R1, R2 and R3_R3。

The solution of the above embodiment employs a divided voltage V using a reference voltage_RThe current I is generated by an operational amplifier A0₁＝V_R/R₄And I is₁＝I₂＝I₃The drain and source voltages of M18 and M16 are then clamped by operational amplifier a 1:

V_DS18＝V_DS16＝I₁*R₃

the gate-to-source voltage difference of M18 is: v_GS18＝I₂*R₂

The gate-to-source voltage difference of M16 is: v_GS16＝I₃*R₁

In this embodiment, the width-to-length ratios of M18 and M16 are set equal and matched so that the threshold voltages of M18 and M16 are equal:

V_GS18＝V_GS16

W₁₈/L₁₈＝W₁₆/L₁₆

this example regulates V_GS18And V_GS16The M18 and M16 are both operated in the deep linear region, and the current I of M16₈I greater than M18₆Setting the width-to-length ratio of M17 to M15 to make the VGS difference between them due to different current magnitudes negligible, if necessary, operational amplifiers can be added separately to clamp the drain voltage of M15, so as to obtain I₈The current magnitude of (a) is:

wherein, mu_pFor hole mobility, C_oxIs the gate oxide capacitance per unit area, t_oxIs the oxide layer thickness.

The current I₈The width-length ratio of the current mirrors M10 and M9 is set to be 1:2 as the bias current of the hysteresis comparator, the width-length ratio of the input pair transistors M2 and M3 is equal: w₂/L₂＝W₁/L₁

When the output of the comparator is low and the hysteresis MOS transistor M3 is not added, the condition that the comparator is overturned is that the current I of M6_DM6Current I with M5_DM5Equal to I, equal to I₈It must be ensured that the M1, M2 and M3 of the inlet pipes all operate in the saturation region.

When the comparator is turned over:

I_DM6＝I_DM5＝I₈

V_IN＝V_REF

when the comparator is inverted, that is, the output is high, the hysteresis MOS transistor M3 is added through the switching transistor M4, and the inversion voltage at this time is:

the hysteresis voltage of the circuit is therefore:

the whole formula does not comprise parameters related to temperature, the parameters related to process angle parameters are also eliminated through matching, so that a comparator for accurately delaying voltage is realized, and I is converted into I through different current mirrors₇And the mirror image is sent to input pair tube comparators with different width-length ratios, so that a plurality of comparators with different sizes and accurate hysteresis voltages can be realized.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

The hysteresis voltage comparators are characterized by comprising an adjustable reference voltage generation module, a bias current generation module and a comparator module;

the adjustable reference voltage generating module generates th current, the th current flows into a terminal of a third resistor of the adjustable reference voltage generating module, the other terminal of the third resistor is connected with a power supply terminal, and a terminal of the third resistor forms a voltage point;

the bias current generating module comprises a drain voltage clamping circuit, a MOS transistor M20, a MOS transistor M19, a th current mirror and a second current mirror, the drain voltage clamping circuit comprises an operational amplifier a1, a th resistor, a second resistor, a MOS transistor M15, a MOS transistor M16, a MOS transistor M17 and a MOS transistor M18, drain currents of the MOS transistor M20 and the MOS transistor M19 are equal to a current of an 0, an 1 end of the second resistor is connected with a power supply end, another 2 end of the second resistor is connected with a drain of the MOS transistor M20 and a gate of the MOS transistor M18, a source and a drain of the MOS transistor M18 are respectively connected with the power supply end and a source of the MOS transistor M18, a drain of the MOS transistor M18 is connected with 18 drains of the current mirror 18 th current mirror, an output end of the operational amplifier a 18 is connected with the drains of the MOS transistor M18 and the gate of the MOS transistor M18, an adjustable drain voltage of the operational amplifier a drain of the operational amplifier a transistor M18 is connected with the drain current of the drain of the second transistor M18, a drain voltage clamping circuit, a drain voltage generating source of the second transistor M18, a drain voltage of the second transistor M18 and a drain voltage generating module 18, a drain voltage of the drain of the transistor M18, a drain voltage, a drain of the transistor M18, a drain voltage generating module is connected with a drain of the transistor M18, a drain voltage generating a drain current, a drain voltage, a drain of the transistor M18, a drain voltage;

the comparator module comprises a transistor pair transistor, the grid electrodes of the MOS transistor pair transistor are respectively connected with an input voltage end and a reference voltage end, MOS transistors M3 are arranged at the MOS transistor pair transistor through switching tubes to generate hysteresis voltage, and the bias current generates mirror current through a third current mirror and is input to the source electrode of the MOS transistor M3.
2. The hysteretic voltage comparator of claim 1, wherein the mirror ratio of the second current mirror is adjustable.
3. The hysteretic voltage comparator as claimed in claim 1, wherein said comparator module comprises a pair of MOS transistor M6 and MOS transistor M5 and MOS transistor M2 and MOS transistor M1, a third current mirror consisting of MOS transistor M3 with switch M4, MOS transistor M9 and MOS transistor M9, said bias current being connected to the drain of MOS transistor M9, the source of MOS transistor M9 being connected to a power supply terminal, the gates of MOS transistor M9 and MOS transistor M9 being connected to a power supply terminal, the source of MOS transistor M9 being connected to the power supply terminal, the drain of MOS transistor M9 being connected to the drains of MOS transistor M9, MOS transistor M9 and MOS transistor M9, the gates of MOS transistor M9 and MOS transistor M9 being connected to an input voltage terminal and a reference voltage terminal, the drains of MOS transistor M9 and MOS transistor M9 being connected to the drains of MOS transistor M9 and MOS transistor M9, the source of MOS transistor M9 being connected to the drain of MOS transistor M9 and the source of MOS transistor M9, and the drain of MOS transistor M9 being connected to the source of the MOS transistor M9, the grid and the drain of MOS pipe M5 short circuit, the grid of MOS pipe M3 is connected with the input voltage end, the drain of MOS pipe M3 is connected with the source of switch pipe M4, the drain of switch pipe M4 is connected with the grid of MOS pipe M5, the grid of switch pipe M4 is connected with the output voltage end, the drain of MOS pipe M6 is connected with the grid of MOS pipe M7, the source and the grid of MOS pipe M8 are connected with a power supply end and a bias current respectively, the source of MOS pipe M7 is connected with the sources of MOS pipe M19 and MOS pipe M20, and the drains of MOS pipe M7 and MOS pipe M8 are connected with the output voltage end.
4. The hysteretic voltage comparator of claim 3, wherein the aspect ratio of MOS transistor M9 and MOS transistor M10 in the third current mirror is adjustable.
5. The hysteretic voltage comparator as claimed in claim 3, wherein the MOS pair transistors are PMOS input pair transistors or dual NMOS input pair transistors.
6. The hysteresis voltage comparator as claimed in claim 3, wherein the adjustable reference voltage generating module comprises an operational amplifier A0, a MOS transistor M21, a MOS transistor M22, a MOS transistor M23, a MOS transistor M24, a MOS transistor M25, a third resistor and a fourth resistor, an input end of the operational amplifier A0 is connected with the divided voltage of the reference voltage and a source of the MOS transistor M25, an output end of the operational amplifier A0 is connected with a gate of the MOS transistor M25, a source and a drain of the MOS transistor M25 are respectively connected with a 25 end of the fourth resistor and a drain of the MOS transistor M25, a source of the MOS transistor M25 is connected with a power supply terminal, a gate and a drain of the MOS transistor M25 are shorted, a gate of the MOS transistor M25 and a gate of the MOS transistor M25 are connected, a source and a drain of the MOS transistor M25 are respectively connected with the power supply terminal and the drain of the MOS transistor M25, a gate of the MOS transistor M25 and a drain of the MOS transistor M25 are connected with a drain of the MOS transistor M25, a drain of the MOS transistor M25 and a drain of the MOS transistor M25 is connected with a drain of the MOS transistor M25, a drain of the.