CN209946378U

CN209946378U - FPGA system for processing Doppler laser frequency shift signal

Info

Publication number: CN209946378U
Application number: CN201920707460.6U
Authority: CN
Inventors: 张亚妮; 刘茹; 吴圣博
Original assignee: Shaanxi University of Science and Technology
Current assignee: Shaanxi University of Science and Technology
Priority date: 2019-05-17
Filing date: 2019-05-17
Publication date: 2020-01-14
Anticipated expiration: 2029-05-17

Abstract

The utility model discloses a handle FPGA system of doppler laser frequency shift signal relates to optic fibre and laser measuring equipment technical field, including power supply circuit, download circuit, serial control circuit and reset circuit, serial control circuit uses the FPGA chip as control core. The utility model discloses a to the high-speed instant processing of low intermediate frequency band Doppler frequency shift signal, the data are received to the multiple serial ports, and stable accurate processing data has simple structure, design flexibility, stable performance, advantage such as with low costs.

Description

FPGA system for processing Doppler laser frequency shift signal

Technical Field

The utility model relates to an optic fibre and laser measuring equipment technical field, in particular to handle FPGA system of doppler laser frequency shift signal.

Background

The laser Doppler effect is that when the light source and the moving object move relatively, the light scattered from the moving object will produce Doppler shift, and the amount of the shift is related to the speed, incident light and speed direction of the moving objectThe included angles are all related. The frequency of the laser is v, and the velocity of the moving object is u, then the amount of doppler shift generated by the motion of the object can be expressed as:

in the formula: e.g. of the type_oIs a unit vector of incident light, e_sIs the unit vector of the scattered light, and c is the speed of light. Therefore, the Doppler frequency shift signal has a unique time-frequency corresponding relation, mainly low and middle frequency band signals, and the speed information of the moving object is obtained by measuring the value of the laser Doppler frequency shift.

Programmable Logic Devices (PLDs) set Logic function integrated circuits by Programmable functions in a system at the request of a user. The best field programmable Gate Array (Fieldprogrammable Gate Array) makes up the defects that the customization circuit is long in period, high in cost and not easy to modify after being manufactured. With the continuous maturity of programmable logic technology, FPGA chips have been widely used in the fields of communication, aerospace, medical electronics, industrial control, and the like. The resources contained in the FPGA chip are more and more abundant, and the realizable functions are more and more, which makes the FPGA occupy more and more important position in the electronic circuit design. However, a single FPGA chip is generally adopted to receive and process data, and the FPGA chip has the defects of limited operating efficiency and unstable performance. There is therefore a need for improvements.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a handle FPGA system of doppler laser frequency shift signal, receive the limited problem of processing data operating efficiency and design for solving ordinary single FPGA chip, use FPGA to control the core, entire system divides can be power supply circuit, download circuit, serial control circuit, the reset circuit four bibliographic categories divides, the realization is to the high-speed instant processing of low-intermediate frequency band doppler frequency shift signal, the multiple serial ports received data, stable accurate processing data, simple structure has, the design is nimble, stable performance, advantages such as with low costs.

The embodiment of the utility model provides a handle FPGA system of Doppler laser frequency shift signal, including power supply circuit, download circuit, serial control circuit and reset circuit, power supply circuit is connected with download circuit, serial control circuit and reset circuit electricity respectively, download circuit and reset circuit all are connected with the serial control circuit electricity.

The embodiment of the utility model provides a pair of handle FPGA system of doppler laser frequency shift signal has following advantage:

1. the utility model provides a novel FPGA system design for processing Doppler laser frequency shift signals, which aims to solve the problem that the prior common single FPGA chip has limited operating efficiency of receiving and processing data, the FPGA is taken as a control core, the whole system design can be divided into four parts, namely a power circuit, a download circuit, a serial control circuit and a reset circuit, so as to realize high-speed instant processing of Doppler frequency shift signals in low and middle frequency bands, and the data is received by multiple serial ports and is stably and accurately processed;

2. the utility model has the advantages of simple structure, design are nimble, stable performance, with low costs, but signal processing such as wide application in optical fiber measurement light filtering, gain smoothness and in numerous fields such as medical science, biology, space flight.

Drawings

Fig. 1 is a schematic diagram of module connection of an FPGA system for processing doppler laser frequency shift signals according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of the power circuit of FIG. 1;

FIG. 3 is a schematic diagram of the download circuit of FIG. 1;

FIG. 4 is a schematic diagram of the serial control circuit of FIG. 1;

fig. 5 is a schematic diagram of the reset circuit of fig. 1.

Detailed Description

In the following, an embodiment of the present invention will be described in detail with reference to the drawings, but it should be understood that the scope of the present invention is not limited by the embodiment.

Referring to fig. 1, the utility model provides a handle FPGA system of doppler laser frequency shift signal, this system include power supply circuit, download circuit, serial control circuit and reset circuit, power supply circuit is used for supplying power to other circuits, download circuit is used for leading-in serial control circuit with the doppler frequency shift signal, serial control circuit is used for comparing the calculation to the doppler frequency shift signal, reset circuit is used for maintaining the stable work of entire system. The power supply circuit is respectively and electrically connected with the download circuit, the serial control circuit and the reset circuit, and the download circuit and the reset circuit are both electrically connected with the serial control circuit. The power circuit, the download circuit, the serial control circuit and the reset circuit can be connected by wires, and the whole circuit can be kept unchanged and marked into an integrated circuit.

Referring to fig. 2, the power circuit includes an SMA radio frequency connector and a voltage stabilizing circuit. The nut port of the SMA radio frequency connector is arranged on a wire in a compression joint mode, a +5V power supply is connected in series with the wire, and a pin 1 of the SMA radio frequency connector is reserved for receiving laser Doppler frequency shift signals, so that a stable electrical performance and environment protection device is provided, the working efficiency is improved, and the space of the device is reduced as much as possible. The radio frequency front end of the SMA radio frequency connector plays a key role in an electronic communication system, and the functions of the SMA radio frequency connector comprise radio frequency power amplification, narrow band filtering, up-down frequency conversion and the like. The voltage stabilizing circuit comprises a voltage stabilizer U1 and peripheral devices, a pin IN of a voltage stabilizer U1 is connected with a 5V power supply, a pin OUT outputs a converted 3.3V power supply, a pin GND is grounded, the pin IN and the GND are connected through capacitors C1 and C2 which are connected IN parallel, the pin OUT is grounded through capacitors C3 and C4 which are connected IN parallel, meanwhile, the pin OUT is grounded through a resistor R1 and a light emitting diode LED1 which are connected IN series, and the 3.3V power supply output by the pin OUT is subjected to voltage reduction through a resistor R1 and then outputs a 2.5V power supply. The regulator U1 may be model LM 2596.

Referring to fig. 3, the download circuit includes a JTAG chip and peripheral devices, the model of the JTAG chip is JLINKV9, the doppler shift signal is introduced by the download circuit, a TAP (test access port) is defined inside the JTAG chip, and the test can be completed while the online programming is performed. And a serial shift register can be used in the download circuit, so that each unit of the serial shift register is distributed to a corresponding pin of the JTAG chip, the boundary scanning register function is realized, and the data at each moment can be integrally and orderly stored in the JTAG chip to wait for subsequent processing. And a pin TCK of the JTAG chip is a test clock input pin, a pin TDI is a test data input pin, a pin TDO is a test data output pin, and a pin TMS is a test mode selection pin, and can be directly connected with a 2.5V power supply. Pin TCK is grounded through resistor R2, pin GND is grounded, pin VCC is connected to the 2.5V power supply output by the power supply circuit, pins TMS and TDI are connected to the 2.5V power supply output by the power supply circuit through resistors R3 and R4, and pin TDI is also connected to the SMA radio frequency connector in the power supply circuit to transmit the unprocessed doppler shift signal.

Referring to fig. 4, the serial control circuit includes an FPGA chip U2 and peripheral devices, and the model of the FPGA chip U2 is EPCS64SI 16N. The serial control circuit enables data downloading and data processing to be carried out simultaneously, pins VCC of the FPGA chip U2 are all connected to a 3.3V power supply output by a power supply circuit, pins GND are grounded, a 16-pin small-outline integrated circuit package is provided, a serial data interface pin ASDI is connected with a pin TDO of a JTAG chip, and each bit of a data word and corresponding data are sequentially transmitted to the kernel through a single channel. When the pin ASDI is at a high level, the external configuration provides a reference clock signal, the data signal is compared with the clock signal to realize frequency counting, and a frequency value is calculated by using a mathematical formula. The frequency period measurement adopts an equal-precision frequency measurement method to measure the frequency, different gate time is set for different frequency sections, parallel multipath counting of the FPGA chip U2 is utilized, under the control of providing a reference clock signal (or clock frequency provided by a 50M active crystal oscillator) as a gate signal by external configuration, the signal to be measured and the reference signal are counted, and then the frequency of the signal to be measured can be obtained through certain multiplication and division operation. Taking a signal to be detected as an example, when the rising edge of the signal fx to be detected comes, the reset circuit is connected to the nCS pin of the FPGA chip U2 and is placed at 0, and the NC pin nCS pin of the FPGA chip U2 is cleared. When the reset circuit is set to 1, the NC pin nCS starts to work normally, when the gate signal is set to 1, the kernel counter of the FPGA chip U2 starts to count, and when the gate signal is set to 0, the counting is not performed. Pin DATA of the FPGA chip U2 is connected to pin TDO of the JTAG chip to input a doppler shift signal.

Referring to fig. 5, the reset circuit includes a switch KEY1, a resistor R5 and a capacitor C5, after the switch KEY1 and the capacitor C5 are connected in parallel, one end of the switch KEY1 is connected to a 3.3V power supply output by the power circuit through a resistor R5, the other end of the switch KEY1 is grounded, and a connection point between the switch KEY1 and the resistor R5 is further connected to a pin nCS of the FPGA chip U2. The reset circuit is used for ensuring the stable and reliable work of the whole system, can carry out reset operation immediately when the circuit is electrified, and can carry out manual operation when necessary or automatically carry out operation according to the requirements of programs or circuit operation. When the reset circuit is powered on, the capacitor C5 is charged, and high potential voltage appears on the resistor R5, so that the FPGA chip U2 is reset; after a few milliseconds, the capacitor C5 is full, the current on the resistor R5 is reduced to 0, the voltage is also 0, and the FPGA chip U2 enters an operating state. In a working state, the switch KEY1 is pressed, the capacitor C5 discharges, and after the discharge is finished, voltage appears on the resistor R5, so that the FPGA chip U2 enters a reset state; until the switch KEY1 is turned off and the capacitor C5 is charged, the FPGA chip U2 enters the operating state again.

The power circuit, the download circuit, the serial control circuit and the reset circuit can all work as local systems and can realize the processing of Doppler frequency shift signals after being connected in a proper mode. The system may also be connected to a 50M active crystal oscillator, such as a square crystal oscillator, which is marked with a few 1 pins, and the remaining counterclockwise (pins down) are marked with 2, 3, 4 pins. The pin 1 is suspended, the pin 2 is grounded, and the pin 3 is an output end and can be connected with a pin TCK of a JTAG chip in the download circuit and a pin DCLK of an FPGA chip U2 in the serial control circuit; the 4-pin 5V power supply is connected, so that the clock frequency required by the FPGA chip U2 is generated, and all parts of the system are kept synchronous.

The utility model discloses a FPGA system can realize the high-speed instantaneous processing to low intermediate frequency band Doppler frequency shift signal, and the data is received to the multiple serial ports, and stable accurate processing data has simple structure, design flexibility, stable performance, advantage such as with low costs, but wide application in signal processing such as optical line filtering, gain smoothness and in numerous fields such as medical science, biology, space flight in the fiber measurement.

The above disclosure is only for a few specific embodiments of the present invention, however, the present invention is not limited to the embodiments, and any changes that can be considered by those skilled in the art shall fall within the protection scope of the present invention.

Claims

1. The FPGA system for processing the Doppler laser frequency shift signal is characterized by comprising a power supply circuit, a downloading circuit, a serial control circuit and a reset circuit, wherein the power supply circuit is electrically connected with the downloading circuit, the serial control circuit and the reset circuit respectively, and the downloading circuit and the reset circuit are both electrically connected with the serial control circuit.

2. The FPGA system for processing Doppler laser frequency shift signals according to claim 1, wherein the power circuit comprises an SMA radio frequency connector and a voltage stabilizing circuit, the SMA radio frequency connector port is mounted on a wire IN a crimping manner and connected with a +5V power supply IN series, a pin 1 of the SMA radio frequency connector receives the laser Doppler frequency shift signals, the voltage stabilizing circuit comprises a voltage stabilizer U1, the voltage stabilizer is LM2596, a pin IN of the voltage stabilizer is connected with the 5V power supply, a pin OUT outputs a converted 3.3V power supply, and a 3.3V power supply output by the pin OUT outputs a 2.5V power supply after being reduced IN voltage through a resistor R1.

3. The FPGA system of claim 2, wherein the download circuit comprises a JTAG chip having a model number of JLINK V9, wherein a pin VCC of the JTAG chip is connected to the 2.5V power supply output by the power circuit, pins TMS and TDI are connected to the 2.5V power supply output by the power circuit through resistors R3 and R4, respectively, and pin TDI is connected to an SMA RF connector in the power circuit.

4. The FPGA system for processing Doppler laser frequency shift signals as recited in claim 3, wherein the serial control circuit comprises an FPGA chip U2, the model of the FPGA chip U2 is EPCS64SI16N, a pin VCC thereof is connected to a 3.3V power supply output by the power supply circuit, the reset circuit is connected to a pin nCS of the FPGA chip U2, and a pin DATA of the FPGA chip U2 is connected to a pin TDO of the JTAG chip.

5. The FPGA system for processing Doppler laser frequency shift signals according to claim 4, wherein the reset circuit comprises a switch KEY1, a resistor R5 and a capacitor C5, the switch KEY1 and the capacitor C5 are connected in parallel, one end of the switch KEY1 is connected with a 3.3V power supply output by the power circuit through a resistor R5, and a connection point between the switch KEY1 and the resistor R5 is connected to a pin nCS of the FPGA chip U2.

6. The FPGA system for processing Doppler laser frequency shift signals according to claim 4, further comprising a 50M active crystal oscillator, wherein the output terminal of the crystal oscillator is connected to the TCK pin of the JTAG chip in the download circuit and the DCLK pin of the FPGA chip U2 in the serial control circuit.