CN209897029U - Delay circuit and semiconductor device including the same - Google Patents
Delay circuit and semiconductor device including the same Download PDFInfo
- Publication number
- CN209897029U CN209897029U CN201920713086.0U CN201920713086U CN209897029U CN 209897029 U CN209897029 U CN 209897029U CN 201920713086 U CN201920713086 U CN 201920713086U CN 209897029 U CN209897029 U CN 209897029U
- Authority
- CN
- China
- Prior art keywords
- delay
- group
- cells
- locked loop
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 230000003111 delayed effect Effects 0.000 description 38
- 238000010586 diagram Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000000872 buffer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 1
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
Images
Landscapes
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model discloses a delay circuit and semiconductor device including this delay circuit. The delay circuit includes: a first delay locked loop including a first delay chain connected to the clock signal input and formed of a first set of delay cells; and a second delay locked loop including a second delay chain connected to the clock signal input terminal and composed of a second group of delay units and a third group of delay units connected to each other, wherein a first delay time of a first delay signal output by the first group of delay units, a second delay time of a second delay signal output by the second group of delay units, and a third delay time of a third delay signal output by the third group of delay units are different from each other, and the first delay time is greater than the third delay time. Through the technical scheme provided by the utility model, can reduce the delay time difference between the delay signal that different delay locked loop output.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to a delay circuit and a semiconductor device including the same.
Background
The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
A time-to-digital converter (TDC) based on the vernier method can achieve a quantized time accuracy smaller than the delay time of a gate circuit, and thus, it is widely used in a high-accuracy time measurement system. The basic principle of the TDC based on the vernier method is shown in fig. 1, and the time difference between the two clock signals is (n1-n2) × T1+ n2 × (T1-T2), where T1 and T2 are periods of the first clock signal and the second clock signal, respectively, and T1 is greater than T2, and n1 and n2 are counts when the phases of the two clock signals coincide, respectively. Both clock signals can be realized by delay circuits.
The prior art delay circuit generally includes a fast Delay Locked Loop (DLL), a slow DLL, a Phase Frequency Detector (PFD), a Charge Pump (CP), and the like, as shown in fig. 2. Wherein the fast DLL and the slow DLL each include a same plurality of delay cells that can be used to generate corresponding delay signals from a received clock signal. The PFD may be used to determine a frequency/phase difference between a delay signal output from a delay cell in a fast DLL and a slow DLL and a clock signal (CLK), and control the CP to adjust a reference voltage VCTRLFAnd VCTRLSAnd adjusting the delay time of the delay unit until the clock signal and the delayed signal reach the same frequency and phase, i.e. forming a lock, at which time the reference voltage VCTRLFAnd VCTRLSAnd remain constant. When both the fast DLL and the slow DLL are locked, the delay time difference between the delay signals outputted from the fast DLL and the slow DLL is
Wherein, TSAnd TFDelay times, T, of the delay cell outputs in the slow DLL and the fast DLL, respectivelyCLKN is the number of delay units for the period of the clock signal.
In the process of implementing the present invention, the inventor finds that there are at least the following problems in the prior art:
in order to reduce the delay time difference, the number of delay units is usually increased, which occupies a larger chip area. Furthermore, since the delay unit has a minimum delay time due to factors such as an integrated circuit manufacturing process, the difficulty of the integrated circuit manufacturing process is increased if the minimum delay time difference is realized.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a delay circuit to reduce the delay time difference between the delay signal that different delay locked loop output.
In order to solve the above technical problem, the present invention provides a delay circuit, which may include:
a first delay locked loop including a first delay chain connected to the clock signal input and formed of a first set of delay cells; and
a second delay locked loop comprising a second delay chain of interconnected second and third sets of delay cells connected to the clock signal input,
wherein, a first delay time of a first delay signal output by the first group of delay units, a second delay time of a second delay signal output by the second group of delay units and a third delay time of a third delay signal output by the third group of delay units are different, and the first delay time is greater than the third delay time.
Optionally, the first delay locked loop further comprises a first voltage generating circuit, a first voltage output of which is connected in parallel with the first input of the first group of delay cells, and a first feedback signal input of which is connected with the delay signal output of a first delay cell of the first group of delay cells located at the end of the first delay chain;
the second delay locked loop further comprises a second voltage generating circuit and a third voltage generating circuit, wherein a second voltage output terminal of the second voltage generating circuit is connected in parallel with the first input terminal of the second group of delay cells, and a second feedback signal input terminal thereof is connected with a delay signal output terminal of a third delay cell of the third group of delay cells, which is located at the end of the second delay chain; and a third voltage output end of the third voltage generating circuit is connected with the first input end of the third group of delay units.
Optionally, the third voltage generating circuit comprises a fixed voltage generating circuit or an adjustable voltage generating circuit.
Optionally, the fixed voltage generating circuit includes a bias voltage supply terminal of the delay circuit.
Optionally, when only one third delay cell is included in the third group of delay cells or the plurality of third delay cells included therein are all the same, the adjustable voltage generating circuit includes a third delay locked loop including a third delay chain composed of a fourth group of delay cells and a fourth voltage generating circuit, and a fourth voltage output terminal of the fourth voltage generating circuit is connected in parallel with the first input terminal of the fourth group of delay cells and the first input terminal of the third group of delay cells, and a fourth feedback signal input terminal thereof is connected with the delay signal output terminal of a fourth delay cell located at the end of the third delay chain among the fourth group of delay cells.
Optionally, when only one third delay unit is included in the third group of delay units or the plurality of third delay units included in the third group of delay units are the same, the adjustable voltage generation circuit includes a fourth delay locked loop to an mth delay locked loop which are connected in sequence, and a delay time of a delay signal generated by each of the fourth delay locked loop to the mth delay locked loop is controlled by a reference voltage generated by a next delay locked loop connected to the fourth delay locked loop, where M is a positive integer greater than 4.
Optionally, the fourth to M-1 th delay locked loops each include a delay chain composed of two groups of delay cells connected in series and a voltage generation circuit for supplying a reference voltage to one of the two groups of delay cells, and the reference voltage of the other of the two groups of delay cells is supplied by the voltage generation circuit in the next delay locked loop connected thereto.
Optionally, when the third group of delay cells includes a different plurality of third delay cell groups, the adjustable voltage generation circuit includes a plurality of delay locked loops corresponding to the plurality of third delay cell groups, and each of the plurality of delay locked loops includes a delay chain made up of a group of delay cells and a voltage generation circuit for providing a third reference voltage to the group of delay cells and the corresponding third delay cell group.
Optionally, when the third group of delay cells includes a plurality of different third delay cell groups, the adjustable voltage generation circuit includes a plurality of groups of delay locked loops corresponding to the plurality of third delay cell groups, and each group of the delay locked loops includes a plurality of delay locked loops connected in sequence, and a delay time of a delay signal generated by each of the plurality of delay locked loops is controlled by a reference voltage generated by a next delay locked loop connected thereto.
The utility model also provides a semiconductor device, this semiconductor device can include above-mentioned delay circuit.
By the above the technical scheme the utility model provides a it is visible, the utility model discloses can be through realizing the delay unit in the different delay locked loop for having different delay time to can reduce the delay time difference between the delay signal that different delay locked loop exported, and then can reduce shared chip resource.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings required for the description of the present invention or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of a prior art vernier based TDC;
FIG. 2 is a schematic diagram of a prior art delay circuit;
fig. 3 is a schematic structural diagram of a delay circuit provided in the present invention;
fig. 4 is a schematic structural diagram of a delay circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a first voltage generation circuit;
FIG. 6 is a schematic diagram of a second voltage generation circuit;
fig. 7 is a schematic structural diagram of another delay circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another delay circuit according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another delay circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are only used for explaining some embodiments of the present invention, but not all embodiments, and are not intended to limit the scope of the present invention or the claims. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected/coupled" to another element, it can be directly connected/coupled to the other element or intervening elements may also be present. The term "connected/coupled" as used herein may include electrical and/or mechanical physical connections/couplings. The term "comprises/comprising" as used herein refers to the presence of features, steps or elements, but does not preclude the presence or addition of one or more other features, steps or elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
In addition, in the description of the present invention, the terms "first", "second", "third", and the like are used for descriptive purposes only and to distinguish similar objects, and there is no order of precedence between the two, and no indication or implication of relative importance is to be inferred. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
The delay circuit and the semiconductor device provided by the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 3, the present invention provides a delay circuit 1000, which may include:
a first delay locked loop 100 including a first delay chain 110 connected to a clock signal input terminal and composed of a first group of delay units, and one first delay unit 111 of the first group of delay units is configured to output a first delayed signal to the outside; and
a second delay locked loop 200 including a second delay chain 210 connected to the clock signal input terminal and composed of a second group of delay units and a third group of delay units connected to each other, and one second delay unit 211 of the second group of delay units corresponding to the first delay unit 111 outputting the first delay signal is configured to output a second delay signal to the outside,
the first delay time of the first delay signal output by the first group of delay units, the second delay time of the second delay signal output by the second group of delay units and the third delay time of the third delay signal output by the third group of delay units are different, and the first delay time is greater than the third delay time.
The delay time difference between the delay signals output by the two delay locked loops can be determined according to the first time information in the first delay signal output by the first delay unit and the second time information in the second delay signal output by the second delay unit, and the number of the first delay unit in the first group of delay units and the second delay unit in the second group of delay units.
Through the above technical scheme of the utility model, under the same integrated circuit manufacturing process condition with prior art, can be through realizing the delay unit in the different delay locked loop as having different delay time to can reduce the delay time difference between the delay signal of different delay locked loop outputs.
Specific implementations of the present invention are described below in several specific examples.
Referring to fig. 4, the present invention provides a delay circuit 1000, which may include a first delay locked loop 100 and a second delay locked loop 200, and the first delay locked loop 100 and the second delay locked loop 200 may be connected through a clock signal input terminal 300. The first delay locked loop 100 may be configured to generate a corresponding first delayed signal from a first clock signal CLK1 received through the clock signal input 300, and the second delay locked loop 200 may be configured to generate a corresponding second delayed signal from a second clock signal CLK2 received through the clock signal input. Based on the first time information in the first delayed signal and the second time information in the second delayed signal, a delay time difference between the first delayed signal output by the first delay locked loop 100 and the second delayed signal output by the second delay locked loop 200 can be determined.
The first delay locked loop 100 may include a first delay chain 110 connected to a clock signal input and a first voltage generation circuit 120. The first delay chain 110 may be configured to generate a first delay signal corresponding to the received first clock signal under the control of the first voltage generation circuit 120, and feed back the first delay signal to the first voltage generation circuit 120. First voltageThe generating circuit 120 may be configured to generate a corresponding first reference voltage (corresponding to V in fig. 3) according to the received first clock signalref1) The first reference voltage is provided to the first delay chain 110, and the first reference voltage is adjusted according to the first delay signal fed back by the first delay chain 110.
The first delay chain 110 may include N connected by the same and in sequence1(N1Is a positive integer greater than 1, for example, it is 4) first delay cells 111. This N1The first delay units 111 may each include a first input terminal, a second input terminal, and a delayed signal output terminal, and may output the first delayed signal (1) to the first delayed signal (N), respectively1). Wherein, the N1First input terminals of the first delay units 111 may be connected in parallel to the first voltage output terminal of the first voltage generation circuit 120 to receive the first reference voltage provided by the first voltage generation circuit 120, and a second input terminal of the first delay unit 111 located at the start of the first delay chain 110 may be connected to the clock signal generation apparatus 300, a second input terminal of the second first delay unit 111 to the nth voltage output terminal of the first delay chain 1101The second input terminals of the first delay units 111 may be connected to the first to nth delay units 111 to 111, respectively1-1 delayed signal output of the first delay unit, and N1The delayed signal output terminal of the first delay unit 111 may be connected to the feedback signal input terminal of the first voltage generating circuit 120 to feed back the first delayed signal (N) to the first voltage generating circuit 1201). In addition, N is1The delayed signal output terminal of any one first delay unit 111 (e.g., the second first delay unit 111) of the first delay units 111 may be used to output the first delayed signal to the outside, that is, the first delayed signal may be the first delayed signal (1) to the first delayed signal (N)1) Any one of them.
This N1The first delay units 111 may be voltage-controlled delay units or voltage-controlled inverse delay units, and may be formed by one or more inverters. In addition, each oneThe first delay times of the first delay units 111 are all the same and can be expressed as follows:wherein, T1Representing a first delay time, TCLK1Indicating the period of the first clock signal. In addition, the first delay time of each of the first delay units 111 is controlled by the first reference voltage, which may decrease or increase with an increase of the first reference voltage, and the first delay signal output by each of the first delay units 111 may be locked to the first clock signal, i.e., the first delay signal and the first clock signal have a uniform frequency and phase and remain stable when the first delay locked loop 100 is locked. Also, when the first delay locked loop 100 is locked, the first delay time of each first delay unit 111 may be greater than a minimum delay time of the first delay unit 111, which may be determined according to a manufacturing process of the first delay unit, for example, may be 2 ns.
As shown in fig. 5, the first voltage generating circuit 120 may include a first frequency discrimination phase detector (PFD)121, a first Charge Pump (CP)122, and a first Loop Filter (LF)123, which are connected in sequence. The first frequency discrimination phase detector 121 may be connected to a clock signal input terminal, and may be provided with an nth terminal1The first feedback signal input terminal of the first delay unit 111 is connected to the delayed signal output terminal thereof, and can be used for comparing the first clock signal sent by the clock signal generating device 300 with the Nth clock signal1The first delay signal (N) fed back by the first delay unit 1111) And controls the first charge pump 122 to adjust the generated first reference voltage according to the comparison result; the first charge pump 122 may be configured to adjust the first reference voltage under the control of the first frequency discrimination phase detector 121; the first loop filter 123 may be provided thereon with a first voltage output terminal for outputting a first reference voltage to each of the first delay cells 111, and may be used to stabilize fluctuations of the first reference voltage to adjust a first delay time of each of the first delay cells 111, thereby causing the first delay signal (1) to the first delay signal (N)1) Having a frequency and phase identical to the first clock signal.
The second delay locked loop 200 may include a second delay chain 210, a second voltage generating circuit 220, and a third voltage generating circuit 230. Wherein the second delay chain 210 may be connected with the clock signal input terminal 300, and may include a second group of delay cells and a third group of delay cells connected to each other and located at the front and rear thereof, respectively, and may be configured to generate a second delay signal and a third delay signal corresponding to the received second clock signal under the control of the second voltage generating circuit 120. The second voltage generation circuit 220 may be configured to generate a corresponding second reference voltage (corresponding to V in fig. 3) according to the received second clock signalref2) And providing a second reference voltage to the second group of delay units, and adjusting the second reference voltage according to a third delay signal fed back by the third group of delay units. The third voltage generation circuit 230 may be configured to provide a third reference voltage (corresponding to V in fig. 3) to the third group of delay cellsref3)。
The second group of delay units may comprise the same and sequentially connected N2(N2Is a positive integer greater than 1, which may be substituted with N1The same or different, for example, it is 3) second delay units 211. This N2The second delay units 211 may also each include a first input terminal, a second input terminal, and a delayed signal output terminal, and may output the second delayed signal (1) to the second delayed signal (N), respectively2). Wherein, the N2First input terminals of the second delay cells 211 may be connected in parallel to the second voltage output terminal of the second voltage generating circuit 220 to receive the second reference voltage provided by the second voltage generating circuit 120, and a second input terminal of a first second delay cell 211 located at a start end of the second delay chain 210 may be connected to the clock signal generating device 300, a second input terminal of the second delay cell 211 to an nth voltage output terminal located at an end of the second delay chain 2102Second input terminals of the second delay units 211 may be connected to the first to nth second delay units 211 to 211, respectively21 delayed signal output terminal of the second delay unit 211, and Nth2The delayed signal output of the second delay unit 211 may be connected to the second input of the first third delay unit of the third group of delay units. In addition, N is2The delay signal output terminal of a second delay unit 211 (e.g., a second delay unit 211) corresponding to the first delay unit 111 of the second delay units 211 outputting the first delay signal to the outside may also be used to output a second delay signal to the outside, and the second delay signal may also be the second delay signal (1) to the second delay signal (N)2) Any one of them. It should be noted that, here, the second delay unit 211 corresponds to the first delay unit 111, which means that the two delay units are located at the same position in the respective delay chains, for example, both are located at the start ends of the respective delay chains, that is, the two delay units are respectively the first delay units of the respective delay chains.
The second set of delay elements may be the same or different from the first set of delay elements. Specifically, when the first reference voltage is the same as the second reference voltage, the second group of delay cells may be different from the first group of delay cells; or when the first reference voltage is different from the second reference voltage, the second group of delay units and the first group of delay units can be the same or different, so that the second delay time generated by the second group of delay units is different from the first delay time generated by the first group of delay units.
In addition, N in the second group of delay units2Each of the second delay units 211 may be a voltage-controlled delay unit or a voltage-controlled inverse delay unit, and may be formed of one or more inverters, but all of the second delay units 211 may be different from all of the first delay units 111. In addition, the second delay time of each of the second delay units 211 is controlled by a second reference voltage, which may be decreased or increased as the second reference voltage increases, and the second delay signal output from each of the second delay units 211 may be locked to the second clock signal, that is, the second delay signal (1) to the second delay signal (N) when the second delay locked loop 200 is locked2) Has a frequency and phase identical to the second clock signal and remains stable. And is locked at the second delay locked loop 200The second delay time of each second delay unit 211 may be greater than the minimum delay time of the second delay unit 211, but different from the first delay time of the first delay unit 111.
The third group of delay units may comprise N connected in sequence3(N3Is a positive integer, e.g., 1), and the third delay units 212 may output the third delayed signal (1) to the third delayed signal (N), respectively3) And any one of the delayed signals may be the third delayed signal. Wherein, the N3The first input terminals of the third delay cells 212 may be connected in parallel to the third voltage generating circuit 230 to receive the third reference voltage from the third voltage generating circuit 230. Furthermore, the second input terminal of the first third delay unit 212 in the third group of delay units is connected to the Nth input terminal2The delayed signal output terminal of the second delay unit 211 is connected to the Nth delay chain 210 at the end of the second delay chain3The delayed signal output terminal of the third delay unit 212 is connected to the second feedback signal input terminal of the second voltage generating circuit 220 to feed back the third delayed signal (N) thereto3). It should be noted that the number of the third delay units 212 included in the third group of delay units may be set according to specific situations, and although not shown in the drawings, it may include only one third delay unit 212.
This N3The third delay units 212 may also be voltage-controlled delay units or voltage-controlled inverse delay units, and each may also be composed of one or more inverters, for example, may be buffers. In addition, N is3The third delay units 212 may be the same or different, and may include different third delay unit groups, and each of the third delay unit groups may include N31A first third delay cell group of third delay cells, containing N32A second third delay element group of third delay elements, … …, and a delay line comprising N3nThe nth third delay unit of the third delay units is grouped. Wherein the third delay units included in the third delay unit groups are different, and N3＝N31+N32+...N3nAnd n is a positive integer.
In addition, the third delay unit 212 of the third group of delay units may be wholly or partially identical to the second delay unit 211 of the second group of delay units, e.g., only the nth delay unit31The third delay units 212 are identical to the second delay units 211.
When the second delay locked loop 200 is locked, the third delay time of each third delay unit 212 may be less than the first delay time of the first delay unit 111 and may be greater than or equal to the minimum delay time of the third delay unit 212 under the control of the third reference voltage, and the specific size thereof may be controlled according to actual needs. When all the third delay units 212 are the same and are buffers each composed of a plurality of inverters, the third delay time thereof may satisfy the following condition:
When the third delay cells 212 in the third group of delay cells are different, the third delay times of different third delay cells 212 are different, which satisfy the following condition:
T31*N31+T32*N32+...T3n*N3n＜T1*|N1-N2l, where T31To T3nRespectively representing the third delay time from the first third delay unit group to the nth third delay unit group.
As shown in fig. 6, the second voltage generating circuit 220 may also include a second Phase Frequency Detector (PFD)221, a second Charge Pump (CP)222, and a second Loop Filter (LF)223, which are connected in sequence. The second phase frequency detector 221 may be connected to a clock signal input terminal, and may be provided with an nth phase frequency detector3A second feedback signal input terminal connected to the delayed signal output terminal of the third delay unit 212 and operable to compare the second clock signal received via the clock signal input terminal 300 with the Nth clock signal3A third delayThird delayed signal (N) fed back by unit 2123) And controls the second charge pump 222 to adjust the generated second reference voltage according to the comparison result; the second charge pump 222 may be used to adjust the second reference voltage under the control of the second phase frequency detector 221; the second loop filter 223 may be provided thereon with a second voltage output terminal for outputting a second reference voltage to each of the second delay units 211, and may be used to stabilize fluctuations of the second reference voltage to adjust a second delay time of each of the second delay units 111, thereby delaying the third delay signal (1) to the third delay signal (N)3) Having a frequency and phase coincident with the second clock signal.
The third voltage generating circuit 230 may include a fixed voltage generating circuit or an adjustable voltage generating circuit. Wherein the fixed voltage generation circuit may be used to provide a fixed third reference voltage to the third delay unit 212, which may include a bias voltage supply terminal of the delay circuit, as shown in fig. 7. The adjustable voltage generation circuit may be configured to provide an adjustable third reference voltage to a third group of delay cells in the second delay chain 210.
In an embodiment of the present invention, when only one third delay unit 212 is included in the third group of delay units or the plurality of third delay units 212 included therein are the same, the adjustable voltage generating circuit may include a third delay locked loop 400, as shown in fig. 8. The third delay locked loop 400 may also be connected to the clock signal input 300 and may also include a third delay chain 410 of a fourth group of delay cells and a fourth voltage generation circuit 420. Wherein the third delay chain 410 may be configured to generate a fourth delayed signal corresponding to the received third clock signal under the control of the fourth voltage generating circuit 420 and to feed back the fourth delayed signal to the fourth voltage generating circuit 420. The fourth voltage generation circuit 420 may be configured to generate a corresponding third reference voltage according to the received third clock signal, provide the third reference voltage to the third delay chain 410 and a third group of delay cells in the second delay chain 210, and adjust the third reference voltage according to a fourth delay signal fed back by the third delay chain 410.
The fourth group of delay units may also comprise N connected in sequence4(N4Is a positive integer greater than 1, e.g., 4) fourth delay units 411, and these fourth delay units 411 may be the same as the third delay unit 212, and these fourth delay units 411 may also output fourth delayed signals (1) to fourth delayed signals (N) respectively4). N in the fourth group of delay cells4The first input of the fourth delay unit 411 and N of the third group of delay units in the second delay chain 2103The first input terminals of the third delay cells 212 are all connected in parallel to the fourth voltage output terminal of the fourth voltage generating circuit 420 to receive the third reference voltage from the fourth voltage generating circuit, and the delay signal output terminal of the fourth delay cell 411 of the fourth group of delay cells located at the end of the third delay chain 410 is connected to the fourth feedback signal input terminal of the fourth voltage generating circuit 420. The fourth voltage generating circuit 420 may also include a third phase frequency detector 421, a third charge pump 422, and a third loop filter 423, which are connected in sequence.
For a detailed description of the third delay chain 410, reference may be made to the detailed description of the first delay chain 110 or the third delay chain 210 described above; for a detailed description of the fourth voltage generating circuit 420, reference may be made to the above detailed description of the first voltage generating circuit 120 or the second voltage generating circuit 220, and no redundancy is made here.
In another embodiment of the present invention, when only one third delay unit 212 is included in the third group of delay units or the plurality of third delay units 212 included therein are the same, the adjustable voltage generating circuit may further include a fourth delay locked loop 500 to an mth delay locked loop 700 connected in sequence, as shown in fig. 9, where M is a positive integer greater than 4. Preferably, the regulated voltage generation circuit 242 may include only the fourth delay locked loop 500 and the fifth delay locked loop 700. The fourth through mth delay locked loops 500 through 700 may also be connected to the clock signal input 300 to generate delay signals corresponding to the received clock signal. Furthermore, the delay time of each of these delay locked loops is controlled by the reference voltage generated by the next delay locked loop connected thereto. For example, the delay time of the ith delay locked loop is controlled by the reference voltage generated by the (i +1) th delay locked loop, where i is a positive integer between 4 and M-1.
The fourth through M-1 delay locked loops 500 through 600 may each include a delay chain (e.g., 510, … …,610,710) of two sets of delay cells connected in series and a voltage generation circuit (e.g., 520, … …,620,720) for providing a reference voltage to one of the two sets of delay cells, the reference voltage of the other of the two sets of delay cells being provided by the voltage generation circuit in the next delay locked loop connected thereto. For example, the reference voltage of another group of delay cells in the fourth delay locked loop may be provided by a voltage generation circuit in the fifth delay locked loop. The mth delay locked loop 700 may include a delay chain composed of a group of delay cells and a voltage generation circuit for providing a reference voltage to the group of delay cells and another group of delay cells in the M-1 th delay locked loop.
In addition, each group of delay cells may include one or more delay cells (e.g., 511,512, … …, 611,612,711) connected in series, and the delay cells in the same group of delay cells may be the same and the delay cells in different groups of delay cells may be different (e.g., different in number and/or structure of delay cells). In addition, the delay units to which the reference voltages are supplied by the same voltage generation circuit may be the same. The reference voltage generated by each voltage generating circuit may be the same or different, and may include a phase frequency detector, a charge pump, a loop filter, and the like, which are connected in sequence, but is not limited thereto.
In addition, the fourth delay locked loop 500 to the M-1 th delay locked loop 600 may be different in whole or in part, or may be the same in whole or in part. Moreover, two groups of delay units in the same delay locked loop can be the same or different.
For a detailed description of the fourth delay locked loop 500 through the M-1 delay locked loop 600, reference may be made to the above description of the second delay locked loop 200, which is not repeated herein. The mth delay locked loop 700 may be identical to the third delay locked loop 400 described above, and for a detailed description thereof, reference may be made to the related description of the third delay locked loop 400 described above, which is also not repeated herein.
In addition, although not shown in fig. 9, the reference voltage V of another group of delay cells 512 in the fourth delay locked loopref5May be provided by a voltage generation circuit in the fifth delay locked loop, and the voltage generation circuit 620 in the M-1 th delay locked loop may provide a reference voltage V to another group of delay cells in the M-2 th delay locked loopref(M-1)。
In another embodiment of the present invention, when the third group of delay cells in the second delay chain 210 includes a different plurality of third delay cell groups, the adjustable voltage generating circuit may include a plurality of delay locked loops corresponding to the plurality of third delay cell groups. Each of the plurality of delay locked loops may include a delay chain made up of a group of delay cells and a voltage generation circuit for providing a third reference voltage to the group of delay cells and a corresponding third group of delay cells. In addition, the third reference voltage provided by the voltage generation circuit to each third delay cell group may be different or the same.
Each group of delay cells in each delay locked loop may also include one or more delay cells that are the same and connected in sequence, and the structure and/or number of delay cells included in different delay locked loops or different groups of delay cells may be different.
For a detailed description of the plurality of delay locked loops, reference may be made to the above description of the third delay locked loop 400, which is not repeated herein.
In another embodiment of the present invention, when the third group of delay cells in the second delay chain 210 includes a different plurality of third delay cell groups, the adjustable voltage generating circuit may include a plurality of groups of delay locked loops corresponding to the plurality of third delay cell groups. Each group of delay locked loops may include a plurality of delay locked loops connected in series, and a delay time of each of the plurality of delay locked loops is controlled by a reference voltage generated by a next delay locked loop connected thereto.
For a detailed description of each set of delay locked loops, reference may be made to the above description of the fourth delay locked loop 500 through the mth delay locked loop 700, which are not repeated herein.
In the above-described embodiment, when all the third delay cells included in the third group of delay cells are the same, the second delay time T of the second delay locked loop2Can be expressed as follows:when the third voltage generating circuit is a fixed voltage generating circuit (e.g., as shown in FIG. 7), T in the above equation3Is a fixed value, e.g. 2ns, so that the second delay time T can be directly calculated according to the above equation2. When the third voltage generating circuit is an adjustable voltage generating circuit (e.g., as shown in FIG. 8), the fourth to M-1 delay locked loops each include (N)2+1) delay cells and only one delay cell is controlled by the reference voltage of the next delay locked loop, the second delay time T of the second delay locked loop2Can be expressed as follows:
T2＝(TCLK2-T3)/N2＝TCLK2*(1/N2/(-N2)M-2/N2+1/(N2+2))
a second delay time T of the second delay locked loop when the third group of delay cells includes a different plurality of third delay cell groups2Can be expressed as follows:
wherein, T31To T3nThe third delay times of the first third delay cell group to the nth third delay cell group respectively.
It should be noted that the number of delay locked loops and delay cells shown in the figures is merely an example, the delay circuit may include more or fewer delay locked loops, and each delay locked loop or group of delay cells may also include more or fewer delay cells. In addition, although the clock signal supplied to each delay locked loop is represented by CLK in the drawings, it may represent a different clock signal, and is not limited herein.
As can be seen from the above description, the present invention can reduce the delay time difference between the delay signals output by different delay locked loops by implementing the delay cells in different delay locked loops to have different delay times. Additionally, the utility model discloses can adopt different modes to provide third reference voltage to the third group delay unit in the second delay locked loop, this makes the delay chain can satisfy different application demands to its range of application has been increased. Further, by providing two multiplexers, it is possible to flexibly select the delay unit which outputs the delay signal to the outside, so that the convenience of use of the delay circuit can be improved.
The present invention also provides a semiconductor device which may include the delay circuit described in the above embodiments. The semiconductor device may further include other modules or units according to practical applications, and is not limited herein.
The devices, circuits, units and the like explained in the above embodiments may be specifically implemented by chips and/or entities (e.g., discrete components) or by products with certain functions. For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functions of the units can be integrated in one or more chips in implementing the present invention.
Although the present invention provides components as described in the above embodiments or figures, more or fewer components may be included in the device based on conventional or non-inventive efforts. The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments.
The above-described embodiments are described in order to enable those of ordinary skill in the art to make and use the invention. It will be readily apparent to those skilled in the art that various modifications to these embodiments may be made, and the generic principles described herein may be applied to other embodiments without the use of the inventive faculty. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications within the scope of the present invention according to the disclosure of the present invention.
Claims (10)
1. A delay circuit, characterized in that the delay circuit comprises:
a first delay locked loop including a first delay chain connected to the clock signal input and formed of a first set of delay cells; and
a second delay locked loop comprising a second delay chain of interconnected second and third sets of delay cells connected to the clock signal input,
wherein, a first delay time of a first delay signal output by the first group of delay units, a second delay time of a second delay signal output by the second group of delay units and a third delay time of a third delay signal output by the third group of delay units are different, and the first delay time is greater than the third delay time.
2. The delay circuit of claim 1,
the first delay locked loop further comprises a first voltage generation circuit having a first voltage output connected in parallel with the first input of the first group of delay cells and a first feedback signal input connected with the delay signal output of a first delay cell of the first group of delay cells at the end of the first delay chain;
the second delay locked loop further comprises a second voltage generating circuit and a third voltage generating circuit, wherein a second voltage output terminal of the second voltage generating circuit is connected in parallel with the first input terminal of the second group of delay cells, and a second feedback signal input terminal thereof is connected with a delay signal output terminal of a third delay cell of the third group of delay cells, which is located at the end of the second delay chain; and a third voltage output end of the third voltage generating circuit is connected with the first input end of the third group of delay units.
3. The delay circuit of claim 2, wherein the third voltage generation circuit comprises a fixed voltage generation circuit or an adjustable voltage generation circuit.
4. The delay circuit of claim 3, wherein the fixed voltage generation circuit comprises a bias voltage supply terminal of the delay circuit.
5. The delay circuit of claim 3, wherein when only one third delay cell is included in the third group of delay cells or a plurality of the third delay cells included therein are the same, the adjustable voltage generating circuit comprises a third delay locked loop, the third delay locked loop comprises a third delay chain formed by a fourth group of delay cells and a fourth voltage generating circuit, and a fourth voltage output terminal of the fourth voltage generating circuit is connected in parallel with a first input terminal of the fourth group of delay cells and a first input terminal of the third group of delay cells, and a fourth feedback signal input terminal thereof is connected with a delay signal output terminal of a fourth delay cell located at an end of the third delay chain in the fourth group of delay cells.
6. The delay circuit of claim 3, wherein when only one third delay cell is included in the third group of delay cells or the plurality of third delay cells included therein are the same, the adjustable voltage generation circuit comprises a fourth delay locked loop to an Mth delay locked loop connected in sequence, and the delay time of the delay signal generated by each of the fourth delay locked loop to the Mth delay locked loop is controlled by the reference voltage generated by the next delay locked loop connected thereto, M being a positive integer greater than 4.
7. The delay circuit of claim 6, wherein the fourth delay locked loop to the M-1 th delay locked loop each include a delay chain of two sets of delay cells connected in series and a voltage generation circuit for providing a reference voltage to one of the two sets of delay cells, the reference voltage of the other of the two sets of delay cells being provided by the voltage generation circuit in the next delay locked loop connected thereto.
8. The delay circuit of claim 3, wherein when the third group of delay cells comprises a different plurality of third groups of delay cells, the adjustable voltage generation circuit comprises a plurality of delay locked loops corresponding to the plurality of third groups of delay cells, and each of the plurality of delay locked loops comprises a delay chain of a group of delay cells and a voltage generation circuit for providing a third reference voltage to the group of delay cells and the corresponding third group of delay cells.
9. The delay circuit of claim 3, wherein when the third group of delay cells comprises a different plurality of third groups of delay cells, the adjustable voltage generation circuit comprises a plurality of groups of delay locked loops corresponding to the plurality of third groups of delay cells, and each group of delay locked loops comprises a plurality of delay locked loops connected in series, and the delay time of the delay signal generated by each of the plurality of delay locked loops is controlled by the reference voltage generated by the next delay locked loop connected thereto.
10. A semiconductor device characterized by comprising the delay circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920713086.0U CN209897029U (en) | 2019-05-17 | 2019-05-17 | Delay circuit and semiconductor device including the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920713086.0U CN209897029U (en) | 2019-05-17 | 2019-05-17 | Delay circuit and semiconductor device including the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209897029U true CN209897029U (en) | 2020-01-03 |
Family
ID=69001122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920713086.0U Active CN209897029U (en) | 2019-05-17 | 2019-05-17 | Delay circuit and semiconductor device including the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209897029U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110086463A (en) * | 2019-05-17 | 2019-08-02 | 湖北京邦科技有限公司 | Delay circuit and semiconductor device including the delay circuit |
| CN110086463B (en) * | 2019-05-17 | 2024-06-07 | 湖北锐光科技有限公司 | Delay circuit and semiconductor device including the same |
-
2019
- 2019-05-17 CN CN201920713086.0U patent/CN209897029U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110086463A (en) * | 2019-05-17 | 2019-08-02 | 湖北京邦科技有限公司 | Delay circuit and semiconductor device including the delay circuit |
| CN110086463B (en) * | 2019-05-17 | 2024-06-07 | 湖北锐光科技有限公司 | Delay circuit and semiconductor device including the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6184753B1 (en) | Clock delay circuitry producing clock delays less than the shortest delay element | |
| US8253462B2 (en) | Duty cycle correction method and its implementing circuit | |
| KR100305646B1 (en) | Clock correcting circuit | |
| US7994828B2 (en) | Frequency divider, frequency dividing method thereof, and phase locked loop utilizing the frequency divider | |
| US8593197B1 (en) | Delay line circuit, delay locked loop and tester system including the same | |
| US20080136479A1 (en) | Semiconductor memory device capable of easily performing delay locking operation under high frequency system clock | |
| US20030030473A1 (en) | Ring-resister controlled DLL with fine delay line and direct skew sensing detector | |
| US7557628B2 (en) | Method and apparatus for digital phase generation at high frequencies | |
| JP6594420B2 (en) | Time-to-digital converter and digital phase-locked loop | |
| US8981974B2 (en) | Time-to-digital converter and control method | |
| US11381231B2 (en) | Digital measurement circuit and memory system using the same | |
| US7219026B2 (en) | Frequency measuring circuits including charge pumps and related memory devices and methods | |
| JPH09512935A (en) | High precision clock distribution circuit | |
| US20040212413A1 (en) | DLL Circuit | |
| CN209897029U (en) | Delay circuit and semiconductor device including the same | |
| US7391245B2 (en) | Delay locked loop and method for setting a delay chain | |
| CN101626237B (en) | Delay phase-locked loop circuit with wide-frequency locking range for avoiding phase locking error | |
| CN110086463B (en) | Delay circuit and semiconductor device including the same | |
| US20050282511A1 (en) | Frequency multiply circuit using SMD, with arbitrary multiplication factor | |
| US20040222832A1 (en) | Interpolator circuit | |
| US7212052B2 (en) | Jitter suppressing delay locked loop circuits and related methods | |
| US8115532B2 (en) | Linear monotonic delay chain circuit | |
| US9276590B1 (en) | Generating signals with accurate quarter-cycle intervals using digital delay locked loop | |
| KR20050011586A (en) | Delay Locked Loop For Generating Multi-Phase Clocks Without Voltage-Controlled Oscillator | |
| JP2005354271A (en) | Semiconductor device, clock phase adjustment circuit, transmission circuit, and reception circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 436044 A03, Ezhou new high-tech creative city, Wutong Lake New District, Ezhou, Hubei Patentee after: Hubei Ruiguang Technology Co.,Ltd. Country or region after: China Address before: 436044 East Lake Phoenix New City, 9, Phoenix Road, Wutong lake, Ezhou, Hubei, A03-301 Patentee before: HUBEI JOINBON TECHNOLOGY CO.,LTD. Country or region before: China |
|
| CP03 | Change of name, title or address |