CN209896067U - Super junction power DMOS device - Google Patents
Super junction power DMOS device Download PDFInfo
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- CN209896067U CN209896067U CN201921232658.XU CN201921232658U CN209896067U CN 209896067 U CN209896067 U CN 209896067U CN 201921232658 U CN201921232658 U CN 201921232658U CN 209896067 U CN209896067 U CN 209896067U
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- 239000004065 semiconductor Substances 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 210000000746 body region Anatomy 0.000 claims abstract description 18
- 238000001465 metallisation Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 12
- 230000005684 electric field Effects 0.000 abstract description 9
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- 238000010586 diagram Methods 0.000 description 9
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- 230000015556 catabolic process Effects 0.000 description 3
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- 229910052732 germanium Inorganic materials 0.000 description 2
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- 150000002500 ions Chemical class 0.000 description 2
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- 238000000034 method Methods 0.000 description 1
- 238000005025 nuclear technology Methods 0.000 description 1
- 230000009024 positive feedback mechanism Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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Abstract
The utility model provides a super junction power DMOS device, including the metallization drain electrode, first conductive type heavily doped semiconductor substrate, first conductive type semiconductor column region, second conductive type semiconductor body region, first conductive type heavily doped semiconductor source region, second conductive type heavily doped semiconductor contact region, polycrystalline silicon gate electrode, gate dielectric layer, metallization source electrode, the utility model discloses an on the basis of conventional super junction power DMOS device, change first conductive type heavily doped semiconductor substrate into non-uniform doping by even doping, avoided the electric field peak on high doping substrate and low doping drift region layer, alleviated the SEB effect to improve the reliability of its device.
Description
Technical Field
The utility model belongs to the technical field of power semiconductor device, a surpass knot power DMOS device is related to.
Background
The DMOS device with the super junction structure is an important power device appearing in recent years, the basic principle of the DMOS device is a charge balance principle, the 2.5 power relation between the specific on-resistance and the withstand voltage of a drift region in a conventional device is broken through by introducing the super junction structure of a P column and an n column which are spaced in the drift region of the common power DMOS, so that the on-resistance of the device is greatly reduced under the condition of high-voltage application, the conversion efficiency of a high-voltage power device is improved, the DMOS device is an ideal power switch device in the field of power electronics, and the application prospect is very wide.
With the rapid development of strategic weaponry, space and nuclear technologies, more and more electronic devices are required to operate in harsh radiation environments, such as nuclear and space radiation. The radiation degrades the performance of the electronic system, greatly reduces the reliability and the service life of the electronic system, even leads to the paralysis of the whole electronic system, and causes huge potential safety hazard and cost waste. The single event effect is one of the main threats affecting the normal operation of the spacecraft in the space, and the heavy ions and the high-energy protons are important particle sources inducing the single event effect of electronic components in the spacecraft. When a single heavy particle or a high-energy proton suddenly penetrates into a semiconductor device, a large amount of charges generated along a material incident track can cause transient effects such as single-particle burnout (SEB), single-particle gate break-through (SEGR) and the like, so that fatal damage is brought to components, and the normal operation of the whole electrical system is influenced. As a power device with greatly improved performance compared with a VDMOS, the super-junction MOSFET has a very wide prospect in the field of aerospace. The SEB radiation resistance of the super-junction power DMOS device is improved, the source region doping concentration is reduced like that of a common super-junction power DMOS device, and besides, a buffer layer can be added between a substrate and a drift region. But the on-resistance of the device is increased by reducing the doping concentration of the source region of the device; the method for adding the buffer layer can reduce the electric field peak value between the N + substrate and the N-drift region, but the electric field peak value still exists at the interface between the buffer layer and the N-drift region, so that the SEB relieving capacity is limited.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a super junction power DMOS device.
In order to realize the purpose of the utility model, the utility model discloses technical scheme as follows:
a super junction power DMOS device comprises a metalized drain electrode 1, a first conductive type heavily doped semiconductor substrate 2 and a first conductive type semiconductor column region 3 in sequence from bottom to top, wherein the first conductive type semiconductor column region 3 and a second conductive type semiconductor column region 4 are alternately arranged, a second conductive type semiconductor body region 5 is arranged at the top of the second conductive type semiconductor column region 4, and the side face of the second conductive type semiconductor body region 5 is in contact with the first conductive type semiconductor column region 3; a heavily doped semiconductor source region 6 with a first conductivity type and a heavily doped semiconductor contact region 7 with a second conductivity type are arranged in the second conductivity type semiconductor body region 5; the polysilicon gate electrode 8 covers the whole first conductive type semiconductor column region 3 and part of the second conductive type semiconductor body region 5 and is isolated from the first conductive type semiconductor column region 3 and the second conductive type semiconductor body region 5 through a gate dielectric layer 9; the metallization source electrode 10 is located the uppermost layer of device, and the lower surface of metallization source electrode 10 and the upper surface of second conductivity type heavily doped semiconductor contact region 7 and the partial upper surface of first conductivity type heavily doped semiconductor source region 6 direct contact, its characterized in that: the first conductive type heavily doped semiconductor substrate 2 adopts non-uniform doping, and the doping concentration meets the following requirements: the doping concentration is gradually reduced from the direction close to the metalized drain electrode 1 to the direction close to the first conductive type semiconductor column region 3; the doping concentration of the first conductivity type heavily doped semiconductor substrate 2 also satisfies: the doping concentration near the metalized drain electrode 1 enables it to form ohmic contact with the metal, and the concentration near the bottom 1-3um of the first conductivity type semiconductor column region 3 is the same as the doping concentration of the first conductivity type semiconductor column region 3.
Preferably, the device is made of a semiconductor material such as silicon, germanium, silicon carbide, gallium arsenide, indium phosphide or gallium nitride.
Preferably, a first conductivity type semiconductor buffer layer 21 is provided between the first conductivity type heavily doped semiconductor substrate 2 and the metalized drain electrode 1.
Preferably, the first conductivity type is N-type, and the second conductivity type is P-type; or the first conduction type is a P type, and the second conduction type is an N type.
The utility model has the advantages that: on the basis of a conventional super junction power DMOS device, the first conduction type heavily doped semiconductor substrate is changed from uniform doping to non-uniform doping, so that electric field peaks of a high doped substrate and a low doped drift region layer are avoided, SEB effect is relieved, and reliability of the device is improved.
Drawings
Fig. 1 is a schematic diagram of a super junction power DMOS device structure and its parasitic BJT in embodiment 1 of the present invention;
fig. 2 is a schematic diagram of the doping concentration in the vertical direction of a conventional super junction power DMOS device;
fig. 3 is a schematic structural diagram of a super junction power DMOS device according to embodiment 2 of the present invention;
fig. 4 is a schematic diagram of the doping concentration in the vertical direction of the super junction power DMOS device according to embodiment 2 of the present invention;
fig. 5 is a schematic diagram of the doping concentration in the vertical direction of the super junction power DMOS device according to embodiment 1 of the present invention.
In the figure: 1 is a metalized drain electrode, 21 is a first conductivity type semiconductor buffer layer, 2 is a first conductivity type heavily doped semiconductor substrate, 3 is a first conductivity type semiconductor pillar region, 4 is a second conductivity type semiconductor pillar region, 5 is a second conductivity type semiconductor body region, 6 is a first conductivity type heavily doped semiconductor source region, 7 is a second conductivity type heavily doped semiconductor contact region, 8 is a polysilicon gate electrode, 9 is a gate dielectric layer, and 10 is a metalized source electrode.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Example 1
A super junction power DMOS device comprises a metalized drain electrode 1, a first conductive type heavily doped semiconductor substrate 2 and a first conductive type semiconductor column region 3 in sequence from bottom to top, wherein the first conductive type semiconductor column region 3 and a second conductive type semiconductor column region 4 are alternately arranged, a second conductive type semiconductor body region 5 is arranged at the top of the second conductive type semiconductor column region 4, and the side face of the second conductive type semiconductor body region 5 is in contact with the first conductive type semiconductor column region 3; a heavily doped semiconductor source region 6 with a first conductivity type and a heavily doped semiconductor contact region 7 with a second conductivity type are arranged in the second conductivity type semiconductor body region 5; the polysilicon gate electrode 8 covers the whole first conductive type semiconductor column region 3 and part of the second conductive type semiconductor body region 5 and is isolated from the first conductive type semiconductor column region 3 and the second conductive type semiconductor body region 5 through a gate dielectric layer 9; the metallization source electrode 10 is located the uppermost layer of device, and the lower surface of metallization source electrode 10 and the upper surface of second conductivity type heavily doped semiconductor contact region 7 and the partial upper surface of first conductivity type heavily doped semiconductor source region 6 direct contact, its characterized in that: the first conductive type heavily doped semiconductor substrate 2 adopts non-uniform doping, and the doping concentration meets the following requirements: the doping concentration is gradually reduced from the direction close to the metalized drain electrode 1 to the direction close to the first conductive type semiconductor column region 3; the doping concentration of the first conductivity type heavily doped semiconductor substrate 2 also satisfies: the doping concentration close to the metalized drain electrode 1 enables the metalized drain electrode to form ohmic contact with metal, the concentration close to the position 1-3um at the bottom of the first conductive type semiconductor column region 3 is the same as the doping concentration of the first conductive type semiconductor column region 3, and smooth transition of impurity concentration can be achieved.
Based on above-mentioned technical scheme, when first conductivity type semiconductor is N type semiconductor and second conductivity type semiconductor is the P type, the utility model provides a super junction power DMOS device is N channel super junction power DMOS device; when first conductivity type semiconductor is P type semiconductor and second conductivity type semiconductor is the N type, the utility model provides a super junction power DMOS device is super junction power DMOS device for the P channel.
Use N channel to surpass knot power DMOS device as the example and illustrate the utility model discloses a theory of operation:
fig. 2 is a schematic diagram of the doping concentration in the vertical direction of a conventional super junction power DMOS device. Under the condition that the bias voltage of the metalized drain electrode 1 is lower than the normal breakdown voltage, the drift current of electron hole pairs generated by radiation can change the electric field distribution of an epitaxial layer, so that avalanche breakdown occurs on the interface of the first conduction type heavily doped semiconductor substrate 2 and the first conduction type semiconductor column region 3. The electron-hole pairs generated by heavy ion incidence and avalanche breakdown form a drift current under the bias of the metalized drain electrode 1. The holes pass through the first conductive type semiconductor column region 3 to become base current of the parasitic triode, so that the parasitic triode in the off state is conducted, the carrier injection effect of an emitter junction is caused, and the avalanche multiplication effect is further promoted. The parasitic triode inside the super junction power DMOS device is shown in figure 1. A first conductive type heavily doped semiconductor source region 6 of the super junction power DMOS device is an emitting electrode of a parasitic triode, a first conductive type semiconductor column region 3 is a collecting electrode of the parasitic triode, and a second conductive type semiconductor body region 5 is a base electrode of the parasitic triode. The positive feedback mechanism enables the drain current to continuously rise until the device is burnt out due to high temperature, namely SEB failure of the super-junction power DMOS device occurs.
Through an SEB failure mechanism of a conventional super-junction power DMOS device, an electric field peak value is prevented from transferring to an interface between an N + substrate and an N-column region, the occurrence of an avalanche multiplication effect is reduced, and the SEB radiation resistance of the device can be improved.
The utility model provides a pair of reinforced (rfd) super junction power DMOS device, first conductive type heavy doping semiconductor substrate 2 adopt non-uniform doping. Fig. 5 is a schematic diagram of the vertical doping concentration of the super junction power DMOS device according to the present invention. The utility model provides a super junction power DMOS device can consolidate its radiation resistance's reason is: because the first conductive type heavily doped semiconductor substrate 2 adopts non-uniform doping, the doping concentration of the first conductive type heavily doped semiconductor substrate 2 to the first conductive type semiconductor column region 3 is slowly changed, no obvious junction region exists, the electric field peak value can be leveled, the occurrence of avalanche multiplication effect is reduced, a parasitic triode is more difficult to open, the SEB effect can be more effectively relieved, and the reliability of the device is improved.
Preferably, the device is made of semiconductor materials of silicon, germanium, silicon carbide, gallium arsenide, indium phosphide and gallium nitride.
Example 2
This example differs from example 1 in that: a first conductivity type semiconductor buffer layer 21 is provided between the first conductivity type heavily doped semiconductor substrate 2 and the metalized drain electrode 1.
Fig. 3 is a schematic diagram of the structure of the super junction power DMOS device with N-buffer layer, and fig. 4 is a schematic diagram of the doping concentration in the longitudinal direction of the super junction power DMOS device with buffer layer. The structure transfers the electric field peak value to the interface between the N-buffer layer and the N-column region, and relieves the SEB effect to a certain extent, but the junction of the N-buffer/N-column region still has an electric field peak, so that the relieving capability is limited.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (4)
1. A super junction power DMOS device sequentially comprises a metalized drain electrode (1), a first conductive type heavily doped semiconductor substrate (2) and a first conductive type semiconductor column region (3) from bottom to top, wherein the first conductive type semiconductor column region (3) and a second conductive type semiconductor column region (4) are alternately arranged, a second conductive type semiconductor body region (5) is arranged at the top of the second conductive type semiconductor column region (4), and the side surface of the second conductive type semiconductor body region (5) is in contact with the first conductive type semiconductor column region (3); a first conductive type heavily doped semiconductor source region (6) and a second conductive type heavily doped semiconductor contact region (7) are arranged in the second conductive type semiconductor body region (5); the polycrystalline silicon gate electrode (8) covers the whole first conduction type semiconductor column region (3) and part of the second conduction type semiconductor body region (5) and is isolated from the first conduction type semiconductor column region (3) and the second conduction type semiconductor body region (5) through a gate dielectric layer (9); the metallization source electrode (10) is located the uppermost layer of device, and the lower surface of metallization source electrode (10) and the upper surface of second conductivity type heavily doped semiconductor contact region (7) and the partial upper surface direct contact in first conductivity type heavily doped semiconductor source region (6), its characterized in that: the first conductive type heavily doped semiconductor substrate (2) adopts non-uniform doping, and the doping concentration meets the following requirements: the doping concentration is gradually reduced from the direction close to the metalized drain electrode (1) to the direction close to the first conductive type semiconductor column region (3); the doping concentration of the first conductivity type heavily doped semiconductor substrate (2) also satisfies: the doping concentration close to the metalized drain electrode (1) enables the metalized drain electrode to form ohmic contact with metal, and the concentration close to the bottom 1-3um of the first conductive type semiconductor column region (3) is the same as the doping concentration of the first conductive type semiconductor column region (3).
2. The super junction power DMOS device of claim 1, wherein: the device is made of semiconductor materials such as silicon, germanium-silicon, silicon carbide, gallium arsenide, indium phosphide and gallium nitride.
3. The super junction power DMOS device of claim 1, wherein: a first conductive type semiconductor buffer layer (21) is arranged between the first conductive type heavily doped semiconductor substrate (2) and the metalized drain electrode (1).
4. The super junction power DMOS device of claim 1, wherein: the first conductive type is an N type, and the second conductive type is a P type; or the first conduction type is a P type, and the second conduction type is an N type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921232658.XU CN209896067U (en) | 2019-07-31 | 2019-07-31 | Super junction power DMOS device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921232658.XU CN209896067U (en) | 2019-07-31 | 2019-07-31 | Super junction power DMOS device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416285A (en) * | 2019-07-31 | 2019-11-05 | 电子科技大学 | A kind of superjunction power DMOS device |
| CN113224164A (en) * | 2021-04-21 | 2021-08-06 | 电子科技大学 | Super junction MOS device |
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- 2019-07-31 CN CN201921232658.XU patent/CN209896067U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416285A (en) * | 2019-07-31 | 2019-11-05 | 电子科技大学 | A kind of superjunction power DMOS device |
| CN110416285B (en) * | 2019-07-31 | 2024-06-07 | 电子科技大学 | Super junction power DMOS device |
| CN113224164A (en) * | 2021-04-21 | 2021-08-06 | 电子科技大学 | Super junction MOS device |
| CN113224164B (en) * | 2021-04-21 | 2022-03-29 | 电子科技大学 | Super junction MOS device |
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Granted publication date: 20200103 |