CN209881739U

CN209881739U - PWM power amplifier capable of reducing phase distortion at modulation stage

Info

Publication number: CN209881739U
Application number: CN201920958261.2U
Authority: CN
Inventors: 张晨
Original assignee: Nanjing Toutuo Electronics Co Ltd
Current assignee: Nanjing Toutuo Electronics Co Ltd
Priority date: 2019-06-25
Filing date: 2019-06-25
Publication date: 2019-12-31
Anticipated expiration: 2029-06-25

Abstract

The utility model discloses a reduce PWM power amplifier of phase distortion at modulation level, including input stage, modulation level, power level and output stage. The input stage includes two loop filters that receive an input signal and output an integrated signal. The modulation stage includes a small phase error modulator that receives the integrated signal and outputs a PWM signal that is center synchronized with the carrier signal. The power stage receives the PWM signal and drives the switching device to amplify the PWM signal to the power rail. The output stage comprises a low-pass filter network, a Zoebel network and an upper and lower electric noise reduction circuit, receives the PWM signal of the power stage, and outputs the PWM signal to be connected with a load, the Zoebel network is connected between the output of the power stage and the ground, and the upper and lower electric noise reduction circuit is connected between the output signal and the ground. The center of the PWM signal is synchronous with the center of the carrier signal by utilizing the improved modulation level, so that the phase error is reduced; meanwhile, two feedbacks of the loop filter are added into the input stage, so that the performance of the power amplifier is greatly improved.

Description

PWM power amplifier capable of reducing phase distortion at modulation stage

Technical Field

The utility model relates to a field electronic circuit field, especially a reduce PWM power amplifier of phase distortion at modulation level.

Background

Historically, power amplifiers have been classified into class a, class B and class AB, which are well known for their superior audio performance and extremely low efficiency. Due to the adoption of a switching mode, a class-D power amplifier is always known to have high efficiency and has poor performance caused by nonlinearity and the like. With the continuous optimization of the switch modulation mode, the class-D power amplifier also enables high-efficiency, small-sized, high-power and high-quality audio performance.

In the PWM modulation method, since power devices such as MOSFETs have a certain junction capacitance, a delay phenomenon occurs in turning on and off the devices, and in order to avoid this phenomenon, a dead time is set when designing a circuit. If the dead time is large, the work of the modulation stage is obviously more reliable, but the aggravation of the distortion of the output waveform and the reduction of the output efficiency are brought; the dead time is small, reducing distortion of the output waveform, but reducing reliability. The modulation stage and thus the dead time needs to find a certain balance between performance and stability.

Therefore, it is necessary to provide a PWM power amplifier that reduces phase distortion during the modulation phase.

Disclosure of Invention

In view of the above, the present invention provides a PWM power amplifier that reduces phase distortion at the modulation stage.

The utility model discloses a reduce PWM power amplifier of phase distortion at modulation level, including input stage, modulation level, power level and output stage. The input stage comprises two loop filters, receives an input signal and outputs an integrated signal. The modulation stage includes a small phase error modulator that receives the integrated signal and outputs a PWM signal that is center synchronized with the carrier signal. The power stage receives the PWM signal and drives the switching device to amplify the PWM signal to the power rail. The output stage comprises a low-pass filter network, a Zoebel network and an upper and lower electric noise reduction circuit, receives the PWM signal of the power stage, outputs and connects with a load, the Zoebel network is connected between the output of the power stage and the ground, and the upper and lower electric noise reduction circuit is connected between the output signal and the ground.

The input stage comprises two loop filters. The first loop filter is a differential operational amplifier, the in-phase input end and the reverse-phase input end are respectively connected with mutually reverse-phase input signals, the in-phase input end and the reverse-phase input end are also respectively connected with the output stage through a resistor to serve as feedback, a CRC second-order integral feedback is arranged between the in-phase output end and the reverse-phase input end, and a CRC second-order integral feedback is arranged between the reverse-phase output end and the in-phase input end. The second loop filter is a differential operational amplifier, the in-phase input end and the reverse-phase input end are respectively connected with the in-phase output end and the reverse-phase output end of the first loop filter, the in-phase input end and the reverse-phase input end are also respectively connected with the output stage through a resistor to serve as feedback, a CRC second-order integral feedback is arranged between the in-phase output end and the reverse-phase input end, and a CRC second-order integral feedback is arranged between the reverse-phase output end and the in-phase input end.

Since the signals output by the in-phase output terminal and the anti-phase output terminal of the input stage are connected in the same way as the signal processing way in the modulation stage and the output stage, in the following description of the modulation stage and the output stage, only the connection way of the in-phase output terminal is described, and the connection way of the anti-phase output terminal is completely the same as the in-phase output terminal.

The modulation stage comprises a small phase error modulator. The small phase error modulator comprises a first comparator, an AND gate, two switching devices, two current sources, a charging capacitor and a second comparator. The non-inverting input end of the first comparator is connected with the non-inverting output end of the input stage, the inverting input end of the first comparator is connected with the triangular carrier signal, and the output signal of the input stage is compared with the triangular carrier signal to generate a conventional PWM signal. And the input of the AND gate is the output of the first comparator and a square wave signal with the same frequency as the triangular carrier signal, and the two signals are subjected to phase comparison to obtain a half PWM signal. The first switch device, the first current source, the second current source and the second switch device are sequentially connected in series between an auxiliary power supply and the ground, and the first switch device is controlled to be conducted by a half PWM signal output by the AND gate. The non-inverting input end of the second comparator is connected between the first current source and the second current source, the inverting input end of the second comparator is connected to the non-inverting input end through the charging capacitor, and the output end of the second comparator is connected with the power stage. The first current source charges the charging capacitor from a reference voltage, so that the voltage of the non-inverting input end of the second comparator rises to trigger the second comparator to change the output state, and then the second current source is triggered to conduct to discharge the charging capacitor. The first current source has a value twice that of the second current source. The output of the second comparator is a PWM signal which is synchronous with the center of the triangular carrier signal, is independent of the input signal and has almost no phase error.

The power stage receives the PWM signal with almost no phase error output from the modulation stage, drives the power switching device to amplify the PWM signal to a power rail, and then outputs the PWM signal of the power stage to the output stage. The driving chip of the power stage comprises a mute pin.

The output stage includes a low pass filter network, a sobel network, and an electrical noise reduction circuit. The sobel network includes a capacitor and a resistor connected in series to ground to prevent output spikes. The low-pass filter network comprises an inductor and a capacitor connected in series to ground, and the cut-off frequency is lower than the frequency of the triangular carrier wave in the modulation stage. The upper and lower electrical noise reduction circuit comprises a switch, three resistors, two MOSFETs, two transistors and a zener diode. A positive power supply is connected to the gates of the two MOSFETs and the cathode of the zener diode through the switch and the first resistor, the switch being controlled by a mute pin signal of the power stage; the two MOSFETs are connected back to back between the filtered signal and ground; the second resistor and the third resistor are respectively connected between the grids of the two MOSFETs and the bases of the two transistors; the two transistors are connected back to the other end of the first resistor. And the second resistor, the third resistor and the two triodes are adopted to realize overcurrent protection of the upper and lower electric noise reduction circuits.

The utility model utilizes the improved modulation level to synchronize the center of the final PWM signal with the center of the carrier signal, and is independent of the input signal, thereby reducing the phase error; meanwhile, two feedbacks of a second-order loop filter are added into the input stage, so that the performance of the power amplifier is greatly improved; and the up-down electric noise reduction circuit with an overcurrent protection function is added in the output stage, and the voltage at two ends of the load is reduced by using the low-impedance shunt circuit at the moment of up-down electric, so that the noise at the moment of switching is reduced.

In order to make the above and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a circuit diagram of a PWM power amplifier with phase distortion reduction at the modulation stage according to the present invention;

fig. 2 is a schematic diagram of waveforms involved in the modulation stage of the present invention.

Numbering in the figures:

10: an input stage; 20: a modulation stage; 30: a power level; 40: an output stage; 201. 202: and-gates in said modulation stage.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention.

Referring to fig. 1, a circuit diagram of a PWM power amplifier for reducing phase distortion in a modulation stage according to the present invention includes an input stage 10, a modulation stage 20, a power stage 30, and an output stage 40. The input stage 10 includes a first loop filter composed of a differential operational amplifier a1, a non-inverting input terminal and an inverting input terminal are respectively connected to mutually inverted input signals Vin and Vip, the non-inverting input terminal and the inverting input terminal are also respectively connected to the output stage 40 through a resistor Rfb1, a second-order integral feedback composed of C1, R1 and C2 is provided between the non-inverting output terminal and the inverting input terminal, and a second-order integral feedback composed of C3, R2 and C4 is provided between the inverting output terminal and the non-inverting input terminal. The input stage 10 further includes a second loop filter composed of a differential operational amplifier a2, a non-inverting input terminal and an inverting input terminal are respectively connected to a non-inverting output terminal and an inverting output terminal of a1, the non-inverting input terminal and the inverting input terminal are also respectively connected to the output stage 40 through a resistor Rfb2, a second-order integral feedback composed of C5, R3 and C6 is provided between the non-inverting input terminal and the inverting input terminal, and a second-order integral feedback composed of C7, R4 and C8 is provided between the inverting output terminal and the non-inverting input terminal. The modulation stage 20 comprises two tuning paths for modulating the signals Vip ', Vin' of the in-phase output and the anti-phase output of a2, respectively, and only the signal Vin 'of the anti-phase output is described in detail herein, and the working principle of the signal Vip' of the in-phase output is exactly the same. The modulation stage 20 comprises a first comparator Cmp1, an and gate 201, two switching devices M1 and M2, two current sources I1 and I2, a charging capacitor C9, a second comparator Cmp 2. The non-inverting input terminal of the first comparator Cmp1 is connected to the inverting output terminal Vin' of a2, and the inverting input terminal thereof is connected to the triangular carrier signal Vc, and after comparison, the conventional PWM signal V1 is generated. And gate 201 takes and of square wave signal Vcs and V1 with the same frequency as Vc to obtain half PWM signal Vh 1. The first switching device M1, the first current source I1, the second current source I2 and the second switching device M2 are sequentially connected in series between the auxiliary power supply and the ground. The non-inverting input of the second comparator Cmp2 is connected between I1 and I2, the non-inverting input and the inverting input are connected through C9, and the inverting input is connected to Vref. The output of Cmp2 is connected to power stage 30. The power stage 30 receives the output signals Vm1, Vm2 of Cmp2 and Cmp4, amplifies to supply rails (+ B, -B), and outputs to the output stage 40. The output stage 40 comprises a low pass filter network, a sobel network comprising a capacitor C11 and a resistor R5 connected in series to ground, and upper and lower electrical noise reduction circuits; the low-pass filter network comprises an inductor L1 and a capacitor C12 connected in series to the ground; the upper and lower electrical noise reduction circuit includes a switch S1, three resistors R6, R7 and R8, two MOSFETs (M5, M6), two transistors J1 and J2, and a zener diode VD 1. The positive power supply is connected to M5, the gate of M6 and the cathode of VD1 through S1 and R6, S1 is controlled by the Mute pin signal (Mute) of the power stage 30; m5, M6 are connected back-to-back between the filtered signal and ground; r7 and R8 are respectively connected between the gates of M5 and M6 and the bases of J1 and J2; j1, J2 are connected back to the other end of R6.

Please refer to fig. 2, which is a schematic diagram of waveforms related to the modulation stage according to the present invention. Vin' is compared with the triangular carrier signal Vc, generating the conventional PWM signal V1; taking the phase of the square wave signal Vcs with V1 to generate a half PWM signal Vh 1; vh1 controls the switch of M1 in fig. 1 to change the signal Vt1 at the non-inverting input of Cmp 2; the center of the PWM signal Vm1 generated by the comparison is synchronized with the center of the triangular carrier Vc, independent of Vin'.

The above only is the embodiment of the present invention, not limiting the patent scope of the present invention, all the equivalent structures or equivalent processes that are used in the specification and the attached drawings or directly or indirectly applied to other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A PWM power amplifier for reducing phase distortion at a modulation stage, comprising an input stage, a modulation stage, a power stage and an output stage; the input stage comprises two loop filters, and the output of the loop filters is connected with the modulation stage; the modulation stage comprises a small phase error modulator, and the output of the small phase error modulator is connected with the power stage; the power stage output is connected with the output stage; the output stage comprises a low-pass filter network, a Zoebel network and an upper and lower electric noise reduction circuit, the Zoebel network is connected between the output of the power stage and the ground, the upper and lower electric noise reduction circuit is connected between an output signal and the ground, and the output of the output stage is connected with a load.

2. A PWM power amplifier for reducing phase distortion in a modulation stage according to claim 1, wherein said input stage comprises two loop filters, said first loop filter is a differential operational amplifier, the non-inverting input terminal and the inverting input terminal are respectively connected to mutually inverted input signals, the non-inverting input terminal and the inverting input terminal are respectively connected to said output stage through a resistor as feedback, a CRC second order integral feedback is provided between the non-inverting input terminal and the inverting input terminal, and a CRC second order integral feedback is provided between the inverting input terminal and the non-inverting input terminal; the second loop filter is a differential operational amplifier, the in-phase input end and the reverse-phase input end are respectively connected with the in-phase output end and the reverse-phase output end of the first loop filter, the in-phase input end and the reverse-phase input end are respectively connected with the output stage through a resistor to serve as feedback, a CRC second-order integral feedback is arranged between the in-phase output end and the reverse-phase input end, and a CRC second-order integral feedback is arranged between the reverse-phase output end and the in-phase input end.

3. The PWM power amplifier of claim 1, wherein said modulation stage comprises a small phase error modulator, said small phase error modulator comprising a first comparator, an and gate, two switching devices, two current sources, a charging capacitor, a second comparator; the non-inverting input end of the first comparator is connected with the non-inverting output end of the input stage, and the inverting input end of the first comparator is connected with the triangular carrier signal; the input of the AND gate is a square wave signal with the frequency same as that of the triangular carrier signal and the output of the first comparator; the first switch device, the first current source, the second current source and the second switch device are sequentially connected in series between an auxiliary power supply and the ground, and the output of the AND gate controls the first switch device; the non-inverting input end of the second comparator is connected between the first current source and the second current source, the inverting input end of the second comparator is connected to the non-inverting input end through the charging capacitor, and the output end of the second comparator is connected with the power stage; the first current source has a value twice that of the second current source.

4. The PWM power amplifier of claim 1, wherein said output stage comprises a low pass filter network, a sobel network and a power-down and power-up noise reduction circuit; the zoebel network includes a capacitance and a resistance in series to ground; the low-pass filter network comprises an inductor and a capacitor connected in series to the ground, and the cut-off frequency is lower than the frequency of the triangular carrier wave in the modulation stage; the upper and lower electric noise reduction circuit comprises a switch, three resistors, two MOSFETs, two transistors and a voltage stabilizing diode; a positive power supply is connected to the gates of the two MOSFETs and the cathode of the zener diode through the switch and the first resistor, the switch being controlled by a mute pin signal of the power stage; the two MOSFETs are connected back to back between the filtered signal and ground; the second resistor and the third resistor are respectively connected between the grids of the two MOSFETs and the bases of the two transistors; the two transistors are connected back to the other end of the first resistor.