CN209803777U

CN209803777U - NVDIMM controller and NVDIMM

Info

Publication number: CN209803777U
Application number: CN201822275375.5U
Authority: CN
Inventors: 周小锋; 江喜平
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xi'an Ziguang Guoxin Semiconductor Co ltd
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2019-12-17
Anticipated expiration: 2028-12-29

Abstract

The utility model provides a NVDIMM controller and NVDIMM. The NVDIMM controller controls the NVDIMM and comprises a DDR controller (101), a NAND flash controller (102), a data backup module (103) and a data recovery module (104), and the DRAM adopts DBI and enables the DBI. In data backup, DDR controller reads N bits DQ from DRAM_iAnd 1-position DBI_iAnd sends it to the data backup module when the DBI is_iWhen 1, the data backup module compares DQ_iAnd DQ_i‑1If DQ_iAnd DQ_i‑1If the median is different and the digit is greater than N/2, then the DQ is inverted_iAnd DBI_iSet to 0, otherwise hold DQ_iAnd DBI_iThe change is not changed; when DBI is used_iAt 0, DQ_iAnd DBI_iRemaining unchanged, the data backup module will process the DQs_iAnd DBI_iSending to a NAND controller that will process the DQs_iAnd DBI_iAnd writing into the NAND flash memory.

Description

NVDIMM controller and NVDIMM

Technical Field

The utility model relates to a non-volatile memory field, more specifically relate to a NVDIMM controller and NVDIMM of low-power consumption.

Background

NVDIMM is a non-volatile memory that includes DRAM, NAND Flash (NAND Flash), and NVDIMM controller. When the mainboard/CPU is abnormal or the power is down, the NVDIMM controller is informed through an interrupt or a message, and the NVDIMM controller can back up the data in the DRAM to the NAND flash memory. When the main board/CPU is powered on again later, the main board/CPU informs the NVDIMM controller to restore the data backed up in the NAND flash memory to the DRAM, and charges the super capacitor. The NVDIMM is powered by the super capacitor during data backup, but the super capacitor has limited power supply capacity and has larger attenuation along with the service time and the working temperature. For NVDIMMs, power consumption for data backup and data backup/restore time are two important performance indicators, which determine the capacity and reliability of the super capacitor and the cost of the product. The increase of data backup power consumption needs to be compensated by improving the capacity of the super capacitor, and the increase of the capacity of the super capacitor can increase the cost and reduce the reliability; data backup/restore time determines power consumption and user experience during data backup. Therefore, the fast backup and recovery of the NVDIMM data with low power consumption can obviously improve the competitiveness of products.

For the NVDIMM controller of DDR4, the power consumption mainly comes from DDR and NAND interfaces, and in the prior art, the power consumption can be reduced by about 25-40% by using dbi (data Bus inversion) on the DDR interface side, and since the NAND flash interface does not provide a signal for data inversion, the power consumption reduction for the NAND interface is difficult to achieve. While NAND flash typically operates at 1.8V (ONFI version 4.0) is a major source of NVDIMM controller interface power consumption.

Chinese patent publication CN107861901A discloses a storage method and system based on NVDIMM-F. The method comprises the following steps: when receiving data to be stored, the CPU sends the data to be stored to the NVDIMM-F; NVDIMM-F stores data to be stored. According to the method, the data to be stored are directly stored in the NVDIMM-F, so that the transmission rate of the data to be stored is greatly improved. However, this method only involves the operation of NVDIMM to store data in NAND and does not involve how to design low power consumption on NAND interface according to the operation data characteristics to reduce the power consumption of NAND interface.

SUMMERY OF THE UTILITY MODEL

The purpose of the utility model is to solve the following problems:

a) Reducing power consumption of the NAND interface with an NVDIMM controller;

b) Data recovery rates are improved with NVDIMM controllers.

According to a first aspect of the present invention, there is provided an NVDIMM controller comprising a DDR controller and a NAND flash memory controller, the NVDIMM controller for controlling an NVDIMM, the NVDIMM comprising a DRAM and a NAND flash memory, wherein the DRAM employs a DBI, characterized in that,

The NVDIMM controller further comprises:

A data backup module at DBI_iComparison of DQ at 1_iAnd DQ_i-1If DQ_iAnd DQ_i-1If the number of bits with different median values is greater than N/2, DQ is obtained_iTurning over and DBI_iset to 0, otherwise hold DQ_iAnd DBI_iThe change is not changed; the data backup module is in DBI_iHolding DQ at 0_iAnd DBI_iThe change is not changed; and

A data recovery module to determine DQs received from the NAND flash memory controller_iAnd DBI_iIf DBI_iIs equal to 0 and DQ_iIf the number of the middle 1 is less than or equal to N/2, the data recovery module converts the DQ_iTurning over and DBI_iRewriting to 1, otherwise the data recovery module holds DQ_iAnd DBI_iAnd is not changed.

According to a preferred embodiment of the first aspect of the present invention, wherein the data backup module arranges DQ in units of pages of the NAND flash memory_iAnd DBI_iThe order of (a).

According to a preferred embodiment of the first aspect of the present invention, wherein the data recovery module recovers DQ in units of pages of the NAND flash memory_iAnd DBI_i。

According to a preferred embodiment of the first aspect of the present invention, wherein the DRAM is DDR 4.

According to a preferred embodiment of the first aspect of the present invention, wherein the DRAM is DDR4 × 8 or DDR4 × 16.

According to the utility model discloses a second aspect provides a NVDIMM, this NVDIMM include according to the utility model discloses first aspect NVDIMM controller.

The utility model discloses a NVDIMM controller is to the DDR that has used DBI mechanism, wherein 1) NVDIMM controller's data backup module is at DBI_iComparison of DQ at 1_iand DQ_i-1If DQ_iand DQ_i-1If the number of bits with different median values is greater than N/2, DQ is obtained_iTurning over and DBI_iSet to 0, otherwise hold DQ_iAnd DBI_iThe change is not changed; the data backup module is in DBI_iHolding DQ at 0_iAnd DBI_iInvariant, and 2) the data recovery module of the NVDIMM controller determines DQ received from the NAND flash controller_iand DBI_iIf DBI_iIs equal to 0 and DQ_iIf the number of the middle 1 is less than or equal to N/2, the data recovery module converts the DQ_iTurning over and DBI_iRewritten to 1, otherwise holds DQ_iAnd DBI_iAnd is not changed. The NVDIMM adopting the NVDIMM controller can reduce the power consumption of the NAND interface and improve the data recovery rate.

Drawings

The invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is to be understood that these drawings are for illustrative purposes only and are not necessarily drawn to scale. In the drawings:

Fig. 1 is a system block diagram of an NVDIMM controller according to one embodiment of the present invention.

Fig. 2 is a schematic diagram of an NVDIMM in accordance with an embodiment of the present invention.

Detailed Description

According to the utility model discloses, NVDIMM controller realizes that nonvolatile function is mainly accomplished by DDR controller, NAND flash memory controller and data backup/recovery module triplex, and these triplex are realized using FPGA or ASIC. The utility model discloses to the DDR that has used the DBI function. Unless otherwise indicated, the DDR described herein is DDR4, but it should be understood that the present invention is not so limited and that the present invention is equally applicable to other existing and future DDR versions that support DBI.

Fig. 1 is a system block diagram of an NVDIMM controller according to one embodiment of the present invention. Taking DDR4x8 as an example, the interface signals associated with the DDR controller are 8 bits DQ and 1 bit DBI.

The operation of the NVDIMM controller will be described in detail below.

The DDR controller reads data from DRAM, due to the action of DBI, the number of '1' in DQ and DBI indication has 9 possibilities, as shown in Table 1, DBI is '0' indicating that there is a flip in DQ data, otherwise, DQ is not flipped.

Table 1: DQ and DBI values and relationships

And the data backup module processes the DQ and the DBI. For DQ_iIf the DQ is_iDBI of 1, the data backup module will DQ_iAnd DQ_i-1Comparing and detecting DQ_iAnd DQ_i-1The number of bits in which the medians are not the same. If the bit number with different values is larger than N/2, wherein N is the bit number of DQ, the data backup module will convert DQ_iFlip over and convert DQ_iDBI of the data backup module is set to be 0, if the number of bits with different values is less than or equal to N/2, the data backup module keeps DQ_iAnd DBI_iAnd is not changed. If DQ_iDBI of 0, the data backup module does not perform DQ_iAnd DQ_i-1To maintain DQ_iAnd DBI_iAnd is not changed. The data backup module sends the processed DQ and DBI to the NAND controller, and the processed DQ and DBI are controlled by the NAND controllerThe device writes the processed DQ and DBI into the NAND flash memory to complete data backup.

The data backup module may use a page (page) of the NAND flash memory as a unit when processing DQ and DBI. Taking a 9KB sized page as an example, read 8KB DQ and 1KB DBI from the DDR interface, format DQ and DBI:

DQ₀DQ₁DQ₂DQ₃DQ₄DQ₅DQ₆DQ₇DBI₀DBI₁DBI₂DBI₃DBI₄DBI₅DBI₆DBI₇and (4) organizing. It should be understood that DQ_iIs 8KB, and DBI_iIs 1 KB. Further, it should be understood that any other suitable format may be used.

When the NVDIMM controller restores the data, the NAND controller reads DQ and DBI from the NAND flash memory and sends to the data restoration module. If DBI_i0 and corresponding DQ_iIs less than or equal to 4, the data recovery module converts the DQ_iTurning over and DBI_iRewritten to 1, otherwise holds DQ_iAnd DBI_iThe change is not changed; if DBI_i0 and corresponding DQ_iIs greater than 4 or if DBI_iData recovery module holds DQ 1_iAnd DBI_iAnd is not changed. And then the data recovery module recovers and writes the DQ into the DRAM through the DDR controller according to the rule of the DBI.

When the data backup module processes DQ and DBI by taking a page (page) of the NAND flash memory as a unit, reading backup written data by taking the page as a unit, and analyzing according to a written format to obtain DQ and DBI stored in the NAND flash memory.

Fig. 2 is a schematic diagram of an NVDIMM in accordance with an embodiment of the present invention. As shown in fig. 2, the NVDIMM controller 100 includes a DDR controller 101, a NAND flash controller 102, a data backup module 103 and a data restore module 104. The NVDIMM controller controls NVDIMM200 including DRAM201 and NAND flash memory 202, data backup/restore module data backup and data restore. The DDR controller is connected with the DRAM, the NAND flash memory controller is connected with the NAND flash memory, the data backup module is connected with the DDR controller and the NAND flash memory controller, and the data recovery module is connected with the DDR controller and the NAND flash memory controller.

it is understood that these embodiments are for illustrative purposes only and that many variations may be made by those skilled in the art, while the scope of the invention is defined by the claims.

Claims

1. an NVDIMM controller comprising a DDR controller and a NAND flash controller, the NVDIMM controller for controlling an NVDIMM comprising DRAM and NAND flash, wherein the DRAM employs DBI,

The NVDIMM controller further comprises:

2. The NVDIMM controller of claim 1, wherein the data backup module arranges DQ in units of pages of NAND flash memory_iAnd DBI_iThe order of (a).

3. The NVDIMM controller of claim 2, wherein the data recovery module recovers DQ in units of page of the NAND flash memory_iAnd DBI_i。

4. The NVDIMM controller of claim 2, wherein the DRAM is DDR 4.

5. The NVDIMM controller of claim 4, wherein the DRAM is DDR4x8 or DDR4x 16.

6. An NVDIMM comprising the NVDIMM controller of any one of claims 1-5.