CN209418507U - A kind of normally-off SiC base DMOSFET device - Google Patents
A kind of normally-off SiC base DMOSFET device Download PDFInfo
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Abstract
The utility model relates to semiconductor fields, a kind of normally-off SiC base DMOSFET device is provided, including SiC epitaxial material substrate, 2D high mobility electrical transmission floor, the area p well, p+ type ultrashort channel floor, n++ type doped region, p++ type doped region, gate medium, gate electrode contact, source electrode contact, drain electrode contact, insulating material layer and pad metal layer, SiC epitaxial material substrate includes n++ type substrate base, n+ type buffer layer and n-type drift layer, n+ type buffer layer is located at the upper surface of n++ type substrate base, and n-type drift layer is located at the upper surface of n+ type buffer layer；2D high mobility electrical transmission layer is located at the upper surface of n-type drift layer, the area p well is set between this two layers, the gate electrode contact of division is located at the upper surface of gate medium, source electrode contact is located at the upper surface of n++ type doped region and p++ type doped region, and drain electrode contact is located at the lower surface of n++ type substrate base.The advantages of the utility model for reducing SiC base DMOSFET device channel resistance and Miller charge, to improve its high-frequency figure of merit.
Description
Technical field
The utility model relates to semiconductor fields, more particularly to a kind of normally-off SiC base DMOSFET device.
Background technique
The physically and electrically characteristic of silicon carbide (SiC) material has apparent advantage compared to traditional Si material.SiC tool
There is the features such as forbidden band is wide, thermal conductivity is high, disruptive field intensity is high, saturated electrons drift speed is high, while also with fabulous physics
And chemical stability, extremely strong Radiation hardness and mechanical strength etc..Therefore, the electronic device based on broad stopband SiC material can
For field of power electronics such as high temperature, high-power, high frequency, high radiation, and SiC base device can be given full play in energy-saving and emission-reduction side
Considerable advantage occupied by face and outstanding feature.
SiC metal-oxide semiconductor fieldeffect transistor (MOSFET) power device in commercialization process very
Maturation, especially using the MOSFET of planar gate structure as mainstream, i.e. DMOSFET.However, SiC base DMOSFET device is situated between in grid
The reliability etc. of matter layer encounters larger challenge, wherein main reasons is that thermal oxide SiC substrate and the SiO that is formed2Layer
There is more interfacial state between SiC substrate, these interfacial states are captured under high temperature High-Field or launching electronics, are unfavorable for device
Electrical stability.
At present the problems such as the low channel mobility and high reverse transfer capacitance of SiC base DMOSFET device, on the one hand, in order to
The ducting capacity of SiC base DMOSFET device is improved, if designer can use the MOSFET of Ganlei's accumulation type channel, however it is such
MOSFET is also faced with threshold voltage shift and the normally opened risk problem of device；On the other hand, SiC base DMOSFET device is used
In high frequency field, reverse transfer capacitance and Miller charge determine therefore the height of its HF switch loss will solve how to make
The device has high ducting capacity and low Miller charge.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of normally-off SiC base DMOSFET device, for dropping
The channel resistance and Miller charge of low SiC base DMOSFET device, to improve the high-frequency figure of merit of SiC base DMOSFET.
The utility model is realized in this way:
A kind of normally-off SiC base DMOSFET device, including SiC epitaxial material substrate, 2D high mobility electrical transmission layer, p
The area well, p+ type ultrashort channel floor, n++ type doped region, p++ type doped region, gate medium, gate electrode contact, source electrode contact, leakage
Electrode contact and insulating material layer, the SiC epitaxial material substrate include that n++ type substrate base, n+ type buffer layer and n-type are floated
Layer is moved, the n+ type buffer layer is located at the upper surface of the n++ type substrate base, and it is slow that the n-type drift layer is located at the n+ type
Rush the upper surface of layer；
The 2D high mobility electrical transmission layer is located at the upper surface of the n-type drift layer, and the area the p well is set to described
Between 2D high mobility electrical transmission layer and the n-type drift layer, and a plurality of areas p well periodic arrangement, adjacent institute
The formation area JFET between the area p well is stated, the two sides of the 2D high mobility electrical transmission layer are successively arranged described from the near to the distant respectively
P+ type ultrashort channel layer, the n++ type doped region and the p++ type doped region, the gate medium cover the 2D high mobility
Electrical transmission layer, the p+ type ultrashort channel layer and n++ type doped region, the gate electrode contact are located at the upper table of the gate medium
Face, the both bounded sides of the p+ type ultrashort channel layer are located at the lower section of gate electrode contact, and the source electrode contact is located at
The upper surface of the n++ type doped region and the p++ type doped region, the insulating material layer cover the gate medium and the grid
Electrode contact, the drain electrode contact are located at the lower surface of the n++ type substrate base.
It further, further include pad metal layer, the pad metal layer covers the insulating material layer, and electric with the source
Pole contact interconnection.
Further, the top in the area the p well is more than the bottom of the 2D high mobility electrical transmission floor, the p
The bottom in the area well is built in the n-type drift layer.
Further, the gate electrode contact is division grid structure, and is not present in the vertical top in the area JFET.
The utility model has the advantages that (1) due to using high mobility electrical transmission layer, so that SiC base DMOSFET device
The JFET transmission resistance of part substantially reduces；(2) p+ type ultrashort channel layer is used, the ditch of SiC base DMOSFET device is further decreased
Road resistance；(3) it due to the self-built potential coupling of high mobility electrical transmission floor and the area p well for burying layer structure, ensure that
SiC base DMOSFET device be normally-off switching device, reduce reverse operation when punch-through breakdown and leakage current；(4) using division
Grid structure reduces the overlapping area of gate electrode contact and drain electrode contact, therefore device has lesser Miller charge.(5)p
The area well length extending transversely is greater than the length of gate medium, and the electric field of gate medium is effectively reduced, improves the reliability of gate medium.
(6) the SiC base DMOSFET device described in is with the higher Ba Lijia figure of merit and bigger compared to traditional DMOSFET device
The HF switch figure of merit.
Detailed description of the invention
The utility model is further described in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the preparation flow figure of the normally-off SiC base DMOSFET device of the utility model.
Fig. 2 is the structural schematic diagram of SiC epitaxial material substrate in the utility model.
Fig. 3 is the structural schematic diagram that 2D high mobility electrical transmission layer is made in the utility model.
Fig. 4 is the structural schematic diagram that the area p well is made in the utility model.
Fig. 5 is the structural schematic diagram that p+ type doped region is made in the utility model.
Fig. 6 is the structural schematic diagram that n++ type doped region and p+ type ultrashort channel layer are made in the utility model.
Fig. 7 is the structural schematic diagram that p++ type doped region is made in the utility model.
Fig. 8 is the structural schematic diagram that gate medium is made in the utility model.
Fig. 9 is the structural schematic diagram that gate electrode contact is made in the utility model.
Figure 10 is the structural schematic diagram that insulating material layer is made in the utility model.
Figure 11 is that source electrode is made in the utility model to contact the structural schematic diagram contacted with drain electrode.
Figure 12 is the structural schematic diagram that pad metal layer is made in the utility model.
Marking in figure indicates: 10, n++ type substrate base, 20, n+ type buffer layer, 30, n-type drift layer, 40,2D high migration
Rate electrical transmission layer, 50, injection masking layer, 60, the area p well, the 70, first side wall exposure mask, 80, p+ type doped region, 81, p+ type it is super
Short channel layer, the 90, second side wall exposure mask, 100, n++ type doped region, 110, p++ type doped region, 120, gate medium, 130, grid electricity
Pole contact, 135, the area JFET, 140, insulating material layer, 150, contact through hole, 160, source electrode contact, 170, drain electrode contact,
180, pad metal layer.
Specific embodiment
Please refer to Fig. 1 to Figure 12, a kind of normally-off SiC base DMOSFET device, including SiC epitaxial material substrate, 2D Gao Qian
Shifting rate electrical transmission floor 40, the area p well 60, p+ type ultrashort channel floor 81, n++ type doped region 100, p++ type doped region 110, grid are situated between
Matter 120, gate electrode contact 130, source electrode contact 160, drain electrode contact 170 and insulating material layer 140, the SiC extension material
Material substrate includes n++ type substrate base 10, n+ type buffer layer 20 and n-type drift layer 30, and the n+ type buffer layer 20 is located at described
The upper surface of n++ type substrate base 10, the n-type drift layer 30 are located at the upper surface of the n+ type buffer layer 20；
The 2D high mobility electrical transmission layer 40 is located at the upper surface of the n-type drift layer 30, and the area the p well 60 is set
Between the 2D high mobility electrical transmission layer 40 and the n-type drift layer 30, and a plurality of 60 periods of the area the p well arrange
Column, form the area JFET 135 between the adjacent area the p well 60, the two sides of the 2D high mobility electrical transmission layer 40 respectively by
It is proximal and distal to be successively arranged the p+ type ultrashort channel layer 81, the n++ type doped region 100 and the p++ type doped region 110, institute
It states gate medium 120 and covers the 2D high mobility electrical transmission layer 40, the p+ type ultrashort channel layer 81 and n++ type doped region
100, the gate electrode contact 130 is located at the upper surface of the gate medium 120, the right and left of the p+ type ultrashort channel layer 81
Boundary is located at the lower section of gate electrode contact 130, and the source electrode contact 160 is located at the n++ type doped region 100 and p+
The upper surface of+type doped region 110, the insulating material layer 140 cover the gate medium 120 and contact 130 with the gate electrode, institute
State the lower surface that drain electrode contact 170 is located at the n++ type substrate base 10.
Wherein, periodic arrangement is that have certain spacing between the adjacent area p well 60, and the area each p well 60 is by around here
It is arranged away from past certain direction.It is arranged according to doping concentration, n++ type > n+ type > N-shaped > n-type；P++ type > p+ type > p-type.
It further include pad metal layer 180, the pad metal layer 180 covers the insulating material layer 140, and electric with the source
160 interconnection of pole contact.
The top in the area the p well 60 is more than the bottom of the 2D high mobility electrical transmission floor 40, the area the p well 60
Bottom be built in the n-type drift layer 30；The area p well 60 is buried structure.The wherein top in the area p well 60 and 2D high
The upper surface of mobility electrical transmission layer 40 keeps certain spacing, makes 2D high mobility electrical transmission layer 40 at T-type shape.
The gate electrode contact 130 is division grid structure, and is not present in the vertical top in the area JFET 135.One
Splitting bar corresponds to a p+ type ultrashort channel layer 81, the most short horizontal distance range on splitting bar boundary and 135 boundary of the area JFET
It is 0.2-3 μm.
The technical solution of the utility model is from SiC base dual material gate medium interface, MOSFET element conducting resistance, Miller electricity
Lotus etc. comprehensively considers, and proposes a kind of SiC base DMOSFET device with ultrashort channel and division grid structure, and utilization is ultrashort
Channel and two-dimentional (2D) high mobility electrical transmission layer reduce the channel resistance of the device, and utilize splitting bar and the area adjacent p well
Between shielding action, the Miller charge of the device is reduced, to improve the switch conversion ability of SiC base DMOSFET device.
The preparation method of the normally-off SiC base DMOSFET device of the present embodiment, comprising:
Step S1, SiC epitaxial material substrate is cleaned；
Referring to Fig. 2, the SiC epitaxial material substrate in the step S1 includes n++ type substrate base 10, n+ type buffer layer
20 are initially formed with n-type drift layer 30, the n+ type buffer layer 20 in the upper surface of the n++ type substrate base 10, the n-type
Drift layer 30 is re-formed in the upper surface of the n+ type buffer layer 20；
The SiC epitaxial material substrate is carried out being standard cleaning, concrete operations are as follows:
A. it is successively cleaned three times with acetone and EtOH Sonicate, then is rinsed with deionized water.
B. the SiC epitaxial material substrate after organic ultrasonic is put into the concentrated sulfuric acid and hydrogen peroxide solution and at least boils 10min.
C. the SiC epitaxial material substrate for boiling the concentrated sulfuric acid is successively boiled into 15min with No.1 liquid and No. two liquid, then uses deionization
Water is stand-by with being dried with nitrogen after rinsing well；No.1 liquid is the mixed liquor of ammonium hydroxide, hydrogen peroxide and deionized water, by volume ammonia
Shui ︰ Guo Yangization Qing ︰ deionized water=1 ︰, 2 ︰ 5；No. two liquid are the mixed liquor of hydrochloric acid, hydrogen peroxide and deionized water, by volume
Yan Suan ︰ Guo Yangization Qing ︰ deionized water=1 ︰, 2 ︰ 5.
D. the SiC epitaxial material substrate after flushing is put into diluted hydrofluoric acid and impregnates 1min, by volume hydrogen fluoride:
Deionized water=1:3 removes the oxide on its surface, and is cleaned with deionized water, then dry.
Step S2,2D high mobility electrical transmission layer 40 is made in the upper surface of the n-type drift layer 30；
Referring to Fig. 3,2D high mobility electrical transmission layer 40 is two-dimentional homogeneous material or dissimilar materials；Utilize chemical vapor deposition
Two-dimentional homogeneous material or dissimilar materials are grown into the SiC extension after cleaning by long-pending or the methods of physical vapour deposition (PVD) or thin film sputtering
The upper surface of the n-type drift layer 30 of material base, the two-dimentional homogeneous material of growth or dissimilar materials with a thickness of 5-200nm, it is raw
Long two-dimentional homogeneous material or dissimilar materials can be silicon carbide, diamond or graphite or boron nitride or sulfide etc. other
Topological insulating materials, the two-dimentional homogeneous material or dissimilar materials of growth are n-type doping type, ultimately form 2D high mobility fax
Defeated layer 40.
Step S3, it is made between the SiC epitaxial material substrate and the 2D high mobility electrical transmission layer 40 a plurality of
In the area p well 60 of periodic arrangement；
Referring to Fig. 4, being formed sediment using chemical vapor deposition or physical vapour deposition (PVD) on 2D high mobility electrical transmission layer 40
Product mask layer, the mask layer can be SiO2Or Si3N4Or polysilicon or metal substance, utilize reticle A, photoetching figure
Shape forms injection masking layer 50, and using doping methods such as ion implantings, the area p well is made in n-type drift layer 30
60 periodic arrangement of the area 60, a plurality of p well is within n-type drift layer 30, which is buried structure, i.e. p well
The top in area 60 is more than the bottom of 2D high mobility electrical transmission floor 40, and is kept with the upper surface of 2D high mobility electrical transmission layer 40
Certain spacing, the spacing range are 20nm~200nm, and the bottom in the area p well 60 is built in n-type drift layer 30, p well
The doping concentration in area 60 is 5 × 1017cm-3~1 × 1019cm-3。
Step S4, in the 2D high mobility electrical transmission layer 40, p+ type ultrashort channel layer 81 is injected in autoregistration, and forms n
++ type doped region 100；Specially first p+ type doped region 80 is made in doping in the 2D high mobility electrical transmission layer 40, then at institute
It states doping in p+ type doped region 80 and n++ type doped region 100, the n++ type doped region 100 and the 2D high mobility fax is made
P+ type ultrashort channel layer 81 is formed between defeated layer 40.
Fig. 5 and Fig. 6 are please referred to, sub-step S4-1, sub-step S4-2, sub-step S4-3, sub-step S4-4 are specifically included；
Sub-step S4-1, on the basis of having formed injection masking layer 50, utilize chemical vapor deposition or physical vapor
Deposition, deposits secondary exposure mask, the secondary exposure mask can be SiO2Or Si3N4Or polysilicon substance, it etches this and secondary covers
Film, forms the first side wall exposure mask 70, and the first side wall exposure mask 70 can also be obtained by prior arts such as other polysilicon oxidation modes
?.
Sub-step S4-2, the first side wall exposure mask 70 of foundation, using doping methods such as thermal diffusion or ion implantings, in 2D Gao Qian
P+ type doped region 80 is made in doping in shifting rate electrical transmission layer 40, and the doped chemical of the p+ type doped region 80 can be B or Al
Or the acceptor types element such as Ga or Nb, the doping concentration of p+ type doped region 80 are 1 × 1017cm-3~1 × 1019cm-3。
Sub-step S4-3, on the basis of having formed injection masking layer 50 and the first side wall exposure mask 70, utilize chemical gas
Mutually deposition or physical vapour deposition (PVD) deposit exposure mask three times, and exposure mask can be SiO three times for this2Or Si3N4Or polysilicon substance,
The exposure mask three times is etched, the second side wall exposure mask 90 is formed, which can also pass through other polysilicon oxidation sides
The prior arts such as formula obtain.
Sub-step S4-4, it is mixed using doping methods such as thermal diffusion or ion implantings in p+ type according to the second side wall exposure mask 90
N++ type doped region 100 is made in doping in miscellaneous area 80, and the doped chemical of n++ type doped region 100 can be applied for N or P or As or Sb etc.
Principal mode element, the doping concentration of n++ type doped region 100 are 1 × 1019cm-3~1 × 1021cm-3.The p+ type ultrashort channel layer of formation
81 lateral lengths are 0.1-0.3 μm.
Step S5, p++ type doped region 110 is made in the n++ type doped region 100；
Referring to Fig. 7, specifically including sub-step S5-1, sub-step S5-2；
Step S5-1, using chemical vapor deposition or physical vapour deposition (PVD), mask layer is deposited, this mask layer can be
SiO2Or Si3N4Or polysilicon substance, photoetching simultaneously etch this mask layer, form base doping mask layer；
Sub-step S5-2, using doping methods such as thermal diffusion or ion implantings, p is made in doping in n++ type doped region 100
++ the doped chemical of type doped region 110, p++ type doped region 110 can mix for acceptor types element, p++ types such as B or Al or Ga or Nb
The doping concentration in miscellaneous area 110 is 2 × 1019cm-3~1 × 1021cm-3。
Step S6, gate medium 120 is made, the gate medium 120 covers the p++ type doped region 110, the n++ type is mixed
Miscellaneous area 100, the p+ type ultrashort channel floor 81 and the 2D high mobility electrical transmission floor 40；
Referring to Fig. 8, specifically including sub-step S6-1, sub-step S6-2；
Then mask layer in sub-step S6-1, removal step S5, the established substrate surface of standard cleaning activate aforementioned
The area p well 60, n++ type doped region 100 in step, p++ type doped region 110, the Activiation method include using carbon film or AlN
Film covering, SiH4High temperature of the methods of the inhibition at 1200 DEG C~1800 DEG C, under conditions of pressure is 600-700Torr, anneal 10-
60 minutes.
Sub-step S6-2, removal above-mentioned carbon film or AlN film do and sacrifice oxygen processing, and the established substrate of standard cleaning
Surface, using thermal oxide and post-oxidation anneal method, or so dry-oxygen oxidation half an hour under conditions of 600 DEG C~1300 DEG C, and
It anneals 1~3 hour at 600 DEG C~1300 DEG C of temperature and NO atmospheric condition, the annealing atmosphere is not only NO, can also
To be POCl3, H2, N2O, P2O5, Sb+NO etc., final to obtain gate medium 120, which can also be by physically or chemically
The methods of vapor deposition or atomic layer deposition obtain, and gate medium 120 can also be other insulating materials such as SixNy(x, y are element
Than) and Al2O3、AlN、AlON、HfO2Contour k dielectric material and their combination.
Step S7, gate electrode contact 130 is made in the upper surface of the gate medium 120；
In the step S7, the manufactured gate electrode contact 130 is division grid structure, and is not present in adjacent p well
The vertical top in the area JFET 135 between area 60, the both bounded sides of the p+ type ultrashort channel layer are located at the gate electrode and connect
The lower section of touching.
Referring to Fig. 9, specifically including sub-step S7-1, sub-step S7-2；
Sub-step S7-1, using film deposition techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer depositions,
It has been formed on the surface of gate medium 120 and has deposited highly doped polysilicon.
Sub-step S7-2, the etching means such as photo etched mask and physics, chemistry are recycled, such as reactive ion etching (RIE)
Either inductively coupled plasma (ICP) etc., the highly doped polysilicon that dry etching is deposited, finally in the table of gate medium 120
The gate electrode contact 130 of division grid structure, the both bounded sides model of 130 covering ultrashort channel layer of gate electrode contact are formed on face
It encloses, and the leftmost terminal of the gate electrode contact 130 on the left side in figure is in the top of n++ type doped region 100, gate electrode contact
There is certain spacing on the boundary in 130 area right end distance p well 60, this distance is 0.2-3 μm, and gate electrode contact 130 is not deposited
It is the top in the area JFET 135 between the area adjacent p well 60.
Step S8, insulating material layer 140 is made in gate electrode contact 130 and the upper surface of the gate medium 120, then
Contact through hole 150 is formed in the insulating material layer 140 etching, source electrode contact 160 is made in the contact through hole 150,
The source electrode contact 160 is located at the upper surface of the n++ type doped region 100 and the p++ type doped region 110；
Figure 10 and Figure 11 are please referred to, sub-step S8-1, sub-step S8-2, sub-step S8-3 are specifically included；
Sub-step S8-1, using film deposition techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer depositions,
It has been formed on the substrate of gate electrode contact 130 and has deposited insulating material layer 140, the insulating material layer 140 has hardware and software platform table
Face.
Sub-step S8-2, using photolithography patterning, by the etching means such as physics, chemistry, dry etching insulating material layer
140, such as reactive ion etching (RIE) either inductively coupled plasma (ICP), contact through hole 150 is formed, the dry method is carved
The etching gas of erosion can be SF6/O2、NF3/Ar、CF4、CHF3/O2、C4F8/O2Deng combination of gases.
Sub-step S8-3, photolithography patterning, using membrane deposition methods such as electron beam evaporation or sputterings, successively deposit Ni,
The multiple layer metal of Ti, Al, removing form source electrode contact 160, and source electrode contact 160 is located at n++ type doped region 100 and p++ type
The upper surface of doped region 110.
Step S9, drain electrode contact 170 is formed in the lower surface of the n++ type substrate base 10.
Figure 11 is please referred to, is protected in established substrate front resist coating, and remove n++ type substrate base with diluted HF
The oxide layer at 10 back side of piece utilizes the membrane deposition methods such as electron beam evaporation or sputtering overleaf deposited metal, the gold
Belonging to layer can be the metals such as AlTi, Ni, TiW, AlTi or their combination, drain electrode contact 170 be made, then remove positive photoetching
Glue.
Source electrode of annealing under the conditions of 900 DEG C~1100 DEG C of temperature range, nitrogen or argon gas contacts 160, drain electrode
Contact 170, forms it into Ohmic contact.
Step 10, deposited metal are in the surface of the insulating material layer 140, the layer metal interconnection source electrode contact
160, pad metal layer 180 is made.
Please refer to Figure 12, the membrane deposition methods such as deposited by electron beam evaporation or sputtering, in established substrate front deposit compared with
Thick metal layers, interconnection source electrode contact 160, form pad metal layer 180.
The preparation method of the SiC base DMOSFET device for having both high ducting capacity and low Miller charge of the utility model is
2D heterogeneous interface reconfiguration technique, deep-submicron autoregistration based on SiC base DMOSFET device inject doping techniques, activated at
With annealing technology, gate oxide technology and polygate electrodes technology, realize DMOSFET device active area buried layer doping,
Ultrashort channel building and splitting bar production.To improve the gate medium stability and high-voltage breakdown energy of SiC base DMOSFET device
Power improves the turn-off capacity of device, enhances the static on state characteristic and dynamic switching behavior of SiC base DMOSFET device.
The SiC base DMOSFET devices use ultrashort channel layer height and high mobility electrical transmission layer of the utility model, drop significantly
The channel resistance and JFET of low SiC base DMOSFET transmit resistance, while high mobility electrical transmission floor and the area buried layer type p well
Self-built potential coupling guarantees the normal pass characteristic of the device, avoids the punch-through breakdown disadvantage of p+ type ultrashort channel layer.Using point
Split grid structure, when forward conduction, electronics enters 2D high mobility electrical transmission layer along ultrashort channel layer transoid level, and along JFET
Area enters n-type drift layer；When reverse blocking, the area adjacent P well and splitting bar are in harmony shielding action effective protection gate medium certainly,
So that the gate medium electric field of the device substantially reduces, snowslide occurs at the PN junction in device body area.The SiC base of the utility model
DMOSFET device has lower forward conduction resistance and higher reverse blocking capability, and the static state of the device, dynamic duty
Reliability is improved.
Substrate material used by particular embodiments described above is not limited to SiC material, can also include silicon, nitrogen
Change the power electronic semiconductors materials such as gallium, gallium oxide, diamond.It is final when using other semiconductor materials as substrate
The made DMOSFET device for having both high ducting capacity and low Miller charge and preparation method should be included in the utility model
Protection scope within.
It should be noted that the direction term mentioned in embodiment, for example, "upper", "lower", etc., be only the side with reference to attached drawing
To, not be used to limit the protection scope of the utility model.Through attached drawing, identical element is by same or similar appended drawing reference
To indicate.When may cause the understanding to the utility model and cause to obscure, conventional structure or construction will be omitted.
It unless there are known entitled phase otherwise anticipates, the numerical parameter in this specification and appended claims is approximation, energy
The resulting required characteristic changing of content that enough bases pass through the utility model.Specifically, all be used in specification and right
The number of content, reaction condition of composition etc. is indicated in it is required that, it is thus understood that be the term by " about " in all situations
It is modified.Under normal circumstances, express meaning refer to comprising by specific quantity ± 10% variation in some embodiments,
± 5% variation in some embodiments, ± 1% variation in some embodiments, in some embodiments ± 0.5% change
Change.
Particular embodiments described above has carried out into one the purpose of this utility model, technical scheme and beneficial effects
Step is described in detail, it should be understood that being not limited to this foregoing is merely specific embodiment of the utility model
Open, within the spirit and principle of the utility model, any modification, equivalent substitution, improvement and etc. done should be included in
Within the protection scope of the utility model.
Claims (4)
1. a kind of normally-off SiC base DMOSFET device, it is characterised in that: including SiC epitaxial material substrate, 2D high mobility electricity
Transport layer, the area p well, p+ type ultrashort channel floor, n++ type doped region, p++ type doped region, gate medium, gate electrode contact, source electricity
Pole contact, drain electrode contact and insulating material layer, the SiC epitaxial material substrate include n++ type substrate base, n+ type buffer layer
With n-type drift layer, the n+ type buffer layer is located at the upper surface of the n++ type substrate base, and the n-type drift layer is located at institute
State the upper surface of n+ type buffer layer；
The 2D high mobility electrical transmission layer is located at the upper surface of the n-type drift layer, and the area the p well is set to the 2D high
Between mobility electrical transmission layer and the n-type drift layer, and a plurality of areas p well periodic arrangement, the adjacent p
The area JFET is formed between the area well, the two sides of the 2D high mobility electrical transmission layer are successively arranged the p+ type from the near to the distant respectively
Ultrashort channel layer, the n++ type doped region and the p++ type doped region, the gate medium cover the 2D high mobility fax
Defeated layer, the p+ type ultrashort channel layer and n++ type doped region, the gate electrode contact are located at the upper surface of the gate medium,
The both bounded sides of the p+ type ultrashort channel layer are located at the lower section of gate electrode contact, and the source electrode contact is located at described
The upper surface of n++ type doped region and the p++ type doped region, the insulating material layer cover the gate medium and the gate electrode
Contact, the drain electrode contact are located at the lower surface of the n++ type substrate base.
2. a kind of normally-off SiC base DMOSFET device as described in claim 1, it is characterised in that: it further include pad metal layer,
The pad metal layer covers the insulating material layer, and contacts interconnection with the source electrode.
3. a kind of normally-off SiC base DMOSFET device as described in claim 1, it is characterised in that: the top in the area the p well
Portion is more than the bottom of the 2D high mobility electrical transmission layer, and the bottom in the area the p well is built in the n-type drift layer.
4. a kind of normally-off SiC base DMOSFET device as described in claim 1, it is characterised in that: the gate electrode, which contacts, is
Grid structure is divided, and is not present in the vertical top in the area JFET.
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| CN109686792B (en) * | 2019-01-31 | 2024-03-19 | 泰科天润半导体科技（北京）有限公司 | Normally-off SiC-based DMOSFET device and preparation method thereof |
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