CN209417127U - Synchronization signal detection circuit based on FPGA - Google Patents
Synchronization signal detection circuit based on FPGA Download PDFInfo
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- CN209417127U CN209417127U CN201821885523.9U CN201821885523U CN209417127U CN 209417127 U CN209417127 U CN 209417127U CN 201821885523 U CN201821885523 U CN 201821885523U CN 209417127 U CN209417127 U CN 209417127U
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- signal detection
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Abstract
The utility model provides a kind of synchronization signal detection circuit based on FPGA, including the voltage collecting device for measuring starting of static frequency conversion device SFC input side network voltage, voltage collecting device input terminal connects SFC, the voltage signal inputs of voltage collecting device output end connection synchronization signal detection plate SU, the input terminal of on-site programmable gate array FPGA in the synchronous signal output end connection master board of SU, the pressure that the pressure of FPGA adopts guarantor's signal output end connection SU adopt guarantor's signal input part.FPGA adopts information-preserving number according to synchronization signal generation pressure and send to SU, pressure adopts information-preserving number for avoiding the silicon-controlled of triggering SFC bridge side from generating interference to sample circuit, mains voltage signal is not acquired when control machines start, to guarantee the accuracy of synchronization signal detection.The utility model structure is simple, low in cost, reliable performance, is suitable for a wide range of promote the use of.
Description
Technical field
The utility model relates to a kind of synchronization signal detection circuits, more particularly to one kind for realizing starting of static frequency conversion dress
Set the circuit of the synchronization signal detection of SFC input network voltage.
Background technique
Starting of static frequency conversion device SFC is widely used in the fields such as large-scale combustion engine unit and pumped storage machine.It will hair
Motor is used as synchronous motor, provides the power supply of variable voltage and frequency to generator by SFC, while controlling Excitation Adjustment
Device is saved, exciting current appropriate is added to generator amature during startup, to make unit starting.It is defeated to step up SFC
Frequency out, is stepped up rotor speed, to meet the requirement of combustion engine unit raising speed.
The bridge side of starting of static frequency conversion device SFC by Group of Silicon Controlled Rectifier at three phase full bridge controlled rectification circuit, by grid side
AC power source is transformed to DC power supply.When SFC normal output voltage, bridge work is in rectification state, by changing rectifier and trigger
Realize the control to DC voltage and electric current in angle.
The core of bridge control is to generate synchronization signal by measurement grid side ac voltage signal, then further according to same
It walks signal and trigger delay angle generates trigger pulse, trigger three phase full bridge controlled rectification circuit.
Existing sync signal detection apparatus, usually directly send ac voltage signal into master control borad, according to alternating current
It presses through zero point and determines synchronization signal, anti-interference is poor, affects the accuracy of testing result.
Utility model content
The technical problems to be solved in the utility model is how to realize that starting of static frequency conversion device SFC inputs network voltage
The accurate detection of synchronization signal.
In order to solve the above-mentioned technical problem, the technical solution of the utility model is to provide a kind of synchronization signal based on FPGA
Measure loop, it is characterised in that: including the voltage acquisition dress for measuring starting of static frequency conversion device SFC input side network voltage
It sets, voltage collecting device input terminal connects SFC, and voltage collecting device output end connects the voltage signal of synchronization signal detection plate SU
Input terminal, the synchronous signal output end of SU connect the input terminal of the on-site programmable gate array FPGA in master board, FPGA's
The pressure that pressure adopts guarantor's signal output end connection SU adopts guarantor's signal input part.
Preferably, the voltage collecting device is voltage transformer.
Preferably, the voltage collecting device is divider resistance.
Preferably, the power grid three-phase alternating voltage signal of the input side of the SFC accesses SU by voltage collecting device；SU
The synchronization signal of the three-phase alternating voltage signal is generated, and the synchronization signal is sent into the FPGA in master board；FPGA
The start pulse signal that the bridge side of SFC is generated according to the synchronization signal and trigger delay angle, drive the bridge side of SFC can
It controls silicon and generates the DC voltage and electric current needed；FPGA adopts information-preserving number also according to synchronization signal generation pressure and send to SU, and pressure is adopted
Information-preserving number, for avoiding the silicon-controlled of triggering SFC bridge side from generating interference to sample circuit, is not adopted when control machines start
Collect mains voltage signal, to guarantee the accuracy of synchronization signal detection.
Device provided by the invention overcomes the deficiencies in the prior art, synchronizes signal detection by SU, passes through FPGA
Information-preserving number is adopted to pressure to control, enhances the anti-interference of system, realizes starting of static frequency conversion device SFC input power grid electricity
The accurate detection of the synchronization signal of pressure.Apparatus structure is simple, low in cost, reliable performance, is suitable for a wide range of promote the use of.
Detailed description of the invention
Fig. 1 is the synchronization signal detection loop structure schematic diagram provided in this embodiment based on FPGA；
Fig. 2 is that pressure adopts guarantor's signal schematic representation.
Specific embodiment
The present invention will be further illustrated below in conjunction with specific embodiments.
Fig. 1 be the synchronization signal detection loop structure schematic diagram provided in this embodiment based on FPGA, it is described based on
The synchronization signal detection circuit of FPGA includes the voltage acquisition for measuring starting of static frequency conversion device SFC input side network voltage
Device, voltage collecting device input terminal connect starting of static frequency conversion device SFC, and voltage collecting device output end connects synchronization signal
The voltage signal inputs of detection plate SU, the synchronous signal output end of synchronization signal detection plate SU connect the scene in master board
The input terminal of programmable gate array FPGA, the pressure of on-site programmable gate array FPGA, which is adopted, protects signal output end connection synchronization signal inspection
The pressure of drafting board SU adopts guarantor's signal input part.
In the present embodiment, the voltage collecting device for measuring starting of static frequency conversion device SFC input side network voltage is
Voltage transformer pt or divider resistance.
Synchronization signal detection circuit provided in this embodiment based on FPGA is in use, by starting of static frequency conversion device SFC
Input side power grid three-phase alternating voltage signal it is same by the secondary side of voltage transformer pt or divider resistance partial pressure access
Signal detection plate SU is walked, the synchronization signal that synchronization signal detection plate SU generates three-phase alternating voltage signal is sent into master board
On-site programmable gate array FPGA, the touching that on-site programmable gate array FPGA is determined according to the synchronization signal and control algolithm of detection
The start pulse signal that delay angle generates the bridge side of starting of static frequency conversion device SFC is sent out, starting of static frequency conversion device SFC is driven
Bridge side silicon-controlled generation need DC voltage and electric current.On-site programmable gate array FPGA is produced also according to synchronization signal
Raw pressure is adopted information-preserving number and is sent to synchronization signal detection plate SU, and pressure adopts information-preserving number for avoiding the silicon-controlled to adopting of triggering SFC bridge side
Sample circuit generates interference, mains voltage signal is not acquired when control machines start, to ensure that synchronization signal detection
Accuracy.
Wherein, the generation of trigger delay angle is realized by the DSP in master board, according to DC current reference value and actual value
Comparison determine trigger delay angle.
Pressure is adopted information-preserving number and is generated by FPGA, takes shielding sampled signal on trigger pulse head point, and other times carry out
Sampled signal.As shown in Fig. 2, allowing pressure to adopt information-preserving number in head pulse is 0, then synchronization signal detection plate SU is without sampling and to letter
It number is kept；Allowing pressure to adopt information-preserving number in other times is 1, then synchronization signal detection plate SU is sampled.
The above, the only preferred embodiment of the utility model, it is in any form and substantive not to the utility model
On limitation, it is noted that for those skilled in the art, in the premise for not departing from the utility model method
Under, several improvement and supplement can be also made, these are improved and supplement also should be regarded as the protection scope of the utility model.It is all ripe
Professional and technical personnel is known, in the case where not departing from the spirit and scope of the utility model, when using disclosed above
Technology contents and the equivalent variations of a little variation, modification and evolution made, be the equivalent embodiment of the utility model；Together
When, all substantial technologicals according to the utility model to the variation, modification and evolution of any equivalent variations made by above-described embodiment,
In the range of still falling within the technical solution of the utility model.
Claims (3)
1. a kind of synchronization signal detection circuit based on FPGA, it is characterised in that: including for measuring starting of static frequency conversion device
The voltage collecting device of SFC input side network voltage, voltage collecting device input terminal connect SFC, voltage collecting device output end
The voltage signal inputs of synchronization signal detection plate SU are connected, the scene in the synchronous signal output end connection master board of SU can
The input terminal of gate array FPGA is programmed, the pressure that the pressure of FPGA adopts guarantor's signal output end connection SU adopts guarantor's signal input part.
2. a kind of synchronization signal detection circuit based on FPGA as described in claim 1, it is characterised in that: the voltage acquisition
Device is voltage transformer.
3. a kind of synchronization signal detection circuit based on FPGA as described in claim 1, it is characterised in that: the voltage acquisition
Device is divider resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821885523.9U CN209417127U (en) | 2018-11-15 | 2018-11-15 | Synchronization signal detection circuit based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821885523.9U CN209417127U (en) | 2018-11-15 | 2018-11-15 | Synchronization signal detection circuit based on FPGA |
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| CN209417127U true CN209417127U (en) | 2019-09-20 |
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| CN201821885523.9U Active CN209417127U (en) | 2018-11-15 | 2018-11-15 | Synchronization signal detection circuit based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109374951A (en) * | 2018-11-15 | 2019-02-22 | 上海发电设备成套设计研究院有限责任公司 | A kind of synchronization signal detection circuit based on FPGA |
-
2018
- 2018-11-15 CN CN201821885523.9U patent/CN209417127U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109374951A (en) * | 2018-11-15 | 2019-02-22 | 上海发电设备成套设计研究院有限责任公司 | A kind of synchronization signal detection circuit based on FPGA |
| CN109374951B (en) * | 2018-11-15 | 2024-03-19 | 上海发电设备成套设计研究院有限责任公司 | Synchronous signal detection loop based on FPGA |
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