CN209366127U - A kind of motor vehicle brake logic circuit and brake - Google Patents
A kind of motor vehicle brake logic circuit and brake Download PDFInfo
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Abstract
The utility model discloses a kind of motor vehicle brake logic circuit, including speed logic signal conversion chip, apart from logical signal conversion chip and logic gate.The invention also discloses a kind of motor vehicle brakes, including logic circuit.The speed signal that speed acquisition equipment acquires is converted to speed logic signal by speed logic signal conversion chip by the utility model, the distance signal of distance acquisition is passed through and is converted to apart from logical signal conversion chip apart from logical signal, it speed logic signal and is exported apart from logical signal by logic gate logical operation, make the control braking motor braking of brake host, it is calculated without program, the reduction program calculating bring reaction time is poor, and safety is higher, assist driver avoidance.
Description
Technical field
The utility model belongs to field of automotive braking technique, and in particular to a kind of motor vehicle brake logic circuit and system
Dynamic device.
Background technique
Existing motor vehicle brake is all made of foot and goes actively to trample foot pedal, and then brake motor movement is made to drive brake
Piece brake motor-car, but with the complexity that the increase of vehicle, road traffic become, when meeting emergency, artificially slightly dredge
Suddenly be possible to that traffic accident occurs, at this time again by people's foot go actively to trample foot pedal braked it is day after the fair, therefore
It adds auxiliary people on motor vehicle to brake at the first time, motor vehicle automatic brake when emergency without artificially participating in has become
Trend of the times, existing motor vehicle automatic brake are to be crossed using vehicle-mounted all kinds of sensors in garage
The environment of surrounding is incuded in journey at any time, collects data, carries out static state, the identification of dynamic object, detecting and tracking, and combine and lead
Navigate instrument map datum, carry out the operation and analysis of system, ranging and the risk distance prestored be compared, combine speed and
Distance is matched, and the mode of brake is selected, and finally unifies one instruction of output, and complicated algorithm can expend in calculating process
Time, and vehicle is also in continuing traveling, when the result that brake Framework computing goes out is risk data, ability control brake is stopped
Vehicle, since the distance in contingency is short, the time that existing algorithm calculates consuming can miss best braking time, make to life life
At threat；In addition, the vehicle of high speed brakes suddenly, speed is easy to cause to squeeze to human heart, i.e., from being directly reduced to 0 at a high speed
Vehicle safety is set to stop, the impact that heart is subject to also brings along accidental injury.
Utility model content
It is a kind of motor-driven the technical problem to be solved by the utility model is in view of the deficiency of the prior art, provide
Vehicle brake logic circuit, novel in design reasonable, the speed signal that speed acquisition equipment is acquired passes through speed logic signal
Conversion chip is converted to speed logic signal, and the distance signal of distance acquisition is passed through and is converted to apart from logical signal conversion chip
It apart from logical signal, speed logic signal and is exported apart from logical signal by logic gate logical operation, makes brake host control
Braking motor braking processed, calculates without program, and the reduction program calculating bring reaction time is poor, convenient for promoting the use of.
In order to solve the above technical problems, the technical solution adopted in the utility model is: a kind of motor vehicle brake logic electricity
Road, comprising:
Speed logic signal conversion chip, for receiving the speed signal of speed acquisition equipment acquisition；
Apart from logical signal conversion chip, for receiving the distance signal of distance acquisition equipment acquisition；
Logic gate, signal for being exported to speed logic signal conversion chip and described apart from logical signal conversion chip
The signal of output carries out logical operation, driving motor vehicle brake braking.
Above-mentioned a kind of motor vehicle brake logic circuit, it is characterised in that: described apart from logical signal conversion chip packet
It includes for receiving the closely short distance logical signal conversion chip of the distance signal of acquisition equipment acquisition and for receiving long distance
The remote logical signal conversion chip of distance signal from acquisition equipment acquisition.
A kind of above-mentioned motor vehicle brake logic circuit, it is characterised in that: the logic gate include the first logic gate and
First output end of the second logic gate, the output end of short distance logical signal conversion chip and speed logic signal conversion chip with
The input terminal of first logic gate connects, the output end of remote logical signal conversion chip and speed logic signal conversion chip
Second output terminal is connect with the input terminal of the second logic gate, the output end of the output end of the first logic gate and the second logic gate with
The input terminal of brake host connects.
Above-mentioned a kind of motor vehicle brake logic circuit, it is characterised in that: the speed logic signal conversion chip
The quantity of the output end of the quantity and short distance logical signal conversion chip of first output end is N number of, wherein N is positive integer；
The quantity of the second output terminal of the speed logic signal conversion chip and remote logical signal conversion chip
The quantity of output end is U, wherein U is positive integer.
Above-mentioned a kind of motor vehicle brake logic circuit, it is characterised in that: first logic gate includes N number of first patrolling
AND gate is collected, when N is greater than 1, first logic gate further includes N-1 the first logic OR gates；
Second logic gate includes U the second logic AND doors；When U is greater than 1, second logic gate further includes U-1
A second logic OR gate.
Above-mentioned a kind of motor vehicle brake logic circuit, it is characterised in that: first logic gate includes N number of first patrolling
NOR gate is collected, when N is greater than 1, first logic gate further includes N-1 third logic OR gate；
Second logic gate includes U the second logic NOR gate, and when U is greater than 1, second logic gate further includes U-1
A 4th logic OR gate.
The utility model additionally provides a kind of motor vehicle brake, including brake host and braking motor, feature exist
In: it further include above-mentioned motor vehicle brake logic circuit.By the motor vehicle brake, automatically controls motor vehicle and encountering tightly
It actively brakes when anxious situation, safety is higher, assist driver avoidance.
Compared with the prior art, the utility model has the following advantages:
1, the utility model motor vehicle brake logic circuit is adopted speed by setting speed logic signal conversion chip
The speed signal of collection equipment acquisition is converted to speed logic signal by speed logic signal conversion chip；It is patrolled by the way that distance is arranged
Signal conversion chip is collected, the distance signal of distance acquisition equipment acquisition is passed through and is converted to distance apart from logical signal conversion chip
Logical signal, signal conversion is simple, quick, reliable, convenient for promoting the use of.
2, the utility model motor vehicle brake logic circuit is patrolled speed logic signal and distance by setting logic gate
It collects signal and carries out logical operation, quickly filter out useful signal, signal output speed is fast, reliable and stable without complicated algorithm.
3, the utility model motor vehicle brake automatically controls motor vehicle and is in case of emergency actively braking, safety
It is higher, assist driver avoidance, convenient for promoting the use of.
In conclusion the utility model is novel in design rationally, the speed signal that speed acquisition equipment is acquired passes through speed
Logical signal conversion chip is converted to speed logic signal, and the distance signal of distance acquisition is passed through and converts core apart from logical signal
Piece is converted to apart from logical signal, speed logic signal and is exported apart from logical signal by logic gate logical operation, makes to brake
The control braking motor braking of device host, calculates without program, and the reduction program calculating bring reaction time is poor, and safety is higher,
Assist driver avoidance, convenient for promoting the use of.
Below by drawings and examples, the technical solution of the utility model is described in further detail.
Detailed description of the invention
Fig. 1 is the schematic block circuit diagram of the utility model brake.
Fig. 2 is the circuit diagram of the utility model embodiment 1.
Fig. 3 is the circuit diagram of the utility model embodiment 2.
Description of symbols:
1-closely acquires equipment；2-remote capture equipment；3-speed acquisition equipment；
4-short distance logical signal conversion chips；5-remote logical signal conversion chips；
6-speed logic signal conversion chips；7-the first logic gate；
8-the second logic gate；9-brake hosts；10-braking motors.
Specific embodiment
Embodiment 1
A kind of motor vehicle brake logic circuit as depicted in figs. 1 and 2, comprising:
Speed logic signal conversion chip 6, for receiving the speed signal of the acquisition of speed acquisition equipment 3；
Apart from logical signal conversion chip, for receiving the distance signal of distance acquisition equipment acquisition；
Logic gate, signal for exporting to speed logic signal conversion chip 6 and described converts core apart from logical signal
The signal of piece output carries out logical operation, driving motor vehicle brake braking.
In the present embodiment, it is described apart from logical signal conversion chip include for receive closely acquisition equipment 1 acquire
The short distance logical signal conversion chip 4 of distance signal and for receive remote capture equipment 2 acquisition distance signal it is remote
Apart from logical signal conversion chip 5.
In the present embodiment, the quantity and short distance logic of the first output end of the speed logic signal conversion chip 6 are believed
The quantity of the output end of number conversion chip 4 is N number of, wherein N is positive integer；
The quantity of the second output terminal of the speed logic signal conversion chip 6 and remote logical signal conversion chip 5
The quantity of output end be U, wherein U is positive integer.
It should be noted that data input module is arranged in the signal input part in speed logic signal conversion chip 6, pass through
Data input module stores M pre-set velocity section, M pre-set velocity section in speed logic signal conversion chip 6 in advance
Pre-set velocity value it is different, wherein M be positive integer and M=N+U, and for each pre-set velocity section be equipped with speed patrol
Collect the pin output on signal conversion chip 6, wherein M pre-set velocity section includes N number of default low speed section and U
N number of first output end of default high-velocity section, N number of default low speed section and speed logic signal conversion chip 6 corresponds, U
A default high-velocity section and U second output terminal of speed logic signal conversion chip 6 correspond；Turn apart from logical signal
The signal input part for changing chip is also provided with data input module, is converting core apart from logical signal in advance by data input module
M pre-determined distance section is stored in piece, the pre-determined distance value of M pre-determined distance section is different, and for each preset away from
Pin output on logical signal conversion chip with a distance from section outfit, M pre-determined distance section include N number of default short distance
Section and U are preset remote section, N number of output end of N number of default short distance section and short distance logical signal conversion chip 4
It corresponds, U are preset the U output end one-to-one correspondence of remote section and remote logical signal conversion chip 5.
It should be noted that the speed signal by speed greater than 50km/h is considered as high speed signal, speed acquisition equipment 3 is acquired
High speed signal when being input to speed logic signal conversion chip 6, high speed signal is located in some default high-velocity section, will be fast
Speed signal of the degree no more than 50km/h is considered as low speed signal, and the low speed signal that speed acquisition equipment 3 acquires is input to speed and patrols
When collecting signal conversion chip 6, high speed signal is located in some default low speed section.
It should be noted that the distance signal by distance greater than 15m is considered as distant signal, remote capture equipment 2 is adopted
When the distant signal of collection is input to remote logical signal conversion chip 5, it is default remote that distant signal is located at some
In section, the distance signal by distance no more than 15m is considered as short distance signal, closely acquires the short distance letter that equipment 1 acquires
When number being input to short distance logical signal conversion chip 4, short distance signal position is preset in short distance section in some.
In actual use, short distance logical signal conversion chip 4, remote logical signal conversion chip 5 and speed logic
Signal conversion chip 6 is DSP family chip or ARM family chip, in actual use, if DSP family chip or ARM series core
Piece pin, which meets, uses needs, short distance logical signal conversion chip 4, remote logical signal conversion chip 5 and speed logic
Signal conversion chip 6 can be concentrated use in a chip and complete signal conversion.
It should be noted that radar range finding module can the obstacle distance of quick detection motor vehicle nearby, for remote
Obstacle distance detection efficient it is low, ADAS drive assistor using image processing techniques obtain range data, for closely
Obstacle distance detection, data processing complex, ranging efficiency is low, high for remote obstacle distance detection efficient, because
This, it is preferred that closely acquisition equipment 1 uses radar range finding module, and remote capture equipment 2 drives assistor using ADAS,
Speed acquisition equipment 3 uses OBD velocity-measuring system.
In the present embodiment, the logic gate includes the first logic gate 7 and the second logic gate 8, the conversion of short distance logical signal
The output end of chip 4 and the first output end of speed logic signal conversion chip 6 are connect with the input terminal of the first logic gate 7, far
The second output terminal and the second logic gate 8 of output end and speed logic signal conversion chip 6 apart from logical signal conversion chip 5
Input terminal connection, input terminal of the output end of the output end of the first logic gate 7 and the second logic gate 8 with brake host 9
Connection.
It should be noted that motor vehicle is at low speeds, directly brake stop stop the impact caused by human body influence it is smaller,
And at high speeds, directly brake stops and stops causing to squeeze to human heart, even if vehicle safety stops, impact that heart is subject to
Accidental injury is also brought along, therefore, logic gate includes that the purpose of the first logic gate 7 and the second logic gate 8 is to be in motor vehicle
The case where low speed and motor vehicle are in high speed distinguishes, using the first logic gate 7 for generating the driving control system of brake host 9
The driving signal of dynamic 10 emergency brake of motor, realizes motor vehicle at low speeds, the purpose stopped of directly braking；Using the second logic
Door 8 controls the driving signal of 10 points of braking motor brakes for generating driving brake host 9, is stopped by steps point and realizes interval
Property brake, make brake of motor-driven vehicle exist buffering, damage will not be brought to people and vehicle, safety is higher.
In the present embodiment, first logic gate 7 includes N number of first logic AND door, and when N is greater than 1, described first is patrolled
Collecting door 7 further includes N-1 the first logic OR gates；
Second logic gate 8 includes U the second logic AND doors；When U is greater than 1, second logic gate 8 further includes
U-1 the second logic OR gates.
It should be noted that the first logic gate 7 includes N number of first logic AND door and the second logic gate 8 includes U second
The purpose of logic AND door is to make short distance logical signal conversion chip 4, remote logical signal conversion chip 5 and speed logic
The output logical one signal of signal conversion chip 6 is useful signal, and output logical zero signal is invalid signals.
In actual use, when N takes 1, in first logic gate 7 be not present the first logic OR gate, only one first
The second logic OR gate, only second logic is not present similarly when U takes 1 in logic AND door in second logic gate 8
AND gate.
The present embodiment is in use, as shown in Fig. 2, preferred speed logic signal conversion chip 6 uses chip IC 1, utilization
The IO0 pin of chip IC 1 receives the speed for the motor vehicle that speed acquisition equipment 3 acquires, and 13 default speed are stored in chip IC 1
Spend section, 13 pre-set velocity sections be respectively (0,5km/h], (5km/h, 10km/h], (10km/h, 20km/h], (20km/
h,30km/h]、(30km/h,40km/h]、(40km/h,50km/h]、(50km/h,60km/h]、(60km/h,70km/h]、
(70km/h, 80km/h], (80km/h, 90km/h], (90km/h, 100km/h], (100km/h, 110km/h] and (110km/h,
120km/h], wherein (0,5km/h], (5km/h, 10km/h], (10km/h, 20km/h], (20km/h, 30km/h], (30km/
H, 40km/h] and (40km/h, 50km/h] it is that low speed presets section, (50km/h, 60km/h], (60km/h, 70km/h],
(70km/h, 80km/h], (80km/h, 90km/h], (90km/h, 100km/h], (100km/h, 110km/h] and (110km/h,
120km/h] be high speed preset section, chip IC 1 IO1 pin output pre-set velocity section (0,5km/h] logical signal, core
Piece IC1 IO2 pin output pre-set velocity section (5km/h, 10km/h] logical signal, the IO3 pin output of chip IC 1 is pre-
If speed sectors (10km/h, 20km/h] logical signal, chip IC 1 IO4 pin output pre-set velocity section (20km/h,
30km/h] logical signal, chip IC 1 IO5 pin output pre-set velocity section (30km/h, 40km/h] logical signal,
Chip IC 1 IO6 pin output pre-set velocity section (40km/h, 50km/h] logical signal, the IO7 pin of chip IC 1 is defeated
Out pre-set velocity section (50km/h, 60km/h] logical signal, the IO8 pin of chip IC 1 exports pre-set velocity section
(60km/h, 70km/h] logical signal, chip IC 1 IO9 pin output pre-set velocity section (70km/h, 80km/h] patrol
Volume signal, chip IC 1 IO10 pin output pre-set velocity section (80km/h, 90km/h] logical signal, chip IC 1
IO11 pin export pre-set velocity section (90km/h, 100km/h] logical signal, the IO12 pin output of chip IC 1 is default
Speed sectors (100km/h, 110km/h] logical signal, the IO13 pin of chip IC 1 exports pre-set velocity section (110km/
H, 120km/h] logical signal；
Preferred short distance logical signal conversion chip 4 uses chip IC 2, receives low coverage using the IO0 pin of chip IC 2
With a distance from the short distance barrier that acquisition equipment 1 acquires, 6 short distances are stored in chip IC 2 and preset section, 6 low coverages
From default section be respectively (0,1.2m], (1.2m, 2m], (2m, 3.5m], (3.5m, 7m], (7m, 10m] and (10m, 15m], core
The IO1 pin output of piece IC2 closely preset section (0,1.2m] logical signal, the IO2 pin of chip IC 2 exports closely
Default section (1.2m, 2m] logical signal, the IO3 pin output of chip IC 2 closely preset section (2m, 3.5m] logic
Signal, the IO4 pin output of chip IC 2 closely preset section (3.5m, 7m] logical signal, the IO5 pin of chip IC 2 is defeated
Out closely preset section (7m, 10m] logical signal, chip IC 2 IO6 pin output closely preset section (10m,
15m] logical signal, remote logical signal conversion chip 5 used chip IC 3, received using the IO0 pin of chip IC 3 remote
The distance for the long-distance barrier object that distance acquisition equipment 2 acquires stores 7 default sections at a distance in chip IC 3, and 7 remote
Distance preset section be respectively (15m, 40m], (40m, 50m], (50m, 58m], (58m, 65m], (65m, 72m], (72m, 79m]
(79m, 86m], the remote default section of the IO1 pin of chip IC 3 output (15m, 40m] logical signal, chip IC 3
The remote default section of IO2 pin output (40m, 50m] logical signal, the IO3 pin of chip IC 3 exports remote preset areas
Section (50m, 58m] logical signal, chip IC 3 the remote default section of IO4 pin output (58m, 65m] logical signal,
Chip IC 3 the remote default section of IO5 pin output (65m, 72m] logical signal, the IO6 pin output of chip IC 3 is remote
Distance preset section (72m, 79m] logical signal, chip IC 3 the remote default section of IO7 pin output (79m, 86m]
Logical signal；
Logic gate includes 6 the first logic AND doors, 5 the first logic OR gates, 7 the second logic AND doors and 6 second
Logic OR gate, 6 the first logic AND doors are respectively the first logic AND door A1, the first logic AND door A2, the first logic AND door
A3, the first logic AND door A4, the first logic AND door A5 and the first logic AND door A6,5 the first logic OR gates are respectively first
Logic OR gate C1, the first logic OR gate C2, the first logic OR gate C3, the first logic OR gate C4 and the first logic OR gate C5,7
Two logic AND doors are respectively the second logic AND door B1, the second logic AND door B2, the second logic AND door B3, the second logic AND
Door B4, the second logic AND door B5, the second logic AND door B6 and the second logic AND door B7,6 the second logic OR gates are respectively the
Two logic OR gate D1, the second logic OR gate D2, the second logic OR gate D3, the second logic OR gate D4, the second logic OR gate D5 and
Two logic OR gate D6；
Brake host 9 indicates that host U1 reserves two pins using host U1, and the IO1 pin of host U1 is brake
The motor vehicle emergency brake signal input part of host 9, the IO2 pin of host U1 are that the motor vehicle point brake signal of brake host 9 inputs
End.
When speed acquisition equipment 3 acquire motor vehicle speed be 25km/h when, fall into pre-set velocity section (20km/h,
30km/h] in, therefore, the IO4 pin of chip IC 1 exports logical one signal, IO1, IO2, IO3, IO5~IO13 of chip IC 1
Pin exports logical zero signal, and when closely acquisition equipment 1 collects distance signal and foreshortens to 7m at this time, the IO1 of host U1
Pin is logical one signal, and driving brake host 9 controls 10 emergency brake of braking motor to stopping；
When the distance apart from barrier of distance acquisition equipment acquisition is greater than 7m, automobile safety.
When the speed for the motor vehicle that speed acquisition equipment 3 acquires is 75km/h, 75km/h falls into pre-set velocity section
(70km/h, 80km/h] in, therefore, the IO9 pin of chip IC 1 exports logical one signal, IO1~IO8, the IO10 of chip IC 1
~IO13 pin exports logical zero signal；
When remote capture equipment 2 collects distance signal, and the long-distance barrier object of the acquisition of remote capture equipment 2
When Distance Shortened is to 58m, the IO3 pin of chip IC 3 exports logical one signal, the IO1 of chip IC 3, IO2, IO4~IO7 pin
Logical zero signal is exported, at this point, the IO2 pin of host U1 is logical one signal, driving brake host 9 controls braking motor
10 points of brakes；
When the collected distance signal of remote capture equipment 2 is greater than 58m, automobile safety；
Chip IC 1, chip IC 2 and chip IC 3 are all made of DSP family chip or ARM family chip.
A kind of motor vehicle brake of the present embodiment, including brake host 9 and braking motor 10, further include the present embodiment one
Kind motor vehicle brake logic circuit.
Embodiment 2
As shown in figures 1 and 3, the present embodiment is unlike the first embodiment: in the present embodiment, first logic gate 7 is wrapped
N number of first logic NOR gate is included, when N is greater than 1, first logic gate 7 further includes N-1 third logic OR gate；
Second logic gate 8 includes U the second logic NOR gate, and when U is greater than 1, second logic gate 8 further includes
U-1 the 4th logic OR gates.
It should be noted that the first logic gate 7 includes N number of first logic NOR gate and the second logic gate 8 includes U second
The purpose of logic NOR gate is to make short distance logical signal conversion chip 4, remote logical signal conversion chip 5 and speed logic
The output logical zero signal of signal conversion chip 6 is useful signal, and output logical one signal is invalid signals.
The present embodiment is in use, as shown in figure 3, the logic gate includes 6 the first logic NOR gate, 5 third logics
OR, 7 the second logic NOR gate and 6 the 4th logic OR gates, 6 the first logic NOR gate be respectively the first logic NOR gate E1,
First logic NOR gate E2, the first logic NOR gate E3, the first logic NOR gate E4, the first logic NOR gate E5 and the first logic NOR
Door E6,5 third logic OR gates are respectively that third logic OR gate G1, third logic OR gate G2, third logic OR gate G3, third are patrolled
OR G4 and third logic OR gate G5 are collected, 7 the second logic NOR gate are respectively the second logic NOR gate F1, the second logic NOR gate
F2, the second logic NOR gate F3, the second logic NOR gate F4, the second logic NOR gate F5, the second logic NOR gate F6 and the second logic
NOR gate F7,6 the 4th logic OR gates are respectively the 4th logic OR gate H1, the 4th logic OR gate H2, the 4th logic OR gate H3,
Four logic OR gate H4, the 4th logic OR gate H5 and the 4th logic OR gate H6；
When speed acquisition equipment 3 acquire motor vehicle speed be 25km/h when, fall into pre-set velocity section (20km/h,
30km/h] in, therefore, the IO4 pin of chip IC 1 exports logical zero signal, IO1, IO2, IO3, IO5~IO13 of chip IC 1
Pin exports logical one signal, and when closely acquisition equipment 1 collects distance signal and foreshortens to 7m at this time, chip IC 2
IO4 pin exports logical zero signal, and the IO4 pin output logical zero signal of chip IC 2 and the IO4 pin of chip IC 1 export
Logical zero signal is logical one signal after the first logic NOR gate E4, and therefore, the IO1 pin of host U1 is logical one letter
Number, driving brake host 9 controls 10 emergency brake of braking motor to stopping；
When the distance apart from barrier of distance acquisition equipment acquisition is greater than 7m, automobile safety.
When the speed for the motor vehicle that speed acquisition equipment 3 acquires is 75km/h, 75km/h falls into pre-set velocity section
(70km/h, 80km/h] in, therefore, the IO9 pin of chip IC 1 exports logical zero signal, IO1~IO8, the IO10 of chip IC 1
~IO13 pin exports logical one signal；
When remote capture equipment 2 collects distance signal, and the long-distance barrier object of the acquisition of remote capture equipment 2
When Distance Shortened is to 58m, the IO3 pin of chip IC 3 exports logical zero signal, the IO1 of chip IC 3, IO2, IO4~IO7 pin
Logical one signal is exported, the IO3 pin output logical zero signal of chip IC 3 and the IO9 pin of chip IC 1 export logical zero
Signal is logical one signal after the first logic NOR gate F3, at this point, the IO2 pin of host U1 is logical one signal, driving
Brake host 9 controls 10 points of braking motor brakes；
When the collected distance signal of remote capture equipment 2 is greater than 58m, automobile safety.
A kind of motor vehicle brake of the present embodiment, including brake host 9 and braking motor 10, further include the present embodiment one
Kind motor vehicle brake logic circuit.
The utility model is converted to Digital Logic letter by speed acquisition equipment 3 and apart from two item datas that acquisition equipment acquires
Number, the driving signal of host U1 is obtained using logic gate, and then realize the braking to braking motor 10, calculate, subtract without program
Few program calculating bring reaction time is poor, and safety is higher, assist driver avoidance, and using effect is good.
The above is only the preferred embodiment of the utility model, not imposes any restrictions to the utility model, all
According to any simple modification to the above embodiments of the utility model technical spirit, change and equivalent structural changes, still
Belong in the protection scope of technical solutions of the utility model.
Claims (7)
1. a kind of motor vehicle brake logic circuit, it is characterised in that: include:
Speed logic signal conversion chip (6), for receiving the speed signal of speed acquisition equipment (3) acquisition；
Apart from logical signal conversion chip, for receiving the distance signal of distance acquisition equipment acquisition；
Logic gate, signal for exporting to speed logic signal conversion chip (6) and described apart from logical signal conversion chip
The signal of output carries out logical operation, driving motor vehicle brake braking.
2. a kind of motor vehicle brake logic circuit described in accordance with the claim 1, it is characterised in that: described apart from logical signal
Conversion chip includes the short distance logical signal conversion chip for receiving the closely distance signal of acquisition equipment (1) acquisition
(4) the remote logical signal conversion chip (5) of the distance signal and for receiving remote capture equipment (2) acquisition.
3. a kind of motor vehicle brake logic circuit according to claim 2, it is characterised in that: the logic gate includes the
One logic gate (7) and the second logic gate (8), the output end and speed logic signal of short distance logical signal conversion chip (4) turn
The first output end for changing chip (6) is connect with the input terminal of the first logic gate (7), remote logical signal conversion chip (5)
The second output terminal of output end and speed logic signal conversion chip (6) is connect with the input terminal of the second logic gate (8), and first patrols
The output end for collecting door (7) is connect with the input terminal of brake host (9) with the output end of the second logic gate (8).
4. a kind of motor vehicle brake logic circuit described in accordance with the claim 3, it is characterised in that: the speed logic signal
The quantity of the output end of the quantity and short distance logical signal conversion chip (4) of first output end of conversion chip (6) is N
It is a, wherein N is positive integer；
The quantity and remote logical signal conversion chip (5) of the second output terminal of the speed logic signal conversion chip (6)
The quantity of output end be U, wherein U is positive integer.
5. a kind of motor vehicle brake logic circuit according to claim 4, it is characterised in that: first logic gate
It (7) include N number of first logic AND door, when N is greater than 1, first logic gate (7) further includes N-1 the first logic OR gates；
Second logic gate (8) includes U the second logic AND doors；When U is greater than 1, second logic gate (8) further includes
U-1 the second logic OR gates.
6. a kind of motor vehicle brake logic circuit according to claim 4, it is characterised in that: first logic gate
It (7) include N number of first logic NOR gate, when N is greater than 1, first logic gate (7) further includes N-1 third logic OR gate；
Second logic gate (8) includes U the second logic NOR gate, and when U is greater than 1, second logic gate (8) further includes
U-1 the 4th logic OR gates.
7. a kind of motor vehicle brake, including brake host (9) and braking motor (10), it is characterised in that: further include such as power
Benefit requires brake logic circuit described in any claim in 1-6.
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| CN201821552797.6U CN209366127U (en) | 2018-09-21 | 2018-09-21 | A kind of motor vehicle brake logic circuit and brake |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821552797.6U CN209366127U (en) | 2018-09-21 | 2018-09-21 | A kind of motor vehicle brake logic circuit and brake |
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