CN209134310U - A kind of synchronous commutating control circuit - Google Patents
A kind of synchronous commutating control circuit Download PDFInfo
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- CN209134310U CN209134310U CN201821860870.6U CN201821860870U CN209134310U CN 209134310 U CN209134310 U CN 209134310U CN 201821860870 U CN201821860870 U CN 201821860870U CN 209134310 U CN209134310 U CN 209134310U
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Abstract
The utility model discloses a kind of synchronous commutating control circuits, it is detected in erasing time T and output voltage of each switch periods to converter, then erasing time T is exported into synchronous rectification logic circuit, and the result that output voltage and setting value are compared is exported into synchronous rectification logic circuit；Synchronous rectification logic circuit generates the conducting of control devices and cut-off signals according to erasing time T and output voltage and the setting value result being compared, and the signal is exported into driving circuit, driving circuit is connected according to devices and cut-off signals, devices conducting and shutdown, the utility model is driven to be able to achieve different capacity grade power-supply system and can work normally within the scope of total temperature.
Description
Technical field
The utility model relates to a kind of synchronous commutating control circuits, in particular to apply in the same of secondary side feedback control occasion
Walk rectifier control circuit.
Background technique
In the primary-side-control scheme of inverse-excitation type isolated converter, need to feed back output voltage or current information to primary side control
Device processed realizes closed-loop control.Common feedback technique has secondary side feedback and primary side feedback.Wherein, the task of secondary side feedback is by device
The isolated amplifier of TL431, optocoupler and additional device composition are completed.The output voltage and reference voltage of converter pass through
TL431 provides error signal after comparing amplification, which flows through the input terminal of optocoupler in a manner of electric current, optocoupler it is defeated
Outlet extracts electric current from the port primary controller FB and generates corresponding error voltage, which is used to adjust accounting for for primary side power tube
Empty ratio, thus by the output voltage stabilization of converter in setting value.This feedback technique have the characteristics that it is with high accuracy, but it is above-mentioned
TL431, optocoupler, additional device etc. increase the space of changer system plate, and optocoupler cannot work at high temperature, and are easy to old
Change.
In contrast, primary side feedback technology (PSR) does not have secondary side feedback device, only passes through the voltage in detection auxiliary winding
To obtain the information of converter output voltage.Because the voltage in auxiliary winding is proportional to the voltage on vice-side winding, specifically
For the turn ratio of winding, then can be adjusted according to duty ratio of the voltage in auxiliary winding to power tube, so that converter
Output voltage stabilization is in setting value.However, primary side feedback have the defects that it is intrinsic: the 1. influence by rectifying device pressure drop, institute
Adopting the voltage in auxiliary winding is not converter output voltage truly；2. by auxiliary winding and vice-side winding circle
The influence of ratio, there are a degree of variations with production technology for this turn ratio；3. being influenced by primary side sample circuit, primary-side-control
Device can not accurately sample the voltage of auxiliary winding.Therefore, using the converter output voltage precision of primary side feedback technology
It is limited.
The Chinese invention patent application of Publication No. CN105610306A is directed to the deficiency of above-mentioned feedback technique, proposes one
Kind secondary side feedback control method shown in FIG. 1.Specifically, the output voltage of secondary controller oversampled converter and and benchmark
Voltage is compared by comparator, and comparison result reflects output voltage in the below or above of benchmark；Secondary controller
Two kinds of different resistance states for selecting switch unit according to the result of the comparison, so that feedback information is pressurized in the form of changing pressure drop
On vice-side winding；Vice-side winding voltage reflection is to auxiliary winding, voltage change in primary side controller detects auxiliary winding, to sentence
Disconnected converter output voltage is higher than benchmark or is lower than benchmark；If converter output voltage is higher than benchmark, Cycle by Cycle reduces primary side
Switching tube opens duty ratio, until detecting output voltage lower than benchmark, conversely, then Cycle by Cycle increases opening for primary side switch pipe
Logical duty ratio loops back and forth like this, until detecting that output voltage is higher than benchmark by output voltage stabilization in setting value.
The secondary side resistance state variation that the Chinese invention patent application of Publication No. CN105610306A proposes is to encode, primary side
Detecting voltage change is to decode.Cataloged procedure occurs in degaussing phase, and erasing current generates pressure drop in different resistance states and adds
Onto vice-side winding, the impedance difference of two kinds of resistance states is bigger, poor bigger, the better detection of primary controller of two kinds of pressure drops.Primary side
Detection method be by this week sampling auxiliary winding voltage compared with the last period, if bigger than the last period, illustrate pair
While high-impedance state has been selected, conversely, being then low resistance state.Since the entire control program that patent proposes can make the output electricity of converter
Press there are certain low-frequency ripples will be in primary side when then the output voltage variation in two neighboring period reaches the threshold value of setting
The judgement for causing mistake, so that loop is out of hand.In order to improve the reliability of primary side detection, in application for a patent for invention
On the basis of CN105610306A, the Chinese invention patent application of a Publication No. CN107612334A is produced, it passes through
It detects in the same period, whether the voltage FA after auxiliary winding partial pressure has a voltage rate of rise in erasing time section
Judge whether output voltage is higher or relatively low, as shown in Fig. 2, this method can be used in patent of invention CN105610306A
Embodiment two and four, but for embodiment third is that invalid, because the rising that each period can occur at least once is oblique
Rate, in practical applications, embodiment only pass through second is that by not opening devices when output voltage is higher
External diode rectifies, and has one apparent the disadvantage is that at high cost and low efficiency, example IV are by series connection one in this way
A diode is realized, is equally low efficiency, at high cost, so only will use the mode of embodiment three in actual use, this
Kind mode is not need external any additional rectifying device, it is only necessary to the scheme that a devices can be realized,
The generation for realizing secondary side feedback signal in different current point shutdowns by synchronous rectification MOS pipe, is then transmitted by transformer
Come over to reflect on auxiliary winding, finally be received by primary side chip, but the program is in application for a patent for invention Publication No.
All none can be good at realizing primary side that secondary side controls in the Chinese invention of CN105610306A and CN107612334A
Detection scheme.
It is come out in order to which secondary side feedback control program is realized in an optimal manner, needs to cooperate suitable primary side signal detection
Circuit, therefore on the basis of the Chinese invention of application for a patent for invention Publication No. CN105610306A and CN107612334A,
Application number of invention patent is that 201811065698.X proposes a kind of new primary side detection circuit, as shown in figure 3, to patented technology
Concrete application is extended,
Application number of invention patent is the concrete principle of 201811065698.X are as follows:
When the output voltage in secondary side feedback control circuit is higher than setting value, it is higher to be detected output voltage
The control circuit on pair side can control devices and just turn off metal-oxide-semiconductor when secondary winding current is larger later, remaining
Electric current passes through the body diode of devices, because pressure drop caused by the pressure drop ratio Rds (on) of diode is big, meeting
Vice-side winding voltage is increased, a rate of rise occurs, vice-side winding voltage is reflected by the coupling of transformer according to the turn ratio
To auxiliary winding, the then input sample delay circuit after divider resistance divides, when this rate of rise is come
Finish the sampling shielding time, so rising edge and failing edge decision circuitry are in place, rising edge decision circuitry can be detected
One rising edge generates, and the rising edge decision circuitry also needs detected amplitude, when voltage change amplitude reaches setting
Value VT1 then exports a high-level control signal Vctrl-1, and time detection circuit receives high-level control signal Vctrl-1
After start timing, not-time if VT1 is not achieved in voltage change amplitude, timing time is denoted as Tx, at this time Tx be 0, when secondary side disappears
After magnetic, vice-side winding voltage falls under starting, and failing edge occurs, also passes through transformer turns ratio conversion and divider resistance partial pressure
After be lowered by and detected along decision circuitry, and the failing edge judgement short circuit also needs detected amplitude, when voltage change width
When degree reaches setting value VT2, high-level control signal Vctr-2 is exported, time detection circuit receives high level Vctr-2 letter
Stop timing after number, this timing time is denoted as Tx, then a set time inside the timing time and time detection circuit
It is compared, set time Tc, if Tx > Tc, determines that output voltage is higher, time detection circuit output control signal
Vctrl is high level, is denoted as state 1, and primary-side-control IC will reduce primary side driving duty ratio and working frequency, make output voltage
It reduces, if Tx < Tc, determines that output voltage is relatively low, time detection circuit output control signal Vctrl is low level, note
For state 0, because output synchronous rectification at this time is turned off under the higher electric current in secondary side, Tx can be therefore more former than Tc long
Side can reliably detect that output voltage is higher.
When output voltage is relatively low, secondary side control IC detects that output voltage lower than setting value, controls synchronous rectification
MOS pipe is turned off when secondary winding current is lesser, also passes through transformer turns ratio conversion and auxiliary winding divider resistance point
Input sample delay circuit after pressure has finished on the sampling shielding time, so rising edge when this rate of rise is come
In place with failing edge decision circuitry, rising edge decision circuitry can detect that a rising edge generates, and the rising
Detected amplitude is also needed along decision circuitry, then exports a high-level control signal when voltage change amplitude reaches setting value VT1
Vctrl-1, time detection circuit starts timing after receiving control signal to level Vctrl-1, if amplitude VT1 cannot reach
It controls signal and keeps low level, without timing, then timing time Tx is 0.After secondary side demagnetization, vice-side winding voltage is opened
Fall under beginning, failing edge occur, is lowered by after also passing through transformer turns ratio conversion and divider resistance partial pressure along decision circuitry detection
It arrives, and the failing edge decision circuitry also needs detected amplitude, when voltage change amplitude reaches setting value VT2 (demagnetization knot
Amplitude when beam is bound to very greatly, so can centainly reach setting value VT2) high-level control signal Vctr-2 is then exported, when
Between detection circuit receive high level Vctr-2 signal after stop timing, this timing time is denoted as Tx, then the timing time and
A set time inside time detection circuit is compared, set time Tc, if Tx > Tc, determines output voltage
Higher, time detection circuit output control signal Vctrl is high level, is denoted as state 1, and primary-side-control IC will reduce primary side drive
Dynamic duty ratio and working frequency, reduce output voltage, if Tx < Tc, determines that output voltage is relatively low, time detection circuit
Output control signal Vctrl is low level, is denoted as state 0, and primary-side-control IC just will increase primary side driving duty ratio and work frequency
Rate increases output voltage, because secondary side synchronous rectification is turned off when vice-side winding is lesser at this time, Tx can be very
It is small, therefore primary side can reliably detect that output voltage is relatively low.Vice-side winding electric current when devices turn off is bigger,
Then Tx is bigger；Conversely, vice-side winding electric current when devices turn off is smaller, then Tx is smaller.
It is assumed that it is Rds (on) that internal resistance, which is connected, in devices at room temperature, to realize that devices exist
It is turned off when secondary winding current is less than or equal to I1 to guarantee timing time Tx1 < Tc, devices its drain terminal when off
Absolute value of voltage is I1*Rds (on)；To realize that devices are turned off when secondary winding current is more than or equal to I2 to protect
Timing time Tx2 > Tc is demonstrate,proved, its drain terminal absolute value of voltage is I2*Rds (on) to devices when off.Secondary side is synchronous
Rectifier control circuit passes through resistance RDDetection devices drain terminal voltage is to control devices shutdown, therefore pair
The shutdown threshold value that two absolute values are fixed as VD1 and VD2, and VD1=I1*Rds need to be arranged in synchronous rectification control chip in side
(on), VD2=I2*Rds (on).
It absolute value is set is fixed as the shutdown threshold value of VD1 and VD2 and do not increase as the temperature increases, and synchronous rectification MOS
The conducting internal resistance Rds (on) of pipe increases as the temperature increases.In the case where being far below room ambient conditions, the conducting of devices
Internal resistance is reduced to Rds (on) 1 by Rds (on), and synchronous rectifier, secondary winding current I11=VD1/ are turned off in VD1
[Rds (on) 1], I11 > I1, then timing time Tx11 > Tx1, Tx11 > Tc, primary-side-control IC can not determine that power-supply system is defeated
Low voltage out, primary side driving duty ratio and working frequency will not increase, and power-supply system output voltage will continue to reduce, and finally lead
It is under-voltage to send a telegraph source system output voltage；Synchronous rectifier is turned off in VD2, secondary winding current is I21=VD2/ [Rds (on)
1], I21 > I2, Tx21 > Tx2, Tx21 > Tc, primary-side-control IC determine that power-supply system output voltage is higher, and primary side drives duty
Than reducing with working frequency, power-supply system output voltage can be reduced.
Much higher than under room ambient conditions, the conducting internal resistance of devices is increased to Rds (on) 2 by Rds (on),
Synchronous rectifier is turned off when VD1, secondary winding current is I12=VD1/ [Rds (on) 2], I12 < I1, Tx12 < Tx1, Tx12
< Tc, primary-side-control IC determine that power-supply system output voltage is relatively low, and primary side driving duty ratio and working frequency can increase, power supply system
System output voltage can increase；Synchronous rectifier is turned off in VD2, secondary winding current is I22=VD2/ [Rds (on) 2], I22
< I2, Tx22 < Tx2, Tx22 < Tc, primary-side-control IC can not determine that power-supply system output voltage is higher, and primary side drives duty
Than that will not reduce with working frequency, power-supply system output voltage will continue to increase, and eventually lead to power-supply system output voltage over-voltage.
A solution is to increase VD1 and VD2 also as the temperature increases, can only match synchronization to a certain extent
The conducting internal resistance Rds (on) of rectification metal-oxide-semiconductor increases as the temperature increases.The power-supply system of different capacity grade need to use difference
The devices of internal resistance Rds (on) are connected, the shutdown threshold value VD1 and VD2 of synchronous rectification control chip setting is unable to satisfy
The demand of the power-supply system of different capacity grade.
Utility model content
Have in view of that, the technical problems to be solved in the utility model be propose a kind of synchronous commutating control circuit to it is existing specially
The concrete application of sharp technology is extended, and secondary side feedback control program is realized in an optimal manner and is come out, and realizes different capacity
Grade power-supply system can work normally within the scope of total temperature.
Just as described in the background art, the implementation emphasis of secondary side feedback control circuit is the generation of signal and connects
It receives, and signal generates certain needs and uses synchronous commutating control circuit, turns off devices at different times and comes
The mode for realizing pressurization is most economical and the best mode of effect.
It is assumed that synchronous commutating control circuit detects that the erasing time of a switch periods in power-supply system is T, power supply system
System is the stability for maintaining output voltage, and the two neighboring switch periods erasing time can be considered identical.If current switch period is same
When step rectifier control circuit detects power-supply system output voltage lower than setting value, synchronous commutating control circuit controls synchronous rectification
Metal-oxide-semiconductor turn-on time is TON1, and ensures 0 < T-TON1 < Tc, and devices turn off within the T-TON1 time, remaining
Erasing current flow through the body diode of devices, so that the drain-source both end voltage of devices be made to increase,
It realizes " pressurization "；If current switch period synchronous commutating control circuit detects that power-supply system output voltage is higher than setting value,
Secondary side synchronous commutating control circuit control devices turn-on time is TON2, and ensures T-TON2 > Tc, synchronous rectification
Metal-oxide-semiconductor turns off within the T-TON2 time, and remaining erasing current flows through the body diode of devices, to make to synchronize
The drain-source both end voltage for rectifying metal-oxide-semiconductor increases, and realizes " pressurization "；And TON1 is not varied with temperature with TON2 and is changed, without
Consider the factor that devices conducting internal resistance R is varied with temperature and is changed, it is ensured that secondary side feedback power-supply system is in total temperature
It is worked normally in range.The utility model is based on such control program, proposes that a kind of synchronous commutating control circuit is as follows:
A kind of synchronous commutating control circuit, the converter applied to primary-side-control secondary side feedback, it is characterised in that: including electricity
Source module, erasing time detection circuit, output voltage detecting circuit, synchronous rectification logic circuit, driving circuit, VD pin, GT
Pin, FB pin and VSS pin；
The VD pin is used to connect the drain terminal of devices, and the GT pin is for connecting synchronous rectification
The grid end of metal-oxide-semiconductor, the VSS pin are used to connect the source of devices, and the FB pin is for connecting transformation
The voltage output end of device；The power module is whole to synchronize by the FB pin generation power supply VCC of synchronous commutating control circuit
Other module for power supply in flow control circuit；
The erasing time detection circuit is used to generate converter erasing time signal in each switch periods and export
Into synchronous rectification logic circuit；
The output voltage detecting circuit is used for the output voltage in each switch periods oversampled converter, by the output
Voltage is compared with setting value, and comparison result is exported into synchronous rectification logic circuit；
The synchronous rectification logic circuit receives the erasing time signal and output electricity of erasing time detection circuit output
The comparison result for pressing detection circuit to export extremely drives to generate the conducting of control devices and cut-off signals and export
In circuit；
The control devices conducting that the driving circuit receives the output of synchronous rectification logic circuit is believed with shutdown
Number, the conducting of driving devices and shutdown.
Preferably, synchronous rectification logic circuit receives the erasing time signal and output electricity of erasing time detection circuit output
The comparison result of detection circuit output is pressed to come from same period.
Preferably, a set time Tc is set in converter primary-side-control chip, if the output of current switch period converter
When voltage is lower than setting value, the driving that synchronous rectification logic circuit output control devices turn-on time is TON1 is believed
Number to driving circuit, it is TON1 that driving circuit, which drives devices turn-on time, and ensures 0 < T-TON1 < Tc, synchronous
Rectification metal-oxide-semiconductor turns off within the T-TON1 time, and remaining erasing current flows through the body diode of devices；If current
When the output voltage of switch periods converter is higher than setting value, synchronous rectification logic circuit output control synchronous rectification MOS pipe is led
For the driving signal that the logical time is TON2 to driving circuit, it is TON2 that driving circuit, which drives devices turn-on time, and
Ensure that T-TON2 > Tc, devices are turned off within the T-TON2 time, remaining erasing current flows through synchronous rectifier
Body diode.
As a kind of specific embodiment of erasing time detection circuit, including comparator CMP1, comparator CMP1's
Non-inverting input terminal connects VD pin, and the inverting input terminal of comparator CMP1 connects VSS pin, the output end output of comparator CMP1
Erasing time signal.
As a kind of specific embodiment of output voltage detecting circuit, including comparator CMP3, comparator CMP3's
Non-inverting input terminal connects FB pin, and the inverting input terminal of comparator CMP3 inputs setting value, the output end output of comparator CMP3
The comparison result.
As a kind of specific embodiment of synchronous rectification logic circuit, including current source I1, switch S1, switch S2,
It is operational amplifier AMP, capacitor CI, switch S3, capacitor C2, switch S4, current source I2, comparator CMP2, phase inverter I NV1, anti-
Phase device INV2, pulse-generating circuit PULSE, pulse-generating circuit PULSE1, pulse-generating circuit PULSE2, selector MUX and
With door AND1；Power supply VCC is successively connected to pin VSS after switch S1, switch S2；The tie point of switch S 1 and switch S2 connects
Connect the non-inverting input terminal of operational amplifier AMP and the non-inverting input terminal of comparator CMP2, the inverting input terminal of operational amplifier AMP
Its output end is connected, the output end of operational amplifier AMP is also divided into three tunnels after switch S3, and the first via is connected to after capacitor C2
Pin VSS, the second tunnel are successively connected to pin VSS after switch S4 and current source I2, and third road connects the anti-of comparator CMP2
Phase output terminal, the input terminal of the output end connection phase inverter INV2 of comparator CMP2, the output end connection of phase inverter INV2 and door
The first input end of AND1, driving circuit is connect with the output end of door AND1, and the input terminal of phase inverter INV1 inputs the erasing time
Signal, the input terminal of the output end connection pulse-generating circuit PULSE1 of phase inverter INV1, pulse-generating circuit PULSE1's is defeated
Outlet connects the input list of pulse-generating circuit PULSE2, and the output end of pulse-generating circuit PULSE2 connects pulse-generating circuit
Two output ends of the input terminal of PULSE, pulse-generating circuit PULSE are separately connected two input terminals of selector MUX, choosing
Select the comparison result of the control terminal input voltage detection circuit output of device MUX, the control of the output end connection switch S4 of selector MUX
End processed, the output end of pulse-generating circuit PULSE1 are also connected with the control terminal of switch S3, the output of pulse-generating circuit PULSE2
End is also connected with the control terminal of switch S2, and the control signal of switch S1 is erasing time signal.
Further, when input signal arrives without failing edge, two output ends continue defeated pulse-generating circuit PULSE
Low level out, once input signal failing edge arrives, two output ends export after the high level continued for some time again immediately
Export low level；And the difference of the two pulse signals of two output ends output is high level lasting time difference.
Further, pulse-generating circuit PULSE1 and pulse-generating circuit PULSE2 arrives in input signal without failing edge
When, persistently export low level；Once input signal failing edge arrives, pulse-generating circuit PULSE1 first persistently exports one immediately
The high level of section time, then exports low level again；Pulse-generating circuit PULSE2 pulse-generating circuit PULSE1 again
Start the high level for continuing to export a period of time when exporting low level, then exports low level again.
Further, when the input of the control terminal of selector MUX is high level, output end and one input terminal
Signal is consistent；When the input of the control terminal of selector MUX is low level, the signal one of output end and its another input terminal
It causes.
Further, as comparator CMP2, when non-inverting input terminal voltage is more than or equal to inverting input terminal voltage, output is high electric
It is flat, when comparator CMP2 exports low level when non-inverting input terminal voltage is less than inverting input terminal voltage.
The control strategy of the utility model is described in detail in specific embodiment, and the utility model is retaining background skill
Art document pair side synchronous rectification longevity of service high effeciency does not need additional series connection and parallel diode reduction and accounts for plate suqare simultaneously
On the basis of reducing cost, the utility model is also had the following beneficial effects:
1, TON1 and TON2 are not varied with temperature and are changed, without consideration devices conducting internal resistance R with temperature
The factor of variation and variation, it is ensured that secondary side feedback power-supply system works normally within the scope of total temperature.
2, meet the demand of the power-supply system of different capacity grade.
Detailed description of the invention
Fig. 1 is the circuit diagram for the secondary side feedback control method that CN105610306A is proposed；
Fig. 2 is the schematic diagram for the primary side detection circuit that CN107612334A is proposed；
Fig. 3 is the schematic diagram for the primary side detection circuit that 201811065698.X is proposed；
Fig. 4 be the utility model proposes synchronous commutating control circuit schematic diagram；
Fig. 5 be the utility model proposes synchronous commutating control circuit in erasing time detection circuit schematic diagram；
Fig. 6 be the utility model proposes synchronous commutating control circuit in synchronous rectification logic control schematic diagram；
Fig. 7 be the utility model proposes synchronous commutating control circuit in output voltage detecting circuit schematic diagram；
Fig. 8 be the utility model proposes synchronous commutating control circuit timing diagram.
Specific embodiment
It is with reference to the accompanying drawings and embodiments, further to the utility model in order to which the utility model is more clearly understood
It is described in detail.It should be appreciated that specific embodiment described herein is only used to explain the utility model, it is not used to limit this
Utility model.
As shown in figure 4, for the utility model proposes synchronous commutating control circuit schematic diagram, be applied to primary-side-control pair
The converter of side feedback, one end that converter primary side winding coil turn is NP are connected to input power VIN, and other end connection accounts for
Sky is than adjusting circuit, function one described in Chinese invention patent of the duty ratio adjusting circuit with Publication No. CN105610306A
It causes, the other end of duty ratio adjusting circuit is connected to input ground GND.Vice-side winding coil turn is that one end of NS is connected to output
Voltage VOUT, one end of output capacitance COUT, synchronous commutating control circuit FB pin, vice-side winding coil turn is NS
The other end is connected to the drain terminal of devices, devices parasitic body diode cathode, synchronous rectification control electricity
The VD pin on road.The source of devices, devices body diode anode, substrate are connected to output capacitance
The other end of COUT, the VSS pin of synchronous commutating control circuit and output ground VSS.The grid end of devices is connected to
Walk the GT pin of rectifier control circuit.
The VD that one end of erasing time detection circuit is connected to synchronous commutating control circuit in synchronous commutating control circuit draws
Foot, the other end MS of erasing time detection circuit are connected to one end of synchronous rectification logic circuit.In synchronous commutating control circuit
One end of output voltage detecting circuit is connected to the FB pin of synchronous commutating control circuit, the other end of output voltage detecting circuit
CH is connected to the synchronous rectification logic circuit other end.The third end TON of synchronous rectification logic circuit is connected to the one of driving circuit
End, the other end of driving circuit are connected to the GT pin of synchronous commutating control circuit.One end of power module be connected to synchronize it is whole
The FB pin of flow control circuit, other end output voltage VCC are each modular circuit power supply in synchronous commutating control circuit.
It is illustrated in figure 5 the schematic diagram of the erasing time detection circuit of the utility model, is a comparator CMP1, comparator
The non-inverting input terminal of C MP1 is connected to the VD pin of synchronous commutating control circuit, and the inverting input terminal of comparator CMP1 is connected to
Output ground VSS, the output end signal MS of comparator CMP1 are connected to one end of synchronous rectification logic circuit.
It is illustrated in figure 6 the utility model, the schematic diagram of synchronous rectification logic control in synchronous commutating control circuit, packet
Include current source I1, switch S1, switch S2, operational amplifier AMP, capacitor CI, switch S3, capacitor C2, switch S4, current source I2,
Comparator CMP2, phase inverter INV1, phase inverter INV2, pulse-generating circuit PULSE, pulse-generating circuit P ULSE1, pulse produce
Raw circuit PULSE2, selector MUX and with door AND1；Power supply VCC is successively connected to pin VSS after switch S1, switch S2；It opens
It closes S1 and connects the non-inverting input terminal of operational amplifier AMP and the non-inverting input terminal of comparator CMP2 with the tie point of switch S2, transport
The inverting input terminal for calculating amplifier AMP connects its output end, and the output end of operational amplifier A MP is also divided into three after switch S3
Road, the first via are connected to pin VSS after capacitor C2, and the second tunnel is successively connected to pin VSS after switch S4 and current source I2,
Third road connects the reversed-phase output of comparator CMP2, and the output end of comparator C MP2 connects the input terminal of phase inverter INV2, instead
The first input end of the output end connection and door AND1 of phase device INV2, connect driving circuit, phase inverter with the output end of door AND1
The input terminal of INV1 inputs erasing time signal, the input of the output end connection pulse-generating circuit PULSE1 of phase inverter INV1
End, the input list of the output end connection pulse-generating circuit PULSE2 of pulse-generating circuit PULSE1, pulse-generating circuit
The input terminal of the output end connection pulse-generating circuit PUL SE of PULSE2, two output ends point of pulse-generating circuit PULSE
Not Lian Jie selector MUX two input terminals, selector MUX control terminal input voltage detection circuit output comparison result,
The control terminal of the output end connection switch S4 of selector MUX, the output end of pulse-generating circuit PULSE1 are also connected with switch S3's
Control terminal, the output end of pulse-generating circuit PULSE2 are also connected with the control terminal of switch S2, and the control signal of switch S1 is demagnetization
Time signal.
For the convenience of description, the size of current of current source I1 is denoted as I1 in embodiment, the size of current of current source I2 is remembered
For I2, the capacitance of capacitor C1 is denoted as C1, the capacitance of capacitor C2 is denoted as C2, erasing time signal is denoted as MS, phase inverter INV1 output
End output signal be denoted as TC, two output ends of pulse-generating circuit PULSE (connection selector MUX two input terminal A and
B) signal exported is denoted as P1 and P2, the signal of pulse-generating circuit PULSE1 output end output is denoted as SA, pulse-generating circuit
The signal that the signal of PULSE2 output end output is denoted as DISC, selector MUX output Y output is denoted as SP, exports with door AND1
The comparison result that the signal of end output is denoted as TON, voltage detecting circuit exports is denoted as CH, and (the control terminal S of connection selector MUX is defeated
Enter the CH signal).
It is illustrated in figure 7 the schematic diagram of the output voltage detecting circuit of the utility model, is a comparator CMP3, comparator
The non-inverting input terminal of C MP3 is connected to the FB pin of synchronous commutating control circuit, and the inverting input terminal input of comparator CMP3 is set
The output end output signal CH of definite value VREF, comparator CMP3 are connected to the control of selector MUX in synchronous rectification logic circuit
Hold S.
Driving circuit receives synchronous rectification logic circuit output signal TON, and output signal passes through synchronous commutating control circuit
GT pin drive devices.TON is high level, and driving circuit drives devices conducting, and TON is low
Level, driving circuit drive devices shutdown.
The utility model driving circuit is using the IR4426 chip of IR (Chinese name: international rectifier) company in conjunction with its recommendation
Peripheral circuit can be realized.
It should be noted that above-mentioned technical proposal synchronous rectification logic circuit receives disappearing for erasing time detection circuit output
Magnetic time signal and the comparison result of output voltage detecting circuit output can come from same period, and the result detected at this time is the most
Accurately；Also different cycles be may be from, at this time in order to guarantee the beneficial effects of the utility model, being separated by periodicity be should not be too large.
Fig. 8 be the utility model proposes synchronous commutating control circuit timing diagram, in conjunction with the figure to the utility model
The control-Strategy analysis of synchronous commutating control circuit is described as follows:
Pulse-generating circuit PULSE output two pulse signals P1 and P2 after the arrival of input signal DISC failing edge are extremely selected
The port A and B of device MUX is selected, the difference of two pulse signals is high level lasting time difference, and pulse signal P1 high level is held
The continuous time is denoted as △ t3, and pulse signal P2 high level lasting time is denoted as △ t4.
Pulse-generating circuit PULSE1 exports pulse signal SA all the way after the arrival of input signal failing edge and SA signal is high
Level duration is denoted as △ ta.
Pulse-generating circuit PULSE2 exports pulse signal DISC and DISC all the way after the arrival of input signal SA failing edge
Signal high level lasting time is denoted as △ tb.
Failing edge refers to that input signal falls to rapidly low level by high level.
The control terminal S of selector MUX is connected to the CH signal that comparator CMP3 is exported in output voltage detecting circuit, signal
Input terminal A is connected to the pulse signal P1 of pulse-generating circuit PULSE output, and signal input part B is connected to pulse-generating circuit
The pulse signal P2, output end Y output signal SP of PULSE output.When CH is high level, signal exports SP and signal inputs
Hold the input pulse signal P2 of B consistent；When CH is low level, signal exports the input pulse signal of SP and signal input part A
P1 signal is consistent.
It is assumed that erasing time detection circuit detects a switch week in power-supply system in the synchronous commutating control circuit of secondary side
The erasing time of phase is T, and power-supply system is to maintain the stability of output voltage, and the two neighboring switch periods erasing time can be considered
It is identical and be T.
Within 0~t1 period, power-supply system is in the excitation stage, and synchronous commutating control circuit VD pin voltage is VIN/
(NP/NS) and it is higher than output ground VSS, comparator CMP1 output signal MS is high level, and switch S1 is turned off, and phase inverter INV1 is defeated
Signal TC is low level out, is low level, the output signal SA of pulse-generating circuit PULSE1 with door AND1 output signal TON
For low level, switch S3 shutdown, the output signal DISC of pulse-generating circuit PULSE2 is low level, switch S2 shutdown, pulse
Output signal P1, P2 of generation circuit PULSE is low level.FB is lower than output voltage detecting circuit setting value VREF at this time,
Comparator CMP3 output signal CH is low level, the output signal of selector MUX output signal SP and pulse-generating circuit PULSE
P1 is unanimously low level, switch S4 shutdown.Capacitance is one end voltage VC1 that the capacitor of C1 is connect with comparator CMP2 in-phase end
For output ground VSS, one end voltage VC2 that the capacitor that capacitance is C2 is connect with comparator CMP2 reverse side is output ground VSS, is compared
Device CMP2 exports high level, and phase inverter INV2 output signal is low level, is low level, driving with door AND1 output signal TON
Output to synchronous commutating control circuit GT pin is low level, devices shutdown.
Within t1~t2 period, power-supply system is in degaussing phase, t1 moment, devices shutdown, by synchronizing
It rectifies metal-oxide-semiconductor parasitic diode and afterflow is connected.Synchronous commutating control circuit VD pin voltage is lower than output ground VSS, comparator
CMP1 output signal MS falls to low level by high level, and switch S1 conducting, TC is by low level for phase inverter INV1 output signal
It is upgraded to high level, the output signal SA of pulse-generating circuit PULSE1 is low level, switch S3 shutdown, pulse-generating circuit
The output signal DISC of PULSE2 is low level, and switch S2 is turned off, and output signal P1, P2 of pulse-generating circuit PULSE is
Low level.FB is lower than output voltage detecting circuit setting value VREF at this time, and comparator CMP3 output signal CH is low level, selection
Device MUX output signal SP consistent with the output signal P1 of pulse-generating circuit PULSE is low level, switch S4 shutdown.Switch S1
Conducting, switch S2 turn off, the current source that size of current is I1 by switch S1 to capacitance be C1 capacitor and comparator CMP2 it is same
One end charging of phase end connection, capacitance are on one end voltage VC1 that the capacitor of C1 is connect with comparator CMP2 in-phase end starts
It rises, one end voltage VC2 that the capacitor that capacitance is C2 is connect with comparator CMP2 reverse side is output ground VSS, and comparator CMP2 is defeated
High level out, phase inverter INV2 output signal are low level, are low level with door AND1 output signal TON, and driving is exported to same
Step rectifier control circuit GT pin is low level, devices shutdown.
At the t2 moment, power-supply system is in the excitation stage, and synchronous commutating control circuit VD pin voltage is by being lower than output ground
VSS rises to VIN/ (NP/NS) and is higher than output ground VSS, and comparator CMP1 output signal MS rises to high electricity by low level
Flat, switch S1 shutdown, capacitance is after one end voltage VC1 that the capacitor of C1 is connect with comparator CMP2 in-phase end rises to VSA
No longer rise, t1 start time to t2 start time this
The section time is denoted as erasing time T1, and has
I1*T1=C1*VSA
Phase inverter INV1 output signal TC falls to low level by high level, generates failing edge, pulse-generating circuit
The output signal SA of PULSE1 rises to high level by low level and high level lasting time is △ ta, switch S3 conducting, capacitance
The capacitor that the one end being connect with comparator CMP2 reverse side for the capacitor of C2 is C1 by capacitance is connect with comparator CMP2 in-phase end
One end charged by amplifier AMP, one end voltage VC2 for being connect with comparator CMP2 reverse side of capacitor that capacitance is C2
VSA is risen to by output ground VSS within the △ ta time, comparator CMP2 exports high level, and phase inverter INV2 output signal is low
Level is low level with door AND1 output signal TON, and driving output to synchronous commutating control circuit GT pin is low level, together
Step rectification metal-oxide-semiconductor is in an off state.
After SA permanent High level time △ ta, SA falls to low level by high level, and S3 shutdown generates failing edge, arteries and veins
The output signal DISC for rushing generation circuit PULSE2 rises to high level by low level and high level lasting time is △ tb, switch
S2 is open-minded, one end voltage VC1 for being connect with comparator CMP2 in-phase end of capacitor that capacitance is C1 in time △ tb by VSA under
It is down to input ground VSS, comparator CMP2 output and low level is fallen to by high level, phase inverter INV2 output is risen to by low level
High level, another input signal TC with door AND1 are low level, and the output signal TON with door AND1 is low level, driving
Output to synchronous commutating control circuit GT pin is low level, devices shutdown.
After signal DISC permanent High level time △ tb, DISC falls to low level by high level, generates failing edge, arteries and veins
Rush the pulse signal that generation circuit PULSE generates output signal P1, P2.P1 rises to high level by low level and high level continues
Time is △ t3, and P2 rises to high level by low level and high level lasting time is △ t4.FB is examined lower than output voltage at this time
Slowdown monitoring circuit setting value VREF, comparator CMP3 output signal CH are low level, and selector MUX output signal SP and pulse generate electricity
The output signal P1 of road PULSE is consistent, and switch S4 is connected and turn-on time is △ t3, and the current source that size of current is I2 is by opening
It closes one end voltage VC2 that S4 connect the capacitor that capacitance is C2 with comparator CMP2 inverting input terminal to discharge, discharge time
For switch S4 turn-on time △ t3, capacitance be one end voltage VC2 for being connect with comparator CMP2 inverting input terminal of the capacitor of C2 by
VSA drops to VSA1, and has
I2* Δ t3=C2* (VSA-VSA1)
One end voltage VC1 that the capacitor that capacitance is C1 is connect with comparator CMP2 in-phase end is output ground VSS, and capacitance is
One end voltage VC2 that the capacitor of C2 is connect with comparator CMP2 reverse side is VSA1, and comparator CMP2 exports low level, phase inverter
INV2 output signal is high level, and the input terminal TC signal with door AND1 is low level, and the output signal TON with door AND1 is low
Level, driving output to synchronous commutating control circuit GT pin are low level, devices shutdown.
Within t3~t4 period, power-supply system is in degaussing phase, t3 moment, devices shutdown, by synchronizing
It rectifies metal-oxide-semiconductor parasitic diode and afterflow is connected.Synchronous commutating control circuit VD pin voltage is lower than output ground VSS, comparator
CMP1 output signal MS falls to low level by high level, and switch S1 conducting, TC is by low level for phase inverter INV1 output signal
It is upgraded to high level, the output signal SA of pulse-generating circuit PULSE1 is low level, switch S3 shutdown, pulse-generating circuit
The output signal DISC of PULSE2 is low level, and switch S2 is turned off, and output signal P1, P2 of pulse-generating circuit PULSE is
Low level.FB is lower than output voltage detecting circuit setting value VREF at this time, and comparator CMP3 output signal CH is low level, selection
Device MUX output signal SP consistent with the output signal P1 of pulse-generating circuit PULSE is low level, switch S4 shutdown.Switch S1
Conducting, switch S2 turn off, the current source that size of current is I1 by switch S1 to capacitance be C1 capacitor and comparator CMP2 it is same
One end charging of phase end connection, capacitance are on one end voltage VC1 that the capacitor of C1 is connect with comparator CMP2 in-phase end starts
Rise, one end voltage VC2 that the capacitor that capacitance is C2 connect with comparator CMP2 reverse side is VSA1, capacitance for C1 capacitor and
When VSA1 has not yet been reached in one end voltage VC1 of comparator CMP2 in-phase end connection, comparator CMP2 exports low level, phase inverter
INV2 output signal is high level, is high level, driving output to synchronous commutating control circuit GT with door AND1 output signal TON
Pin is high level, devices conducting.In one end electricity that the capacitor that capacitance is C1 is connect with comparator CMP2 in-phase end
When pressure VC1 reaches VSA1, comparator CMP2 output rises to high level by low level, and phase inverter INV2 output signal is by high electricity
It is flat to fall to low level, low level, driving output to synchronous rectification control are fallen to by high level with door AND1 output signal TON
Circuit GT pin processed falls to low level, devices shutdown, devices service time TON1 by high level
And meet formula
I1*TON1=C1*VSA1.
By devices parasitic diode afterflow after devices shutdown, capacitance is the capacitor of C1 compared with
One end voltage VC1 of device CMP2 in-phase end connection continues to be charged by the current source that size of current is I1.
At the t4 moment, power-supply system is in the excitation stage, and synchronous commutating control circuit VD pin voltage is by being lower than output ground
VSS rises to VIN/ (NP/NS) and is higher than output ground VSS, and comparator CMP1 output signal MS rises to high electricity by low level
Flat, switch S1 shutdown, capacitance is that one end voltage VC1 that the capacitor of C1 is connect with comparator CMP2 in-phase end rises to after VSA not
Rise again, t3 start time to t4 period start time is denoted as erasing time T2, devices parasitic diode afterflow
Time is
△ t1=T2-TON1, and have
I1*T2=C1*VSA
Phase inverter INV1 output signal TC falls to low level by high level, generates failing edge, pulse-generating circuit
The output signal SA of PULSE1 rises to high level by low level and high level lasting time is △ ta, switch S3 conducting, capacitance
The capacitor that the one end being connect with comparator CMP2 reverse side for the capacitor of C2 is C1 by capacitance is charged by amplifier AMP, is held
Value is that one end voltage VC2 that the capacitor of C2 is connect with comparator CMP2 reverse side is risen within the △ ta time by output ground VSA1
VSA, comparator CMP2 export high level, and phase inverter INV2 output signal is low level, are low with door AND1 output signal TON
Level, driving output to synchronous commutating control circuit GT pin is low level, and devices continue to turn off.
After SA permanent High level time △ ta, SA falls to low level by high level, and S3 shutdown generates failing edge, arteries and veins
The output signal DISC for rushing generation circuit PULSE2 rises to high level by low level and high level lasting time is △ tb, switch
S2 is open-minded, one end voltage VC1 for being connect with comparator CMP2 in-phase end of capacitor that capacitance is C1 in time △ tb by VSA under
It is down to input ground VSS, comparator CMP2 output and low level is fallen to by high level, phase inverter INV2 output has low level to rise to
High level, another input signal TC with door AND1 are low level, and the output signal TON with door AND1 is low level, driving
Output to synchronous commutating control circuit GT pin is low level, and devices continue to turn off.
After signal DISC permanent High level time △ tb, DISC falls to low level by high level, generates failing edge, arteries and veins
Rush the pulse signal that generation circuit PULSE generates output signal P1, P2.P1 rises to high level by low level and high level continues
Time is △ t3, and P2 rises to high level by low level and high level lasting time is △ t4.FB is examined higher than output voltage at this time
Slowdown monitoring circuit setting value VREF, comparator CMP3 output signal CH are high level, and selector MUX output signal SP's and PULSE is defeated
Signal P2 is consistent out, and switch S4 is opened and turn-on time is △ t4, and the current source that size of current is I2 is by switch S4 to capacitance
One end voltage VC2 connecting for the capacitor of C2 with comparator CMP2 inverting input terminal discharges, and discharge time is that switch S4 is led
Logical time △ t4, capacitance are that one end voltage VC2 that the capacitor of C2 is connect with comparator CMP2 inverting input terminal is dropped to by VSA
VSA2, and have
I2* Δ t4=C2* (VSA-VSA2)
One end voltage VC1 that the capacitor that capacitance is C1 is connect with comparator CMP2 in-phase end is output ground VSS, and capacitance is
One end voltage VC2 that the capacitor of C2 is connect with comparator CMP2 reverse side is VSA2, and comparator CMP2 exports low level, phase inverter
INV2 output signal is high level, and the input terminal TC signal with door AND1 is low level, and the output signal TON with door AND1 is low
Level, driving output to synchronous commutating control circuit GT pin are low level, devices shutdown.
Within t5~t6 period, power-supply system is in degaussing phase.
At the t5 moment, afterflow is connected by devices parasitic diode in devices shutdown.Synchronous rectification
Control circuit VD pin voltage is lower than output ground VSS, and comparator CMP1 output signal MS falls to low level by high level, switchs
S1 conducting, phase inverter INV1 output signal TC rise to high level, the output signal of pulse-generating circuit PULSE1 by low level
SA is low level, and switch S3 shutdown, the output signal DISC of pulse-generating circuit PULSE2 is low level, switch S2 shutdown, arteries and veins
Output signal P1, P2 for rushing generation circuit PULSE is low level.FB is higher than output voltage detecting circuit setting value at this time
VREF, comparator CMP3 output signal CH are high level, and selector MUX output signal SP is consistent with the output signal P2 of PULSE
For low level, switch S4 shutdown.Switch S1 conducting, switch S2 shutdown, size of current, which is given for the current source of I1 by switch S1, to be held
Value is one end charging that the capacitor of C1 is connect with comparator CMP2 in-phase end, the capacitor and comparator CMP2 in-phase end that capacitance is C1
One end voltage VC1 of connection is begun to ramp up, and one end voltage VC2 that the capacitor that capacitance is C2 is connect with comparator CMP2 reverse side is
VSA2, when VSA2 has not yet been reached in one end voltage VC1 that the capacitor that capacitance is C1 is connect with comparator CMP2 in-phase end, comparator
CMP2 exports low level, and phase inverter INV2 output signal is high level, is high level with door AND1 output signal TON, drives defeated
It is out high level, devices conducting to synchronous commutating control circuit GT pin.In the capacitor and comparator that capacitance is C1
When one end voltage VC1 of CMP2 in-phase end connection reaches VSA2, comparator CMP2 output rises to high level, reverse phase by low level
Device INV2 output signal falls to low level by high level, falls to low level by high level with door AND1 output signal TON, drives
Dynamic output falls to low level, devices shutdown, synchronous rectification by high level to synchronous commutating control circuit GT pin
Metal-oxide-semiconductor service time TON2 and meet formula
I1*TON2=C1*VSA2.
By devices parasitic diode afterflow after devices shutdown, capacitance is the capacitor of C1 compared with
One end voltage VC1 of device CMP2 in-phase end connection continues to be charged by the current source that size of current is I1.
At the t6 moment, power-supply system is in the excitation stage, and synchronous commutating control circuit VD pin voltage is by being lower than output ground
VSS rises to VIN/ (NP/NS) and is higher than output ground VSS, and comparator CMP1 output signal MS rises to high electricity by low level
Flat, switch S1 shutdown, capacitance is that one end voltage VC1 that the capacitor of C1 is connect with comparator CMP2 in-phase end rises to after VSA not
Rise again, t5 start time to t6 period start time is denoted as erasing time T3, devices parasitic diode afterflow
Time △ t2=T3-TON2, and have
I1*T3=C1*VSA
Phase inverter INV1 output signal TC falls to low level by high level, generates failing edge, pulse-generating circuit
The output signal SA of PULSE1 rises to high level by low level and high level lasting time is △ ta, switch S3 conducting, capacitance
The capacitor that the one end being connect with comparator CMP2 reverse side for the capacitor of C2 is C1 by capacitance is charged by amplifier AMP, is held
Value is that one end voltage VC2 that the capacitor of C2 is connect with comparator CMP2 reverse side is risen within the △ ta time by output ground VSA1
VSA, comparator CMP2 export high level, and phase inverter INV2 output signal is low level, are low with door AND1 output signal TON
Level, driving output to synchronous commutating control circuit GT pin is low level, and devices continue to turn off.
After SA permanent High level time △ ta, SA falls to low level by high level, and S3 shutdown generates failing edge, arteries and veins
The output signal DISC for rushing generation circuit PULSE2 rises to high level by low level and high level lasting time is △ tb, switch
S2 is open-minded, one end voltage VC1 for being connect with comparator CMP2 in-phase end of capacitor that capacitance is C1 in time △ tb by VSA under
It is down to input ground VSS, comparator CMP2 output and low level is fallen to by high level, phase inverter INV2 output has low level to rise to
High level, another input signal TC with door AND1 are low level, and the output signal TON with door AND1 is low level, driving
Output to synchronous commutating control circuit GT pin is low level, and devices continue to turn off.
After signal DISC permanent High level time △ tb, DISC falls to low level by high level, generates failing edge, arteries and veins
Rush the pulse signal of generation circuit PULSE output signal P1, P2.P1 rises to high level and high level lasting time by low level
For △ t3, P2 rises to high level by low level and high level lasting time is △ t4.FB is higher than output voltage detection electricity at this time
Road setting value VREF, comparator CMP3 output signal CH are high level, and the output of selector MUX output signal SP and PULSE are believed
Number P2 is consistent, and switch S4 is opened and turn-on time is △ t4, and the current source that size of current is I2 is C2 to capacitance by switch S4
One end voltage VC2 for being connect with comparator CMP2 inverting input terminal of capacitor discharge, when discharge time is switch S4 conducting
Between △ t4, one end voltage VC2 for connecting with comparator CMP2 inverting input terminal of capacitor that capacitance is C2 drops to VSA2 by VSA,
And have
I2* Δ t4=C2* (VSA-VSA2)
One end voltage VC1 that the capacitor that capacitance is C1 is connect with comparator CMP2 in-phase end is output ground VSS, and capacitance is
One end voltage VC2 that the capacitor of C2 is connect with comparator CMP2 reverse side is VSA2, and comparator CMP2 exports low level, phase inverter
INV2 output signal is high level, and the input terminal TC signal with door AND1 is low level, and the output signal TON with door AND1 is low
Level, driving output to synchronous commutating control circuit GT pin are low level, devices shutdown.
It is assumed that T1=T2=T3, C1=C2, I1=I2
The capacitor for being C1 to capacitance:
I1*T1=C1*VSA
I1*TON1=C1*VSA1
I1*TON2=C1*VSA2
The capacitor for being C2 to capacitance:
I2* Δ t3=C2* (VSA-VSA1)
I2* Δ t4=C2* (VSA-VSA2)
It can be obtained by above-mentioned formula:
I1* Δ t3=C2* (VSA-VSA1)
I1* Δ t3=C2*VSA-C2*VSA1=C1*VSA-C2*VSA1
I1* Δ t3=I1*T1-C2*VSA1
I1* (T1- Δ t3)=C2*VSA1=C1*VSA1=I1*TON1
TON1=T1- Δ t3
Δ t3=T-TON1=Δ t1
Δ t4=T-TON2=Δ t2
Similarly △ t2=△ t4, by adjusting the pulse signal high level of pulse-generating circuit PULSE output signal P1, P2
Duration is △ t3, △ t4, and then adjusts the turn-off time of devices
△ t1=T-TON1, △ t2=T-TON2.
If the output voltage detecting circuit in current switch period synchronous commutating control circuit detects that power-supply system exports
Synchronous rectification logic circuit output control synchronous rectification MOS when voltage is lower than setting value VREF, in synchronous commutating control circuit
For the driving signal that pipe turn-on time is TON1 to driving circuit, it is TON1 that driving circuit, which drives devices turn-on time,
And ensuring 0 < △ t1=△ t3=T-TON1 < Tc, devices turn off within the T-TON1 time, remaining demagnetization electricity
Stream flows through the body diode of devices, because of the conducting internal resistance Rds of the pressure drop ratio devices of diode
(on) pressure drop caused by is big, so vice-side winding voltage can be made to increase, a rate of rise occurs；If current switch period pair
It is synchronous when output voltage detecting circuit in the synchronous commutating control circuit of side detects that power-supply system output voltage is higher than setting value
The driving signal that synchronous rectification logic circuit output control devices turn-on time in rectifier control circuit is TON2
To driving circuit, it is TON2 that driving circuit, which drives devices turn-on time, and ensures △ t2=△ t4=T-TON2 >
Tc, devices turn off within the T-TON2 time, and remaining erasing current flows through the body diode of synchronous rectifier, because
Pressure drop caused by conducting internal resistance R for the pressure drop ratio devices of diode is big, so can make vice-side winding voltage liter
There is a rate of rise in height.TON1 is not varied with temperature with TON2 and is changed, without consideration devices conducting
Internal resistance Rds (on) is varied with temperature and the factor that changes, it is ensured that secondary side feedback power-supply system works normally within the scope of total temperature.
The set time Tc set in said chip can also be realized by pulse-generating circuit PULSE1 or PULSE2.
Above are merely preferred embodiments of the utility model, it is noted that above-mentioned preferred embodiment should not regard
For limitations of the present invention, the protection scope of the utility model should be defined by the scope defined by the claims..For
For those skilled in the art, without departing from the spirit and scope of the utility model, it can also make several
Improvements and modifications, these improvements and modifications also should be regarded as the protection scope of the utility model.
Claims (10)
1. a kind of synchronous commutating control circuit, the converter applied to primary-side-control secondary side feedback, it is characterised in that: including power supply
Module, erasing time detection circuit, output voltage detecting circuit, synchronous rectification logic circuit, driving circuit, VD pin, GT draw
Foot, FB pin and VSS pin；
The VD pin is used to connect the drain terminal of devices, and the GT pin is for connecting devices
Grid end, the VSS pin is used to connect the sources of devices, and the FB pin is for connecting converter
Voltage output end；It is synchronous rectification control that the power module, which generates power supply VCC by the FB pin of synchronous commutating control circuit,
Other module for power supply in circuit processed；
The erasing time detection circuit is used to generate converter erasing time signal in each switch periods and export to same
In step rectification logic circuit；
The output voltage detecting circuit is used for the output voltage in each switch periods oversampled converter, by the output voltage
It is compared with setting value, and comparison result is exported into synchronous rectification logic circuit；
The synchronous rectification logic circuit receives erasing time signal and the output voltage inspection of erasing time detection circuit output
The comparison result of slowdown monitoring circuit output, to generate the conducting of control devices and cut-off signals and export to driving circuit
In；
The driving circuit receives the conducting of control devices and the cut-off signals of synchronous rectification logic circuit output,
Drive devices conducting and shutdown.
2. synchronous commutating control circuit according to claim 1, it is characterised in that: synchronous rectification logic circuit receives demagnetization
The erasing time signal of time detection circuit output and the comparison result of output voltage detecting circuit output come from same period.
3. synchronous commutating control circuit according to claim 1, it is characterised in that: set one in converter primary-side-control chip
Set time Tc, if the output voltage of current switch period converter is lower than setting value, the output control of synchronous rectification logic circuit
The driving signal that devices turn-on time processed is TON1 to driving circuit, driving circuit driving devices are led
The logical time is TON1, and ensures 0 < T-TON1 < Tc, and devices turn off within the T-TON1 time, remaining demagnetization electricity
Stream flows through the body diode of devices；It is synchronous if current switch period output voltage is higher than the setting value of converter
Rectifying logic circuit output control devices turn-on time is the driving signal of TON2 to driving circuit, driving circuit
Driving devices turn-on time is TON2, and ensures T-TON2 > Tc, and devices are within the T-TON2 time
Shutdown, remaining erasing current flow through the body diode of synchronous rectifier.
4. synchronous commutating control circuit according to claim 1, it is characterised in that: erasing time detection circuit includes comparing
The non-inverting input terminal of device CMP1, comparator CMP1 connect VD pin, and the inverting input terminal of comparator CMP1 connects VSS pin, than
Output end compared with device CMP1 exports erasing time signal.
5. synchronous commutating control circuit according to claim 1, it is characterised in that: output voltage detecting circuit includes comparing
The non-inverting input terminal of device CMP3, comparator CMP3 connect FB pin, and the inverting input terminal of comparator CMP3 inputs setting value, compares
The output end output of the device CMP3 comparison result.
6. synchronous commutating control circuit according to claim 1, it is characterised in that: synchronous rectification logic circuit includes electric current
Source I1, switch S1, switch S2, operational amplifier AMP, capacitor CI, switch S3, capacitor C2, switch S4, current source I2, comparator
CMP2, phase inverter INV1, phase inverter INV2, pulse-generating circuit PULSE, pulse-generating circuit PULSE1, pulse-generating circuit
PULSE2, selector MUX and with door AND1；Power supply VCC is successively connected to pin VSS after switch S1, switch S2；Switch S1 and
The non-inverting input terminal of the tie point connection operational amplifier AMP of switch S2 and the non-inverting input terminal of comparator CMP2, operation amplifier
The inverting input terminal of device AMP connects its output end, and the output end of operational amplifier AMP is also divided into three tunnels after switch S3, and first
Road is connected to pin VSS after capacitor C2, and the second tunnel is successively connected to pin VSS, third road after switch S4 and current source I2
Connect the reversed-phase output of comparator CMP2, the input terminal of the output end connection phase inverter INV2 of comparator CMP2, phase inverter
The first input end of the output end connection and door AND1 of INV2, driving circuit, phase inverter INV1 are connect with the output end of door AND1
Input terminal input erasing time signal, phase inverter INV1 output end connection pulse-generating circuit PULSE1 input terminal, arteries and veins
The input list of the output end connection pulse-generating circuit PULSE2 of generation circuit PULSE1 is rushed, pulse-generating circuit PULSE2's is defeated
Outlet connects the input terminal of pulse-generating circuit PULSE, and two output ends of pulse-generating circuit PULSE are separately connected selector
Two input terminals of MUX, the comparison result of the control terminal input voltage detection circuit output of selector MUX, selector MUX's is defeated
The control terminal of outlet connection switch S4, the output end of pulse-generating circuit PULSE1 are also connected with the control terminal of switch S3, and pulse produces
The output end of raw circuit PULSE2 is also connected with the control terminal of switch S2, and the control signal of switch S1 is erasing time signal.
7. synchronous commutating control circuit according to claim 6, it is characterised in that: pulse-generating circuit PULSE is being inputted
When signal arrives without failing edge, two output ends persistently export low level, once input signal failing edge arrives, two outputs
End exports low level after exporting the high level continued for some time immediately again；And the two pulse signals of two output ends output
Difference be high level lasting time difference.
8. synchronous commutating control circuit according to claim 6, it is characterised in that: pulse-generating circuit PULSE1 and pulse
Generation circuit PULSE2 persistently exports low level when input signal arrives without failing edge；Once input signal failing edge arrives
Come, pulse-generating circuit PULSE1 first persistently exports the high level of a period of time immediately, then exports low level again；Pulse produces
Raw circuit PULSE2 starts to continue the high level of output a period of time when pulse-generating circuit PULSE1 exports low level again,
Then low level is exported again.
9. synchronous commutating control circuit according to claim 6, it is characterised in that: when the control terminal of selector MUX inputs
When being high level, output end is consistent with the signal of one input terminal；When the control terminal input of selector MUX is low electricity
Usually, output end is consistent with the signal of its another input terminal.
10. synchronous commutating control circuit according to claim 6, it is characterised in that: when comparator CMP2 is in homophase input
End voltage exports high level when being more than or equal to inverting input terminal voltage, when comparator CMP2 is less than reverse phase in non-inverting input terminal voltage
Low level is exported when input terminal voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821860870.6U CN209134310U (en) | 2018-11-13 | 2018-11-13 | A kind of synchronous commutating control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821860870.6U CN209134310U (en) | 2018-11-13 | 2018-11-13 | A kind of synchronous commutating control circuit |
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| Publication Number | Publication Date |
|---|---|
| CN209134310U true CN209134310U (en) | 2019-07-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821860870.6U Withdrawn - After Issue CN209134310U (en) | 2018-11-13 | 2018-11-13 | A kind of synchronous commutating control circuit |
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|---|---|
| CN (1) | CN209134310U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109510481A (en) * | 2018-11-13 | 2019-03-22 | 广州金升阳科技有限公司 | A kind of synchronous commutating control circuit and control method |
| CN114003147A (en) * | 2021-11-02 | 2022-02-01 | 深圳市汇顶科技股份有限公司 | Signal detection device, touch pad and electronic equipment |
| WO2023005758A1 (en) * | 2021-07-30 | 2023-02-02 | 深圳英集芯科技股份有限公司 | Switched-mode power supply secondary-side synchronous rectifier controller, and switched-mode power supply |
-
2018
- 2018-11-13 CN CN201821860870.6U patent/CN209134310U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109510481A (en) * | 2018-11-13 | 2019-03-22 | 广州金升阳科技有限公司 | A kind of synchronous commutating control circuit and control method |
| CN109510481B (en) * | 2018-11-13 | 2024-02-13 | 广州金升阳科技有限公司 | Synchronous rectification control circuit and control method |
| WO2023005758A1 (en) * | 2021-07-30 | 2023-02-02 | 深圳英集芯科技股份有限公司 | Switched-mode power supply secondary-side synchronous rectifier controller, and switched-mode power supply |
| CN114003147A (en) * | 2021-11-02 | 2022-02-01 | 深圳市汇顶科技股份有限公司 | Signal detection device, touch pad and electronic equipment |
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