CN209001929U - A kind of fully differential CMOS switched-capacitor integrator - Google Patents
A kind of fully differential CMOS switched-capacitor integrator Download PDFInfo
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- CN209001929U CN209001929U CN201821768223.2U CN201821768223U CN209001929U CN 209001929 U CN209001929 U CN 209001929U CN 201821768223 U CN201821768223 U CN 201821768223U CN 209001929 U CN209001929 U CN 209001929U
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Abstract
The utility model discloses a kind of fully differential CMOS switched-capacitor integrators, it is to be switched by eight, two sampling capacitances, two integrating capacitors and an operational amplifier composition, wherein: being sequentially connected in series first switch between the input terminal of forward voltage and the output end of backward voltage, first sampling capacitance, 4th switch and operational amplifier, the 5th switch has been sequentially connected in series between the input terminal of backward voltage and the output end of forward voltage, second sampling capacitance, 8th switch and operational amplifier, and, between first switch and the first sampling capacitance, between first sampling capacitance and the 4th switch, between 5th switch and the second sampling capacitance, it is parallel with a switching branches respectively between second sampling capacitance and the 8th switch, between the 4th switch and the output end of backward voltage, it is in parallel between 8th switch and the output end of forward voltage There is an integrating capacitor.The utility model has many advantages, such as that circuit structure is simple, area occupied is small, precision is high, low in energy consumption.
Description
Technical field
The utility model is to be related to a kind of fully differential CMOS switched-capacitor integrator, belongs to microelectronics technology.
Background technique
In recent years, signal and information processing widely penetrated into scientific research, technological development, industrial production, national defence and
The every field of national economy, the research hotspot for being designed to IC designer of signal processing chip.In order to meet electricity
Pond drives the energy conservation of the demand and large scale system of portable equipment to need, and signal processing chip needs high performance same in guarantee
When, constantly advance towards more low-voltage, more low-power consumption and more inexpensive direction.
Integrator is common critical function circuit in signal processing chip, it is excellent to signal processing chip overall performance
It is bad to generate significant impact.In the signal processing circuit of early stage, circuit designers generally use resistance, capacitor and amplifier etc.
Continuous time integrator is formed, constitutes required integrator transmission function, and handle signal.But resistance and capacitor
Absolute error limit its application in high-precision circuit.
And switched-capacitor circuit is because having many advantages, such as high time constant precision, good temperature characterisitic, being easy to clock control,
It is applied in analog filter；But conventional switched-capacitor integrator area occupied is very big, such as Tim Denison
People reached the unit gain frequency of 2.5Hz in 2007, and integrating capacitor has reached 100pF, and area is very big, did not had practical
Property, it is not able to satisfy the growth requirement of present miniaturization technologies especially；Fully differential switching capacity integral has been researched and proposed thus
Device, such as: CN201810109015.X can guarantee and fully differential integrator although the patent uses partial positive feedback capacitance structure
Under identical chip area and in high-precision requirement, time constant is larger, or in the case where same time constant, chip face
Product it is smaller, but still there are structures it is more complex, area is larger the problems such as, the development that cannot still meet miniature electronic very well is wanted
It asks.
Utility model content
In view of the above problems existing in the prior art, the purpose of the utility model is to provide a kind of fully differential switching capacity products
Point device, realize guarantee it is high-precision have many advantages, such as that structure is simple, area is small simultaneously, to meet the development of miniature electronic
It is required that.
To achieve the above object, the technical solution adopted in the utility model is as follows:
A kind of fully differential CMOS switched-capacitor integrator is by eight switches, two sampling capacitances, two integrating capacitors and one
Operational amplifier composition, in which: be sequentially connected in series first between the input terminal of forward voltage and the output end of backward voltage and opened
Pass, the first sampling capacitance, the 4th switch and operational amplifier, between the input terminal of backward voltage and the output end of forward voltage
It has been sequentially connected in series the 5th switch, the second sampling capacitance, the 8th switch and operational amplifier, also, has been adopted in first switch with first
Between sample capacitor, the first sampling capacitance and the 4th switch between, the 5th switch the second sampling capacitance between, the second sampling capacitance
It is parallel with a switching branches respectively between the 8th switch, between the 4th switch and the output end of backward voltage, the 8th switch
An integrating capacitor is parallel between the output end of forward voltage.
Preferably, eight switches are NMOS switch.
Preferably, two sampling capacitance is symmetrical and capacitance is equal.
Preferably, two integrating capacitor is symmetrical and capacitance is equal.
Preferably, second switch is connected in parallel between first switch and the first sampling capacitance, and third switch in parallel exists
Between first sampling capacitance and the 4th switch, the 6th switch in parallel is between the 5th switch and the second sampling capacitance, the 7th switch
It is connected in parallel between the second sampling capacitance and the 8th switch；Also, the output end of the second switch is connected with reference voltage, institute
With stating the output termination common mode of third switch, the output end of the 6th switch is connected with reference voltage, the 7th switch
Output termination common mode.
As further preferred scheme, first switch, third switch, the 5th switch and the 7th switch grid with first
Clock signal is connected, and the grid that second switch, the 4th switch, the 6th switch and the 8th switch is connected with second clock signal
It connects, and the first clock signal and second clock signal are opposite signal.
As further preferred scheme, the second clock signal is to concatenate a phase inverter by the first clock signal to obtain.
Compared to the prior art, the advantageous effects of the utility model are:
By sampling circuit structure provided by the utility model, the fully differential CMOS switched-capacitor integrator can be made not only to have
There are high-precision and low-power consumption, and have many advantages, such as that circuit structure is simple, area occupied is small, high-precision micro number electricity can be met
The requirement on road, therefore, the utility model have obvious industrial application value.
Detailed description of the invention
Fig. 1 is a kind of electrical block diagram of fully differential CMOS switched-capacitor integrator provided by the embodiment of the utility model；
Fig. 2 is sampling circuitry phase structural schematic diagram provided by the embodiment of the utility model；
Fig. 3 is integral circuitry phase structural schematic diagram provided by the embodiment of the utility model；
Fig. 4 is the structural schematic diagram of second clock signal provided by the embodiment of the utility model.
Specific embodiment
The technical solution of the utility model is described in further detail below in conjunction with drawings and examples.
Embodiment
Please refer to shown in Fig. 1: a kind of fully differential CMOS switched-capacitor integrator provided in this embodiment, be by eight switch S1~
S8, two sampling capacitance Cs1 and Cs2, two integrating capacitor CI1 and CIA 2 and operational amplifier AMP is formed, in which: first
The input terminal of switch S1 and the input terminal Vip of forward voltage are connected in series, the input terminal of second switch S2 and the first sampling capacitance Cs1
Input terminal be connected in parallel on the output end of first switch S1, the input terminal of third switch S3 and the input terminal of the 4th switch S4 are connected in parallel on
The output end of first sampling capacitance Cs1, integrating capacitor CI1 input terminal and the positive input terminal of operational amplifier AMP are connected in parallel on
The output end of four switch S4, integrating capacitor CI1 output end and the negative output terminal of operational amplifier AMP are connected in parallel on backward voltage
Output end vo n, and the output end of second switch S2 is connected with reference voltage Vref, and the output of third switch S3 terminates common mode
Ground；In addition, the input terminal of the 5th switch S5 and the input terminal Vin of backward voltage are connected in series, the input terminal of the 6th switch S6 and
The input terminal of two sampling capacitance Cs2 is connected in parallel on the output end of the 5th switch S5, the input terminal and the 8th switch S8 of the 7th switch S7
Input terminal be connected in parallel on the output end of the second sampling capacitance Cs2, integrating capacitor CI2 input terminal and operational amplifier AMP's is negative
Input terminal is connected in parallel on the output end of the 8th switch S8, integrating capacitor CIThe positive output end of 2 output end and operational amplifier AMP are simultaneously
It is associated in the output end vo p of forward voltage, and the output end of the 6th switch S6 is connected with reference voltage Vref, the 7th switch S7
Output termination common mode.
Sampling capacitance Cs1 is symmetrical with Cs2 and capacitance is equal.
Integrating capacitor CI1 and CI2 is symmetrical and capacitance is equal.
Eight switch S1~S8 are NMOS switch.Wherein: the grid of switch S1, S3, S5 and S7 are believed with the first clock
Number clk1 is connected, and the grid of switch S2, S4, S6 and S8 are connected with second clock signal clk2, and the first clock signal
Clk1 and second clock signal clk2 is opposite signal.
When the first clock signal is high level (that is: clk1=1), second clock signal is low level (that is: clk2=0)
When, switch S1, S3, S5 and S7 are closed, and switch S2, S4, S6 and S8 are disconnected, at this time at fully differential CMOS switched-capacitor integrator
In sampling phase (please referring to shown in Fig. 2).
Conversely, when the first clock signal is low level (that is: clk1=0), second clock signal is high level (that is: clk2
=1) when, switch S2, S4, S6 and S8 are closed, and switch S1, S3, S5 and S7 are disconnected, and fully differential switching capacity integrates at this time
Device is in integral phase (please referring to shown in Fig. 3).
The second clock signal clk2 is to concatenate a phase inverter by the first clock signal clk1 to obtain, and refers to Fig. 4 institute
Show.
In conclusion it is humorous even can be eliminated since integrator described in the utility model uses full-differential circuits
Wave and common mode interference, thus have the advantages that high-precision and low-power consumption, in addition, the utility model also have circuit structure simply,
The advantages that area occupied is small can meet the requirement of high-precision micro digital circuit, have obvious industrial application value.
It is last it is necessarily pointed out that: the foregoing is merely the preferable specific embodiments of the utility model, but this
The protection scope of utility model is not limited thereto, and anyone skilled in the art discloses in the utility model
In technical scope, any changes or substitutions that can be easily thought of, should be covered within the scope of the utility model.
Claims (7)
1. a kind of fully differential CMOS switched-capacitor integrator, it is characterised in that: be by eight switches, two sampling capacitances, two integrals
Capacitor and an operational amplifier composition, in which: successively gone here and there between the input terminal of forward voltage and the output end of backward voltage
It is associated with first switch, first sampling capacitance, the 4th switch and operational amplifier, in the input terminal and forward voltage of backward voltage
It has been sequentially connected in series the 5th switch, the second sampling capacitance, the 8th switch and operational amplifier between output end, also, has been opened first
Close between the first sampling capacitance, between the first sampling capacitance and the 4th switch, between the 5th switch and the second sampling capacitance, the
Be parallel with a switching branches respectively between two sampling capacitances and the 8th switch, the 4th switch and the output end of backward voltage it
Between, the 8th switch the output end of forward voltage between be parallel with an integrating capacitor.
2. fully differential CMOS switched-capacitor integrator according to claim 1, it is characterised in that: eight switches are that NMOS is opened
It closes.
3. fully differential CMOS switched-capacitor integrator according to claim 1, it is characterised in that: two sampling capacitances it is symmetrical and
Capacitance is equal.
4. fully differential CMOS switched-capacitor integrator according to claim 1, it is characterised in that: two integrating capacitors it is symmetrical and
Capacitance is equal.
5. fully differential CMOS switched-capacitor integrator according to claim 1, it is characterised in that: second switch is connected in parallel on first and opens
It closes between the first sampling capacitance, between the first sampling capacitance and the 4th switch, the 6th switch in parallel exists third switch in parallel
Between 5th switch and the second sampling capacitance, the 7th switch in parallel is between the second sampling capacitance and the 8th switch；Also, it is described
The output end of second switch is connected with reference voltage, the output termination common mode of the third switch, the 6th switch
Output end is connected with reference voltage, the output termination common mode of the 7th switch.
6. fully differential CMOS switched-capacitor integrator according to claim 5, it is characterised in that: first switch, third switch, the
The grid of five switches and the 7th switch is connected with the first clock signal, second switch, the 4th switch, the 6th switch and the 8th
The grid of switch is connected with second clock signal, and the first clock signal and second clock signal are opposite signal.
7. fully differential CMOS switched-capacitor integrator according to claim 6, it is characterised in that: the second clock signal be by
First clock signal concatenates a phase inverter and obtains.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821768223.2U CN209001929U (en) | 2018-10-30 | 2018-10-30 | A kind of fully differential CMOS switched-capacitor integrator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821768223.2U CN209001929U (en) | 2018-10-30 | 2018-10-30 | A kind of fully differential CMOS switched-capacitor integrator |
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| CN209001929U true CN209001929U (en) | 2019-06-18 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112600556A (en) * | 2020-12-09 | 2021-04-02 | 屹世半导体(上海)有限公司 | Sampling circuit based on clock control |
| CN113785300A (en) * | 2020-04-10 | 2021-12-10 | 京东方科技集团股份有限公司 | Fingerprint identification detection circuit, control method thereof and fingerprint identification control chip |
-
2018
- 2018-10-30 CN CN201821768223.2U patent/CN209001929U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113785300A (en) * | 2020-04-10 | 2021-12-10 | 京东方科技集团股份有限公司 | Fingerprint identification detection circuit, control method thereof and fingerprint identification control chip |
| CN112600556A (en) * | 2020-12-09 | 2021-04-02 | 屹世半导体(上海)有限公司 | Sampling circuit based on clock control |
| CN112600556B (en) * | 2020-12-09 | 2024-05-17 | 屹世半导体(上海)有限公司 | Sampling circuit based on clock control |
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Effective date of registration: 20230621 Address after: Room 401, Building 3, Block 2, Gangcheng Square, No. 35, Lane 88, Yunjuan Road, Lingang New Area, Pudong New Area, Shanghai, June 2013 Patentee after: SHANGHAI SHININGIC ELECTRONIC TECHNOLOGY CO.,LTD. Address before: 201620 No. 333, Longteng Road, Shanghai, Songjiang District Patentee before: SHANGHAI University OF ENGINEERING SCIENCE |