CN208836088U

CN208836088U - There is the power operational amplifier of current-limiting protection function based on CDMOS technique

Info

Publication number: CN208836088U
Application number: CN201821713906.8U
Authority: CN
Inventors: 汪洋; 丁利强; 金湘亮; 杨红姣
Original assignee: Xiangtan University
Current assignee: Xiangtan University
Priority date: 2018-10-23
Filing date: 2018-10-23
Publication date: 2019-05-07
Anticipated expiration: 2028-10-23

Abstract

The utility model discloses a kind of power operational amplifiers based on CDMOS technique with current-limiting protection function, including first order operation amplifier unit, second level operation amplifier unit, current-limiting protection unit, biasing circuit；The biasing circuit is connect with first order operation amplifier unit, second level operation amplifier unit; the output end of first order operation amplifier unit is connect with the input terminal of second level operation amplifier unit, and the current-limiting protection unit is connect with the output end of second level operational amplifier unit.The utility model simplifies circuit complexity by improved current source load structure, reduces the number of bias voltage, and then reduces the quiescent dissipation of circuit system；It by increasing current detecting transistor and resistance in operational amplifier output stage come inductive output size of current, and then protects circuit not destroyed when exporting short circuit, enhances the reliability of system.

Description

There is the power operational amplifier of current-limiting protection function based on CDMOS technique

Technical field

The utility model relates to a kind of power operational amplifiers, in particular to a kind of to be protected based on CDMOS technique with current limliting The power operational amplifier of protective function.

Background technique

Power amplification class A amplifier A is widely used in communication system and various electronic equipments, provides for load sufficiently large Signal power, commonly used in the practical applications such as driving motor, voice coil inductance, sound equipment amplification, there is low-frequency range to work, is high-power The features such as output, high efficiency, intelligent control.In recent years, portable with IC design and the continuous development of manufacturing technology Formula, intelligent electronic product are gradually towards lighting, high integration, miniaturization, this is to the integrated electricity of low pressure and low power analoglike The demand on road is also continuing to increase.

Currently, low-voltage, high-current output power class operational amplifier mostly uses greatly BJT technique, but it is electric under this technique The thermal stability on road is poor, and especially circuit system work is in the case where larger output electric current.In order under complex environment, The requirement that bigger range of temperature needs is adapted to, some low-voltage, high-current Power arithmetics based on other techniques has been developed and has put Big device circuit, such as CMOS, CDMOS technique.Traditional operational amplifier mostly uses greatly PMOS to input pipe, is made an uproar with reducing input Sound uses Foldable cascade structure to obtain higher DC current gain.But due to the carrier mobility of PMOS transistor Rate is smaller, so PMOS differential pair input pipe shows lesser mutual conductance, in addition, PMOS tube needs in the case where identical mutual conductance Breadth length ratio can be more much larger than NMOS tube, occupy relatively large chip area, this will will increase design cost.Furthermore tradition Foldable cascade structure in the bias voltage that needs it is relatively more, increase complexity, the circuit of circuit design in this way Whole quiescent dissipation, also add chip layout area.Due to mostly integrate class operational amplifier work output electric current compared with It is small, do not use current-limiting protection functional circuit generally to limit output.Accordingly, it is considered to chip use environment complexity with it is changeable, Conventional operational amplifiers structure is difficult to meet the good performance requirement of high-gain, High-current output, stability.

Current source load circuit generallys use the prior art in Fig. 2 in traditional folded cascode circuitry, although can also To realize that the DC current gain for improving first order Foldable cascade grade operational amplification circuit still needs to increase volume in circuit Outer DC bias circuit, and then increase the complexity of circuit, and additional power consumption can be generated.

Traditional two-stage calculation amplifier circuit realizes that several hundred milliamperes, even greater electric current export due to less, so There is no current-limiting protection circuit.In the operation amplifier circuit of design output larger current, in output stage operational amplification circuit Transistor often uses relatively large breadth length ratio, it is generally thousands of perhaps up to ten thousand when output stage be surprisingly shorted to VDD or When GND, output stage transistor will flow through several hundred milliamperes even high current of several peaces in moment, this is easy to burn out output stage crystalline substance Body pipe, therefore just need to design reliability of the special current-limiting protection circuit to improve operational amplifier.

In traditional operational amplification circuit, the bias of translinear loop circuit transistor, as in Fig. 4 PMOS tube MP5 and The grid voltage biasing circuit of NMOS tube MN9 often directlys adopt simple biasing and realizes, the metal-oxide-semiconductor as diode concatenates is real Existing, the bias stability that this structure generates is relatively poor.

Summary of the invention

In order to solve the above-mentioned technical problem, it is simple, safe and reliable based on CDMOS work to provide a kind of structure for the utility model Skill has the power operational amplifier of current-limiting protection function.

The technical solution that the utility model solves the above problems is: one kind having the function of current-limiting protection based on CDMOS technique Power operational amplifier, including first order operation amplifier unit, second level operation amplifier unit, current-limiting protection unit, biasing Circuit；

The biasing circuit is connect with first order operation amplifier unit, second level operation amplifier unit, is used for the first order Operation amplifier unit and second level operation amplifier unit provide corresponding bias voltage；

The output end of the first order operation amplifier unit is connect with the input terminal of second level operation amplifier unit, for mentioning For high DC current gain；

The input terminal of the second level operation amplifier unit is connect with the output end of first order operation amplifier unit, for increasing Add the maximum amplitude of oscillation of first order operation amplifier element output signal；

The current-limiting protection unit is connect with the output end of second level operational amplifier unit, when output electric current is more than specified After value, operation amplifier unit output in the second level is limited to a fixed value to the grid voltage of pipe by current-limiting protection circuit, without It is influenced, super-high-current is not flowed it through to pipe with protection output and is damaged by the variation inputted.

The above-mentioned power operational amplifier based on CDMOS technique with current-limiting protection function, the first order operation amplifier Unit includes the Foldable cascade amplifying circuit that NMOS inputs pipe, and Foldable cascade amplifying circuit is using active negative Load technology, improves the DC current gain of first order amplifier unit, and Foldable cascade amplifying circuit includes the first to the 8th NMOS Pipe, first to fourth PMOS tube, wherein the grid of the grid of the first NMOS tube, the second NMOS tube connect respectively input signal VIN+, The source electrode of VIN-, the source electrode of the first NMOS tube and the second NMOS tube connects and is connected to the drain electrode of third NMOS tube, third NMOS tube The drain electrode of source electrode and the 4th NMOS tube be connected, the source electrode ground connection of the 4th NMOS tube, the grid of third NMOS tube, the 4th NMOS The grid of pipe is connected and accesses the voltage bias VB of biasing circuit offer；The grid of first PMOS tube is connected with the grid of the second PMOS tube And the voltage bias VB 1 of biasing circuit offer is provided, and the source electrode of the first PMOS tube connects power supply with the source electrode of the second PMOS tube, and first The drain electrode of PMOS tube is connected with the drain electrode of the source electrode of third PMOS tube and the second NMOS tube, the drain electrode of the second PMOS tube and the 4th The drain electrode of the source electrode of NMOS tube and the first NMOS tube is connected, and the grid of the grid of third PMOS tube and the 4th PMOS tube is connected simultaneously Access the voltage bias VB 2 that biasing circuit provides, grid and drain electrode, sixth NMOS tube of the drain electrode of third PMOS tube with the 5th NMOS tube Grid, the grid of the 7th NMOS tube, the grid of the 8th NMOS tube be connected, the source electrode of the 5th NMOS tube and the 7th NMOS tube Drain electrode is connected, and the source electrode ground connection of the 7th NMOS tube, the drain electrode of the source electrode and the 8th NMOS tube of the 6th NMOS tube is connected, and the 8th The source electrode of NMOS tube is grounded.

The above-mentioned power operational amplifier based on CDMOS technique with current-limiting protection function, the second level operation amplifier Unit includes being made of the 9th NMOS tube, the 5th PMOS tube, provides the translinear loop of stable bias to tube grid for output Circuit；The Class-AB output-stage circuit being made of the 7th PMOS tube, the 11st NMOS tube；By first resistor, second resistance, One capacitor, the second capacitor are constituted, the compensation circuit for miller compensation；It is born by the output that load resistance and load capacitance are constituted It carries；4th PMOS tube drain electrode with the grid of the 7th PMOS tube, the source electrode of the 5th PMOS tube, the 9th NMOS tube drain electrode phase Connection, the source electrode of the 7th PMOS tube access power supply, and the drain electrode of the 5th PMOS tube and the source electrode of the 9th NMOS tube are connected rear and with the The drain electrode of six NMOS tubes, the 11st NMOS tube grid be connected, the grid of the 5th PMOS tube access biasing circuit provides inclined VP1, the bias VP2 that the grid access biasing circuit of the 9th NMOS tube provides are pressed, the source electrode of the 11st NMOS tube is grounded, and the 11st The drain electrode of NMOS tube is connected with the drain electrode of the 7th PMOS tube constitutes output end OUT；One end of first resistor in Miller's compensating circuit Be connected with the grid of the 7th PMOS tube, the other end of first resistor is connected with one end of first capacitor, first capacitor it is another End connection output end OUT, one end of second resistance are connected with the grid of the 11st NMOS tube, the other end of second resistance and second One end of capacitor connects, and the other end of the second capacitor connects output end OUT；One termination output end OUT of load resistance, load electricity The other end of resistance is grounded, a termination output end OUT of output load capacitance, the other end ground connection of output load capacitance.

The above-mentioned power operational amplifier based on CDMOS technique with current-limiting protection function, the current-limiting protection circuit packet Include the 6th PMOS tube, the 8th to the 13rd PMOS tube, the tenth NMOS tube, the 12nd to the 18th NMOS tube, third to the 6th electricity Resistance；One termination power of the 3rd resistor, the other end of 3rd resistor connect the source electrode of the 9th PMOS tube, the 8th PMOS tube respectively Source electrode, a termination power of the 4th resistance, the source electrode of the tenth PMOS tube of another termination of the 4th resistance, the grid of the 8th PMOS tube Pole connects the grid of the 7th PMOS tube, and the drain electrode of the 8th PMOS tube connects output end OUT, the grid and the tenth PMOS tube of the 9th PMOS tube Grid, the tenth PMOS tube source electrode be connected, drain electrode and the drain electrode of the 13rd NMOS tube, the 6th PMOS tube of the 9th PMOS tube Grid be connected, the grid of the tenth PMOS tube and drain electrode are connected with the drain electrode of the 14th NMOS tube, the source of the 6th PMOS tube Pole connects power supply, and the drain electrode of the 6th PMOS tube connects the grid of the 7th PMOS tube, the grid of the 13rd NMOS tube, the 14th NMOS tube Grid, the 15th NMOS tube grid be connected with the grid of drain electrode, the 16th NMOS tube, the source electrode of the 13rd NMOS tube, The source electrode of 14 NMOS tubes, the source electrode of the 15th NMOS tube, the 16th NMOS tube source electrode ground connection, the drain electrode of the 16th NMOS tube Connect the drain electrode of the 11st PMOS tube, the grid of the 11st PMOS tube, the grid of the 12nd PMOS tube, the 13rd PMOS tube grid Pole, source electrode, the source electrode of the 12nd PMOS tube, the source electrode of the 13rd PMOS tube of the 11st PMOS tube connect power supply, and the 12nd The drain electrode of PMOS tube is connect with the grid of the drain electrode of the 17th NMOS tube, the tenth NMOS tube, the drain electrode and the tenth of the tenth NMOS tube The grid of one NMOS tube is connected, the source electrode of the tenth NMOS tube ground connection, the grid of the 17th NMOS tube and the 13rd PMOS tube Drain electrode, the drain electrode of the grid of the 18th NMOS tube, the 18th NMOS tube are connected, and the source electrode of the 17th NMOS tube connects the 5th resistance One end, the 12nd NMOS tube source electrode, the other end ground connection of the 5th resistance, the source electrode of the 18th NMOS tube connects the one of the 6th resistance End, the other end ground connection of the 6th resistance, the grid of the 12nd NMOS tube are connected with the grid of the 11st NMOS tube, and the 12nd The drain electrode of NMOS tube meets output end OUT.

The above-mentioned power operational amplifier based on CDMOS technique with current-limiting protection function, the biasing circuit are first Grade operation amplifier unit provides bias voltage VB, VB1, VB2, provides bias voltage VP1, VP2 for second level operation amplifier unit, Biasing circuit includes the 14th to the 27th PMOS tube, the 19th to the 33rd NMOS tube；Wherein the 14th PMOS tube Source electrode connects power supply, and the drain electrode of the 14th PMOS tube connects the source electrode of the 15th PMOS tube, the grid and drain electrode phase of the 15th PMOS tube The grid of the 14th PMOS tube of Lian Bingyu, which links together, provides voltage bias VB 2 for Foldable cascade amplifying circuit, and the 15th The drain electrode of PMOS tube is connected with the drain electrode of the 19th NMOS tube；The source electrode of 19th NMOS tube and the drain electrode of the 21st NMOS tube It is connected, the source electrode ground connection of the source electrode of the 21st NMOS tube, the 22nd NMOS tube, the drain electrode of the 22nd NMOS tube and the The source electrode of 20 NMOS tubes is connected, the grid of the 19th NMOS tube, the grid of the 20th NMOS tube, the 21st NMOS tube Grid, the 22nd NMOS tube grid, the 20th NMOS tube drain electrode link together amplify for Foldable cascade it is single Member provides voltage bias VB；The drain electrode of 20th NMOS tube is connected with the drain electrode of the 17th PMOS tube, the grid of the 17th PMOS tube Exterior control voltage VOH/VOL, the source electrode of the 17th PMOS tube connect the drain electrode of the 16th PMOS tube, the grid of the 16th PMOS tube External a reference source bias voltage V_REF, the source electrode of the 16th PMOS tube connects power supply；The source electrode of 18th PMOS tube connects power supply, and the tenth The drain electrode of eight PMOS tube, the 18th PMOS tube grid, the 24th NMOS tube drain electrode link together and be the first order fortune It calculates amplifying unit and voltage bias VB 1 is provided；The source electrode of 24th NMOS tube meets the drain electrode of the 26th NMOS tube, the 26th NMOS The source electrode of pipe is grounded, the grid of the 24th NMOS tube, the grid of the 25th NMOS tube, the 26th NMOS tube grid, The grid of 27th NMOS tube is connected to VB, the source electrode ground connection of the 27th NMOS tube, and the drain electrode of the 27th NMOS tube connects The source electrode of 25th NMOS tube, the drain electrode of the 25th NMOS tube meet source electrode, the 23rd NMOS of the 28th NMOS tube The grid of pipe, the drain electrode of the 28th NMOS tube connect grid and the drain electrode of the 19th PMOS tube, and the source electrode of the 19th PMOS tube connects Power supply, the grid of the 28th NMOS tube is connected with the grid leak pole of the 29th NMOS tube generates bias VP2 as second level fortune It calculates transconductance linearity loop circuit in amplifying unit and bias is provided；The source electrode of 29th NMOS tube connect the 30th NMOS tube grid and Drain electrode, the source electrode ground connection of the 30th NMOS tube, the grid of the 29th NMOS tube, the drain electrode of the 29th NMOS tube, the 20th The drain electrode of one PMOS tube is connected, the source electrode of the 21st PMOS tube and drain electrode and the 23rd NMOS of the 20th PMOS tube The drain electrode of pipe is connected, and the source electrode ground connection of the 23rd NMOS tube, the source electrode of the 20th PMOS tube connects power supply, the 20th PMOS tube Grid VB1, the grid and the 23rd PMOS of the 21st PMOS tube are connected to together with the grid of the 22nd PMOS tube The grid of pipe is connected to VB2 together；The source electrode of 22nd PMOS tube connects power supply, and the drain electrode of the 22nd PMOS tube connects the 20th The drain electrode of the source electrode of three PMOS tube, the 23rd PMOS tube connects the source electrode of the 25th PMOS tube, the grid of the 27th PMOS tube Pole, the source electrode of the 27th PMOS tube connect power supply, the grid of the 25th PMOS tube, the grid of the 26th PMOS tube and drain electrode It links together and generates bias VP1 and provide bias for transconductance linearity loop circuit in the operation amplifier unit of the second level, the 26th The source electrode of PMOS tube connects grid and the drain electrode of the 24th PMOS tube, and the source electrode of the 24th PMOS tube connects power supply, and the 26th The grid leak of PMOS tube is extremely connected and connects together with the drain electrode of the 32nd NMOS tube, and the source electrode of the 32nd NMOS tube connects second The drain electrode of 17 PMOS tube, the drain electrode of the 33rd NMOS tube, the source electrode ground connection of the 33rd NMOS tube, the 32nd NMOS It manages, the grid of the 33rd NMOS tube links together and is connected to VB；The grid of 31st NMOS tube, the 31st The drain electrode of NMOS tube, the drain electrode of the 25th PMOS tube link together, the source electrode ground connection of the 31st NMOS tube.

The above-mentioned power operational amplifier based on CDMOS technique with current-limiting protection function, the first order operation amplifier In unit, the transistor channel breadth length ratio of the first to the 8th NMOS tube is respectively 250/1,250/1,60/1,30/1,50/1,50/ 1,25/1,25/1, the transistor channel breadth length ratio of first to fourth PMOS tube is respectively 50/1,50/1,150/1,150/1.

The above-mentioned power operational amplifier based on CDMOS technique with current-limiting protection function, the second level operation amplifier In unit, the 5th PMOS tube, the transistor channel breadth length ratio of the 7th PMOS tube are respectively 250/1,17000/1, the 9th NMOS tube, The transistor channel breadth length ratio of 11st NMOS tube is respectively 75/1,5040/1, and first resistor, the resistance value of second resistance are 14.3K Ω, first capacitor, the capacitance of the second capacitor are 4.3pF, and the resistance value of load resistance is 100 Ω, the capacitance of load capacitance For 10pF.

The above-mentioned power operational amplifier based on CDMOS technique with current-limiting protection function, in the current-limiting protection circuit, 6th PMOS tube, the transistor channel breadth length ratio of the 8th to the 13rd PMOS tube be respectively 15/1,200/1,50/1,50/1, 150/1,150/1,250/1, the tenth NMOS tube, the transistor channel breadth length ratio of the 12nd to the 18th NMOS tube are respectively 7.5/ 1,120/1,250/1,250/1,60/1,30/1,50/1,50/1, the resistance value of third to the 6th resistance be respectively 57.6 Ω, 45.8KΩ、19Ω、38.2KΩ。

The above-mentioned power operational amplifier based on CDMOS technique with current-limiting protection function, in the biasing circuit, the tenth The transistor channel breadth length ratio of four to the 27th PMOS tube is respectively 10/1,60/1,41.7/1,50/1,20/1,40/1,20/ 1,60/1,10/1,30/1,400/1,250/1,250/1,400/1, the transistor channel of the 19th to the 33rd NMOS tube is wide It is long than be respectively 20/1,10/1,10/1,5/1,120/1,20/1,10/1,10/1,5/1,75/1,75/1,120/1,20/1, 20/1、10/1。

The utility model has the beneficial effects that: the utility model simplifies circuit by using current source load technology Design, reduce the number of bias voltage, and then reduce the quiescent dissipation of circuit system；The utility model special designing Current-limiting circuit protects circuit when output is shorted to VDD or GND, not destroyed, enhances the reliability of system；In addition, this Grid in the output stage of utility model for output pmos and NMOS tube provides the transconductance linearity loop circuit of bias, passes through two Closed-loop feedback circuit enhances the stability of bias voltage, and then stabilizes the output of operational amplifier.

Detailed description of the invention

Fig. 1 is traditional two-stage trsanscondutance amplifier schematic diagram.

Fig. 2 is conventional current source support structures schematic diagram.

Fig. 3 is the current source load structure principle chart that the utility model uses.

Fig. 4 is the two-stage calculation amplifying unit and current-limiting protection circuit schematic diagram of the utility model.

Fig. 5 is the biasing circuit schematic diagram of the utility model.

Fig. 6 is the two-stage calculation amplifying circuit DC current gain and phase margin simulation curve figure of the utility model.

Fig. 7 is the maximum undistorted ac output current simulation curve figure of two-stage calculation amplifying circuit of the utility model.

When Fig. 8 is that the current-limiting protection circuit output of the utility model is shorted to GND, the emulation of output short circuit current size is bent Line chart.

When Fig. 9 is that the current-limiting protection circuit output of the utility model is shorted to VDD, the emulation of output short circuit current size is bent Line chart.

Specific embodiment

The utility model is further described with reference to the accompanying drawings and examples.

As shown in Figure 3-Figure 5, a kind of power operational amplifier based on CDMOS technique with current-limiting protection function, including First order operation amplifier unit, second level operation amplifier unit, current-limiting protection unit, biasing circuit；The biasing circuit and Level-one operation amplifier unit, the connection of second level operation amplifier unit, are used for first order operation amplifier unit and second level operation Amplifying unit provides corresponding bias voltage；The output end and second level operation amplifier unit of the first order operation amplifier unit Input terminal connection, for providing high DC current gain；The input terminal of the second level operation amplifier unit and first order operation The output end of amplifying unit connects, for increasing the maximum amplitude of oscillation of first order operation amplifier element output signal；The current limliting is protected Shield unit is connect with the output end of second level operational amplifier unit, after exporting electric current overrate, current-limiting protection circuit By the output of second level operation amplifier unit to the grid voltage pullup or pulldown of pipe (in output pmos grid potential Draw, output nmos transistor grid potential be pulled down) to a fixed level value, so that output transistor output limit Constant current does not flow it through super-high-current to pipe with protection output and damages.

The first order operation amplifier unit includes the Foldable cascade amplifying circuit that NMOS inputs pipe, collapsible Cascade amplifying circuit uses active load technology, improves the DC current gain of first order amplifier unit, Foldable cascade Amplifying circuit includes the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS Pipe MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the first PMOS tube MP1, the second PMOS tube MP2, Third PMOS tube MP3, the 4th PMOS tube MP4, wherein the grid of the grid of the first NMOS tube MN1, the second NMOS tube MN2 connects respectively The source electrode of input signal VIN+, VIN-, the source electrode of the first NMOS tube MN1 and the second NMOS tube MN2 connect and are connected to the 3rd NMOS The drain electrode of the drain electrode of pipe MN3, the source electrode and the 4th NMOS tube MN4 of third NMOS tube MN3 is connected, the source of the 4th NMOS tube MN4 Pole is grounded GND, and the grid of third NMOS tube MN3, the grid of the 4th NMOS tube MN4 are connected and access the bias of biasing circuit offer VB；The grid of first PMOS tube MP1 is connected with the grid of the second PMOS tube MP2 and accesses the voltage bias VB 1 of biasing circuit offer, the The source electrode of the source electrode of one PMOS tube MP1 and the second PMOS tube MP2 connect power vd D, the drain electrode and third of the first PMOS tube MP1 The drain electrode of the source electrode of PMOS tube MP3 and the second NMOS tube MN2 are connected, the drain electrode of the second PMOS tube MP2 and the 4th NMOS tube MN4 Source electrode and the first NMOS tube MN1 drain electrode be connected, the grid of third PMOS tube MP3 and the grid phase of the 4th PMOS tube MP4 Connect and access the voltage bias VB 2 of biasing circuit offer, the drain electrode of third PMOS tube MP3 and the grid of the 5th NMOS tube MN5 and drain electrode, Grid, the grid of the 7th NMOS tube MN7, the grid of the 8th NMOS tube MN8 of 6th NMOS tube MN6 is connected, the 5th NMOS tube The drain electrode of the source electrode of MN5 and the 7th NMOS tube MN7 is connected, and the source electrode of the 7th NMOS tube MN7 is grounded GND, the 6th NMOS tube MN6 The drain electrode of source electrode and the 8th NMOS tube MN8 be connected, the source electrode of the 8th NMOS tube MN8 is grounded GND.

The second level operation amplifier unit includes being made of the 9th NMOS tube MN9, the 5th PMOS tube MP5, for output The transconductance linearity loop circuit for stablizing bias is provided tube grid；It is made of the 7th PMOS tube MP7, the 11st NMOS tube MN11 Class-AB output-stage circuit；It is made of first resistor R1, second resistance R2, first capacitor C1, the second capacitor C2, for close Strangle the Miller's compensating circuit of compensation；The output loading being made of load resistance RL and load capacitance CL；The 4th PMOS tube MP4 Drain electrode be connected with the drain electrode of the grid of the 7th PMOS tube MP7, the source electrode, the 9th NMOS tube MN9 of the 5th PMOS tube MP5, The source electrode of seven PMOS tube MP7 accesses power supply, the drain electrode of the 5th PMOS tube MP5 and the source electrode of the 9th NMOS tube MN9 be connected afterwards and with The drain electrode of 6th NMOS tube MN6, the grid of the 11st NMOS tube MN11 are connected, and the grid of the 5th PMOS tube MP5 accesses biasing The bias VP2 that the grid access biasing circuit for the bias VP1, the 9th NMOS tube MN9 that circuit provides provides, the 11st NMOS tube The source electrode of MN11 is grounded GND, and the drain electrode of the 11st NMOS tube MN11 is connected with the drain electrode of the 7th PMOS tube MP7 constitutes output end OUT；One end of first resistor R1 is connected with the grid of the 7th PMOS tube MP7 in Miller's compensating circuit, and first resistor R1's is another One end is connected with one end of first capacitor C1, and the other end of first capacitor C1 connects output end OUT, one end of second resistance R2 with The grid of 11st NMOS tube MN11 is connected, and the other end of second resistance R2 is connect with one end of the second capacitor C2, the second capacitor The other end of C2 connects output end OUT；The other end ground connection of termination an output end OUT, load resistance RL of load resistance RL The other end of termination an output end OUT, output load capacitance CL of GND, output load capacitance CL are grounded GND；The trsanscondutor Property loop circuit in increase output using two feedback control loops to the stability of tube grid voltage, so that it is defeated to stablize operational amplifier Outlet voltage.

The current-limiting protection circuit includes the 6th PMOS tube MP6, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10, the 11st PMOS tube MP11, the 12nd PMOS tube MP12, the 13rd PMOS tube MP13, the tenth NMOS tube MN10, 12nd NMOS tube MN12, the 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th NMOS tube MN15, the 16th NMOS tube MN16, the 17th NMOS tube MN17, the 18th NMOS tube MN18,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6；A termination power vd D of the 3rd resistor R3, the other end of 3rd resistor R3 meet the 9th PMOS respectively The source electrode of the source electrode of pipe MP9, the 8th PMOS tube MP8, a termination power vd D of the 4th resistance R4, the other end of the 4th resistance R4 The source electrode of the tenth PMOS tube MP10 is connect, the grid of the 8th PMOS tube MP8 meets the grid of the 7th PMOS tube MP7, the 8th PMOS tube MP8 Drain electrode meet output end OUT, the grid of the grid of the 9th PMOS tube MP9 and the tenth PMOS tube MP10, the tenth PMOS tube MP10 Source electrode is connected, and the drain electrode of the 9th PMOS tube is connected with the grid of the drain electrode of the 13rd NMOS tube MN13, the 6th PMOS tube MP6 It connects, the grid of the tenth PMOS tube and drain electrode are connected with the drain electrode of the 14th NMOS tube, and the source electrode of the 6th PMOS tube MP6 connects power supply VDD, the drain electrode of the 6th PMOS tube MP6 connect the grid of the 7th PMOS tube MP7, the grid of the 13rd NMOS tube MN13, the 14th The grid of NMOS tube MN14, the 15th NMOS tube MN15 grid be connected with the grid of drain electrode, the 16th NMOS tube MN16, The source electrode of 13 NMOS tube MN13, the source electrode of the 14th NMOS tube MN14, the 15th NMOS tube MN15 source electrode, the 16th NMOS The source electrode of pipe MN16 is grounded GND, and the drain electrode of the 16th NMOS tube MN16 meets drain electrode, the 11st PMOS of the 11st PMOS tube MP11 The grid of pipe MP11, the grid of the 12nd PMOS tube MP12, the 13rd PMOS tube MP13 grid, the 11st PMOS tube MP11's Source electrode, the source electrode of the 12nd PMOS tube MP12, the 13rd PMOS tube MP13 source electrode connect power vd D, the 12nd PMOS tube The drain electrode of MP12 is connected with the grid of the drain electrode of the 17th NMOS tube MN17, the tenth NMOS tube MN10, the tenth NMOS tube MN10 Drain electrode be connected with the grid of the 11st NMOS tube MN11, the source electrode of the tenth NMOS tube MN10 ground connection, the 17th NMOS tube The drain and gate of the grid of MN17 and the 18th NMOS tube MN18 are connected, and the source electrode of the 17th NMOS tube MN17 connects the 5th electricity One end of R5, the source electrode of the 12nd NMOS tube MN12 are hindered, the other end of the 5th resistance R5 is grounded GND, the 18th NMOS tube MN18 Source electrode connect one end of the 6th resistance R6, the other end of the 6th resistance R6 is grounded GND, the grid of the 12nd NMOS tube MN12 and the The grid of 11 NMOS tube MN11 is connected, and the drain electrode of the 12nd NMOS tube MN12 meets output end OUT.

The biasing circuit provides bias voltage VB, VB1, VB2 for first order operation amplifier unit, is that second level operation is put Big unit provides bias voltage VP1, VP2, and biasing circuit includes the 14th PMOS tube MP14, the 15th PMOS tube MP15, the tenth Six PMOS tube MP16, the 17th PMOS tube MP17, the 18th PMOS tube MP18, the 19th PMOS tube MP19, the 20th PMOS tube MP20, the 21st PMOS tube MP21, the 22nd PMOS tube MP22, the 23rd PMOS tube MP23, the 24th PMOS tube MP24, the 25th PMOS tube MP25, the 26th PMOS tube MP26, the 27th PMOS tube MP27, the 19th NMOS tube MN19, the 20th NMOS tube MN20, the 21st NMOS tube MN21, the 22nd NMOS tube MN22, the 23rd NMOS tube MN23, the 24th NMOS tube MN24, the 25th NMOS tube MN25, the 26th NMOS tube MN26, the 27th NMOS tube MN27, the 28th NMOS tube MN28, the 29th NMOS tube MN29, the 30th NMOS tube MN30, the 31st NMOS tube MN31, the 32nd NMOS tube MN32, the 33rd NMOS tube MN33；Wherein the source electrode of the 14th PMOS tube MP14 connects power supply VDD, the drain electrode of the 14th PMOS tube MP14 connect the source electrode of the 15th PMOS tube MP15, the grid of the 15th PMOS tube MP15 and leakage Extremely it is connected and links together with the grid of the 14th PMOS tube and provides voltage bias VB 2 for Foldable cascade amplifying circuit, the The drain electrode of 15 PMOS tube MP15 is connected with the drain electrode of the 19th NMOS tube MN19；The source electrode and second of 19th NMOS tube MN19 The drain electrode of 11 NMOS tube MN21 is connected, the source electrode of the source electrode of the 21st NMOS tube MN21, the 22nd NMOS tube MN22 It is grounded GND, the drain electrode of the 22nd NMOS tube MN22 is connected with the source electrode of the 20th NMOS tube MN20, the 19th NMOS tube The grid of MN19, the grid of the 20th NMOS tube MN20, the 21st NMOS tube MN21 grid, the 22nd NMOS tube MN22 The drain electrode of grid, the 20th NMOS tube MN20 link together and provide voltage bias VB for Foldable cascade amplifying unit；The The drain electrode of 20 NMOS tube MN20 is connected with the drain electrode of the 17th PMOS tube MP17, and the grid of the 17th PMOS tube MP17 is external Voltage VOH/VOL is controlled, the source electrode of the 17th PMOS tube MP17 connects the drain electrode of the 16th PMOS tube MP16, the 16th PMOS tube The external a reference source bias voltage V of the grid of MP16_REF, the source electrode of the 16th PMOS tube MP16 meets power vd D；18th PMOS tube The source electrode of MP18 meets power vd D, the drain electrode of the 18th PMOS tube MP18, the grid of the 18th PMOS tube MP18, the 24th The drain electrode of NMOS tube MN24 links together and provides voltage bias VB 1 for first order operation amplifier unit；24th NMOS tube The source electrode of MN24 connects the drain electrode of the 26th NMOS tube MN26, and the source electrode of the 26th NMOS tube MN26 is grounded GND, and the 24th The grid of NMOS tube MN24, the grid of the 25th NMOS tube MN25, the grid of the 26th NMOS tube MN26, the 27th The grid of NMOS tube MN27 is connected to VB, and the source electrode of the 27th NMOS tube MN27 is grounded GND, the 27th NMOS tube MN27's Drain electrode connects the source electrode of the 25th NMOS tube MN25, and the drain electrode of the 25th NMOS tube MN25 connects the 28th NMOS tube MN28's The grid of source electrode, the 23rd NMOS tube MN23, the drain electrode of the 28th NMOS tube MN28 connect the grid of the 19th PMOS tube MP19 Pole and drain electrode, the source electrode of the 19th PMOS tube MP19 connect power vd D, the grid and the 29th of the 28th NMOS tube MN28 The grid leak pole of NMOS tube MN29, which is connected, to be generated bias VP2 and provides partially for transconductance linearity loop circuit in the operation amplifier unit of the second level Pressure；The source electrode of 29th NMOS tube MN29 connects grid and the drain electrode of the 30th NMOS tube MN30, the 30th NMOS tube MN30's Source electrode is grounded GND, the grid of the 29th NMOS tube MN29, the drain electrode of the 29th NMOS tube MN29, the 21st PMOS tube The drain electrode of MP21 is connected, the drain electrode of the source electrode and the 20th PMOS tube MP20 of the 21st PMOS tube MP21, the 23rd The drain electrode of NMOS tube MN23 is connected, and the source electrode of the 23rd NMOS tube MN23 is grounded GND, the source electrode of the 20th PMOS tube MP20 Power vd D is met, the grid of the 20th PMOS tube MP20 is connected to VB1 together with the grid of the 22nd PMOS tube MP22, and second The grid of 11 PMOS tube MP21 and the grid of the 23rd PMOS tube MP23 are connected to VB2 together；22nd PMOS tube The source electrode of MP22 meets power vd D, and the drain electrode of the 22nd PMOS tube MP22 connects the source electrode of the 23rd PMOS tube MP23, and the 20th The drain electrode of three PMOS tube MP23 connects the source electrode of the 25th PMOS tube MP25, the grid of the 27th PMOS tube MP27, and the 20th The source electrode of seven PMOS tube MP27 meets power vd D, the grid of the grid of the 25th PMOS tube MP25, the 26th PMOS tube MP26 It links together with drain electrode and generates bias VP1 and provide bias for transconductance linearity loop circuit in the operation amplifier unit of the second level, the The source electrode of 26 PMOS tube MP26 connects grid and the drain electrode of the 24th PMOS tube MP24, the source of the 24th PMOS tube MP24 Pole meets power vd D, and the grid leak of the 26th PMOS tube MP26 is extremely connected and is connected in one with the drain electrode of the 32nd NMOS tube MN32 It rises, the source electrode of the 32nd NMOS tube MN32 connects the leakage of the drain electrode of the 27th PMOS tube MP27, the 33rd NMOS tube MN33 The source electrode of pole, the 33rd NMOS tube MN33 is grounded GND, the grid of the 32nd NMOS tube MN32, the 33rd NMOS tube MN33 Pole links together and is connected to VB；The drain electrode of the grid, the 31st NMOS tube MN31 of the 31st NMOS tube MN31, The drain electrode of 25 PMOS tube MP25 links together, and the source electrode of the 31st NMOS tube MN31 is grounded GND.

In the first order operation amplifier unit, the transistor channel breadth length ratio of the first to the 8th NMOS tube is respectively 250/ 1,250/1,60/1,30/1,50/1,50/1,25/1,25/1, the transistor channel breadth length ratio difference of first to fourth PMOS tube It is 50/1,50/1,150/1,150/1.

In the second level operation amplifier unit, the wide length of transistor channel of the 5th PMOS tube MP5, the 7th PMOS tube MP7 Than being respectively 250/1,17000/1, the 9th NMOS tube MN9, the 11st NMOS tube MN11 transistor channel breadth length ratio be respectively 75/1,5040/1, first resistor R1, second resistance R2 resistance value be 14.3K Ω, the appearance of first capacitor C1, the second capacitor C2 Value is 4.3pF, and the resistance value of load resistance RL is 100 Ω, and the capacitance of load capacitance CL is 10pF.

In the current-limiting protection circuit, the transistor channel breadth length ratio of the 6th PMOS tube MP6, the 8th to the 13rd PMOS tube Respectively 15/1,200/1,50/1,50/1,150/1,150/1,250/1, the tenth NMOS tube MN10, the 12nd to the 18th The transistor channel breadth length ratio of NMOS tube is respectively 7.5/1,120/1,250/1,250/1,60/1,30/1,50/1,50/1, the The resistance value of three to the 6th resistance is respectively 57.6 Ω, 45.8K Ω, 19 Ω, 38.2K Ω.

In the biasing circuit, the transistor channel breadth length ratio of the 14th to the 27th PMOS tube is respectively 10/1,60/ 1, the 41.7/1,50/1,20/1,40/1,20/1,60/1,10/1,30/1,400/1,250/1,250/1,400/1, the 19th to The transistor channel breadth length ratio of 33rd NMOS tube is respectively 20/1,10/1,10/1,5/1,120/1,20/1,10/1,10/ 1、5/1、75/1、75/1、120/1、20/1、20/1、10/1。

In two-stage calculation amplifier provided by the utility model, the 5th NMOS tube MN5, in first order operation amplifier unit Six NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8 form current source load, wherein the 5th NMOS tube MN5, the 6th The breadth length ratio of NMOS tube MN6 transistor is the 7th NMOS tube MN7,2 times of the 8th NMOS tube MN8 transistor breadth length ratio.Circuit is just The 5th NMOS tube MN5, the work of the 6th NMOS tube MN6 transistor are in saturation region, the 7th NMOS tube MN7, the 8th under normal operating condition NMOS tube MN8 transistor works in linear zone.

Such as the output resistance of the enough current source loads of Fig. 2 prior art are as follows:

Wherein g_m6, g_mb6The mutual conductance and backgate mutual conductance of respectively the 6th NMOS tube, r₀₆,r₀₈Respectively the six, the 8th NMOS The saturation conduction resistance of transistor.

Current source load such as Fig. 3 that the utility model uses, since the 6th NMOS tube MN6, the 5th NMOS tube MN5 work exist Saturation region, the 7th NMOS tube MN7, the 8th NMOS tube MN8 pipe work in linear zone, and

V_DSN7≤2(V_GSN7-V_THN7)

Wherein V_DSN7, V_GSN7The respectively drain-source voltage and gate source voltage of the 7th NMOS tube, V_THN7For the threshold of the 7th NMOS tube Threshold voltage.Flow through the electric current I of the 7th NMOS tube_DN7It is obtained by following formula:

μ_nFor the mobility of NMOS tube electronics, C_oxFor the gate oxide capacitance of metal-oxide-semiconductor unit area,It is The breadth length ratio of seven NMOS tube channels.The 7th NMOS tube MN7 of transistor is equivalent to a resistance under this kind of operating condition, the resistance value are as follows:

The resistance is much larger than conducting resistance when transistor saturation conduction；

The DC current gain A of two-stage calculation amplifying circuit_v01Expression formula:

Wherein g_mn1、g_mn5、g_mn10Respectively first, five, the mutual conductance of the tenth NMOS tube, g_mp3、g_mp7Respectively third, the 7th The mutual conductance of PMOS tube, g_mpb3、g_mnb5The respectively backgate mutual conductance of third PMOS tube, the 5th NMOS tube, r_0p1、r_0p3、r_0p7Respectively The first, the saturation conduction resistance of third, the 7th PMOS tube, r_0n5、r_0n10The saturation conduction electricity of respectively the five, the tenth NMOS tubes Resistance, R_0n7For the 7th NMOS tube work linear zone resistance.

The DC current gain A for the two-stage calculation amplifying circuit that the load of prior art current source is constituted_v02Expression formula:

Due to

R_on7>r_on7

It can obtain:

A_v01>A_v02

Wherein r_0n7For the saturation conduction resistance of the 7th NMOS tube.

The two-stage calculation amplifier circuit of the utility model uses current source load as shown in Figure 3, with prior art phase Than reducing the number of biasing pressure, while reducing the quiescent dissipation of circuit system.

The current-limiting protection circuit is for limiting the two-stage calculation amplifier output stage the 7th PMOS tube MP7 and the tenth NMOS The maximum current that pipe MN10 flows through, in the case that output is shorted to VDD or GND, current-limiting protection circuit work will be exported Electric current is limited to a setting value, and the utility model is set in 800mA or so.

Be respectively adopted in the current-limiting protection circuit the 8th PMOS tube MP8 and the 12nd NMOS tube MN12 detect respectively this two The electric current flowed through in the 7th PMOS tube MP7 and the 11st NMOS tube MN11 of grade operational amplification circuit output stage.

In current-limiting protection circuit, for export the 7th PMOS tube MP7 current limliting protection circuit include, the 6th PMOS tube MP6, 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10, the 13rd NMOS tube MN13, 14 NMOS tube MN14, the 15th NMOS tube MN15, the 16th NMOS tube MN16 and 3rd resistor R3, the 4th resistance R4 and Three capacitor C3.Wherein the resistance value of the 4th resistance R4 of resistance value ratio of 3rd resistor R3 is much larger, the 9th PMOS tube MP9 under normal condition Source potential it is higher, the voltage drop on 3rd resistor R3 is smaller, be no more than its threshold voltage, at this point, flowing through the 8th PMOS tube The electric current of MP8 is smaller, and the voltage drop similarly generated on the 4th resistance R4 is smaller compared to the voltage drop on 3rd resistor R3, So the source potential of the tenth PMOS tube MP10 is high compared with the 9th PMOS tube MP9 source potential；Due to the 9th PMOS tube MP9 and the tenth The grid of PMOS tube MP10 is connected, so grid voltage is identical, flows through the electric current phase of the 9th PMOS tube MP9 and the tenth PMOS tube MP10 Together, the 9th PMOS tube MP9 uses diode connection, works in saturation region, and the source potential of the tenth PMOS tube MP10 is higher, so Tenth PMOS tube MP10 work just can guarantee that the electric current for flowing through the 8th PMOS tube MP8 of current detecting is smaller in linear zone, this feelings The grid potential of the 9th PMOS tube MP9 and the source potential of the 9th PMOS tube MP9 are close under condition, are high level, this when The grid of 6th PMOS tube MP6 is high level, and the 6th PMOS tube MP6 is not turned on, and the 7th PMOS tube MP7 is worked normally；Work as output In the case that end is shorted to GND, the 7th PMOS tube MP7 will flow through very high current, flow through in the 8th PMOS tube MP8 in this case Electric current increase, the pressure drop generated on corresponding 3rd resistor R3 increases, and the current potential of the 9th PMOS tube MP9 source electrode reduces, the 9th The drain potential of PMOS tube MP9 follows source potential to reduce, and the grid potential of the 6th PMOS tube MP6 reduces at this time, is lower than one Threshold V T P, the 6th PMOS tube MP6 conducting, the drain potential of the 6th PMOS tube MP6 is drawn high, due to the 6th PMOS tube MP6 Drain electrode be connected with the grid of the 7th PMOS tube MP7, the grid potential of such 7th PMOS tube MP7 is fixed on a restriction Value, the electric current for then flowing through the 7th PMOS tube MP7 are limited at 800mA or so, are unlikely to damage because output is shorted to ground GND It is bad.The breadth length ratio of the 7th PMOS tube MP7 pipe is up to 17000 in the utility model, so if not designing current-limiting protection circuit, it is defeated It will be generated huge current flow (several amperes) when being shorted out, and then moment can burn out chip.

The design rule of the 8th PMOS tube MP8 and 3rd resistor R3, the 4th resistance R4 are as follows in current-limiting circuit:

Ignore channel-length modulation, the 7th PMOS tube MP7 electric current I_MP7With gate source voltage V_GSP7Calculation formula such as Under:

V_GSP7=VDD-V₀₁

μ_pFor the mobility in PMOS tube hole, V_GSP7For the gate source voltage of the 7th PMOS tube, V_THP7For the threshold of the 7th PMOS tube Threshold voltage, VDD are supply voltage, V₀₁For the grid end voltage of the 7th PMOS tube,It is long for the width of the 7th PMOS tube channel Than；

Flow through the electric current I on 3rd resistor R3_R3Are as follows:

I_R3=I_MP8+I_MP9=I_MP8+I_MN14

I_MP8、I_MP9、I_MN14It respectively flows through the electric current in the eight, the 9th PMOS tube and flows through the electricity of the 14th NMOS tube Stream.

Flow through the electric current of the 8th PMOS tube MP8 are as follows:

V_GSP8=VDD- (I_MP8+I_MN14)R₃-V₀₁

Wherein V_GS8For the gate source voltage of the 8th PMOS tube, V_THP8For the threshold voltage of the 8th PMOS tube, VDD is power supply electricity Pressure, R₃For the resistance value of 3rd resistor.

It is obtained according to various above:

During the electric current flowed through in 7th PMOS tube MP7 is gradually increased, the electric current flowed through in the 8th PMOS tube MP8 also will Increase, the source potential of the 9th PMOS tube MP9 will decline, as the 9th PMOS tube MP9 source potential and the tenth PMOS tube MP10 When source potential is equal, as the 9th PMOS tube MP9 drain potential turns low turning point by high, then flows through the 8th PMOS tube The calculation method of MP8 size of current is as follows:

V_b=VDD-I_MN14R₄

I_MP9=I_MP10=I_MN14

It can obtain:

And then it can obtain

Wherein Va, Vb are respectively a in current-limiting circuit, and the current potential of b point, R4 is the resistance value of the 4th resistance, I_MP10To flow through Electric current in ten PMOS tube.

As long as the maximum current value I in the 7th PMOS tube MP7 is flowed through in setting in the utility model_MP7According to the work of transistor Skill parameter, can by select the 8th PMOS tube MP8 of current detecting transistor breadth length ratio, and then come determine 3rd resistor R3 and The ratio of 4th resistance R4.The breadth length ratio of the 8th PMOS tube MP8 is 200:1, the 4th resistance R4 and third electricity in the utility model The ratio for hindering R3 is about R4:R3 ≈ 795:1

In current-limiting protection circuit, the protection circuit to the 11st NMOS tube MN11 current limliting includes, the 11st PMOS tube MP11, 12nd PMOS tube MP12, the 13rd PMOS tube MP13, the tenth NMOS tube MN10, the 12nd NMOS tube MN12, the 17th NMOS Pipe MN17, the 18th NMOS tube MN18, the 5th resistance R5, the 6th resistance R6.Wherein the 5th resistance of resistance value ratio of the 6th resistance R6 The resistance value of R5 is much larger, and the source potential of the 17th NMOS tube MN17 is lower under normal condition, the voltage drop on the 5th resistance R5 It is smaller, it is no more than its threshold voltage, at this point, the electric current for flowing through the 12nd NMOS tube MN12 is smaller, similarly in the 5th resistance R5 The voltage drop of upper generation is smaller compared to the voltage drop on 3rd resistor R3 (because flowing through the 17th NMOS tube under normal circumstances The electric current of MN17 and the 18th NMOS tube MN18 are suitable), so the source potential of the tenth NMOS tube MN10 is compared with the 18th NMOS tube The source potential of MN18 is high；Since the grid of the 17th NMOS tube MN17 and the 18th NMOS tube MN18 is connected, so grid voltage phase Together, the electric current for flowing through the 17th NMOS tube MN17 and the 18th NMOS tube MN18 is identical, and the 18th NMOS tube MN18 uses two poles Pipe connection works in saturation region, and the source potential of the 17th NMOS tube MN17 is higher, so the 17th NMOS tube MN17 work exists Linear zone just can guarantee that the electric current for flowing through the 12nd NMOS tube MN12 is smaller, in this case the leakage of the 11st NMOS tube MN11 pipe The source potential of electrode potential and the 11st NMOS tube MN11 are close, are low level, this when the tenth NMOS tube MN10 grid Extremely low level, the 6th PMOS tube MP6 are not turned on, and the 11st NMOS tube MN11 is worked normally；When output end is shorted to the feelings of VDD Under condition, the 11st NMOS tube MN11 will flow through very high current, and the electric current flowed through in the 12nd NMOS tube MN12 in this case increases Greatly, the pressure drop generated on corresponding 3rd resistor R3 increases, and the current potential of the 17th NMOS tube MN17 source electrode increases, the 17th NMOS The drain potential of pipe MN17 follows source potential to increase, and the grid potential of the tenth NMOS tube MN10 increases at this time, is higher than a threshold Threshold voltage VTN, the tenth NMOS tube MN10 conducting, the drain potential of the 11st NMOS tube MN11 is dragged down, due to the tenth NMOS tube The drain electrode of MN10 is connected with the grid of the 11st NMOS tube MN11, and the grid potential of such 11st NMOS tube MN11 is fixed on One limit value, the electric current for then flowing through the 11st NMOS tube MN11 are limited at 800mA or so, are unlikely to be shorted to because of output Power vd D and damage.The breadth length ratio of the 11st NMOS tube MN11 is up to 8400 in the utility model, so if not designing current limliting Circuit is protected, output will generate huge current flow (several amperes) when being shorted to VDD, and then moment can burn out chip.

The 12nd NMOS tube MN12 and the 5th resistance R5, the design principle of the 6th resistance R6 are as follows in current-limiting circuit:

Ignore channel-length modulation, flows through the 11st NMOS tube MN11 electric current I_MN11, the 11st NMOS tube MN11 grid Source voltage V_GSN11It calculates as follows:

V_GSN11=V₀₂

V₀₂For the grid end voltage of the 11st NMOS tube, V_THN11For the threshold voltage of the 11st NMOS tube.

Flow through the electric current on the 5th resistance R5 are as follows:

I_R5=I_MN12+I_MN17=I_MN12+I_MP13

I_MN17And I_MP13Respectively flow through the electric current in the 12nd NMOS tube and the 13rd PMOS tube.

Flow through the electric current of the 12nd NMOS tube MN12 are as follows:

V_GSN12=V₀₂-(I_MN12+I_MP13)R₅

R₅For the resistance value of the 5th resistance, V_THN12For the threshold voltage of the 12nd NMOS tube, V_GSN12For the 12nd NMOS tube Gate source voltage.

It is obtained according to various above:

During the electric current flowed through in 11st NMOS tube MN11 is gradually increased, the electricity that is flowed through in the 12nd NMOS tube MN12 Stream will also increase, and the source potential of the 17th NMOS tube MN17 will rise, when the 17th NMOS tube MN17 source potential and the tenth When the source potential of eight NMOS tube MN18 is equal, as the 17th NMOS tube MN17 drain potential by low turn of high turning point, this When flow through the 12nd NMOS tube MN12 size of current calculation method it is as follows:

V_d=I_MN18R₆

I_MN17=I_MN18=I_MP13

It can obtain:

And then it can obtain

Wherein Vc, Vd are respectively the voltage of c, d point in current-limiting circuit.

As long as the maximum current value I in the 11st NMOS tube MN11 is flowed through in setting_MN11It, can according to the technological parameter of transistor With by the breadth length ratio for selecting the 12nd NMOS tube MN12, and then come the ratio that determines the 5th resistance R5 and the 6th resistance R6.This It is about R6 that the breadth length ratio of the 12nd NMOS tube MN12, which is the ratio of 120:1, the 6th resistance R6 and the 5th resistance R5, in utility model: R5≈2010:1

The biasing circuit is as shown in figure 5, the wherein external reference voltage V of the grid of the 16th PMOS tube MP16_REF, the tenth The external control level VOH/VOL of the grid of seven PMOS tube MP17, when the 17th PMOS tube MP17 grid connects VOH high level, partially Circuits do not work, and biasing circuit cannot provide normal bias for two-stage calculation amplifying circuit, and two-stage calculation amplifier circuit is not Work；When the grid of the 17th PMOS tube MP17 connects VOL low level, bias circuit portion provides partially for two-stage calculation amplifier Pressure, operational amplifier work normally.

5th PMOS tube MP5 in the biasing circuit, the 24th PMOS tube MP24, the 26th PMOS tube MP26 and 7th PMOS tube MP7 constitutes a translinear loop；9th NMOS tube MN9, the 29th NMOS tube in the biasing circuit MN29, the 30th NMOS tube MN30 and the 11st NMOS tube MN11 constitute another translinear loop.In translinear loop The effect of 15th PMOS tube MP15, the 9th NMOS tube MN9 is only two-stage calculation amplification output stage quiescent biasing, they are to two The unity gain bandwidth product GBW of grade operational amplifier does not work.

In the biasing circuit the 23rd NMOS tube MN23 and the 27th PMOS tube MP27 respectively with the trsanscondutor Property loop circuit constitute feedback control loop.Feedback mechanism is as follows:

Increase branch current where the 20th PMOS tube MP20, is not having In the case where 23rd NMOS tube MN23, the current potential of VP1 point can be increased, so that the grid potential of the 9th NMOS tube MN9 It increases, influences the static grid voltage of the 11st NMOS tube MN11, and then influence the stability of output electric current.In the utility model Increase by the 23rd NMOS tube MN23, when the branch current where the 20th PMOS tube MP20 increases, the 23rd NMOS tube The presence of the shunting of MN23 makes the electric current for flowing through the 21st PMOS tube MP21 can't be very big, so that the voltage of VP1 Very big raising is not had.Nevertheless, flowing through the electric current of the 21st PMOS tube MP21 can also increased, VP1 point current potential meeting Have and slightly improves, but after VP1 is improved, due to the 28th NMOS tube MN28 and the 29th NMOS tube MN29 common gate connection, So the electric current that the 28th NMOS tube MN28 flows through will increase, and the 28th NMOS tube MN28 source potential increases, in turn So that the grid source of the 23rd NMOS tube MN23 further increases, so that the electric current that the 23rd NMOS tube MN23 flows through is further Increase so that the electric current for flowing through the 21st PMOS tube MP21 reduces so that VP1 current potential reduces, it is enough at feed back into One step stablizes the current potential of VP1, to stablize the output of two-stage calculation amplifier.

In the biasing circuit, if flowed through in branch where making the 33rd NMOS tube MN33 for some reason Electric current increases, and in the presence of no 27th PMOS tube MP27 pipe, the current potential of VP2 point is increased, translinear loop electricity The grid potential of 15 PMOS tube MP15 pipe of Lu Zhong increases, so that the grid potential of the 11st NMOS tube MN11 increases, Influence the stability of output stage.But the 27th PMOS tube MP27 is added, since the presence of shunting to flow through the 32nd The electric current of NMOS tube MN32 reduces, and is unlikely to follow and flows through the increase of electric current in the 33rd NMOS tube MN33 and increase, in turn So that VP2 will not be increased too much, but the current potential of VP2 still will receive the 33rd NMOS tube MN33 electric current increase and slightly It increases, this electric current that branch where the 25th PMOS tube MP25 will be made to flow through increased, so that the 25th PMOS The source potential of pipe MP25 declines, due to the source electrode phase of the grid and the 25th PMOS tube MP25 of the 27th PMOS tube MP27 Even, so that bigger electric current is flowed through in the gate source voltage increase of the 27th PMOS tube MP27, so that flowing through the 32nd The electric current of NMOS tube MN32 reduces, and the current potential of VP2 point reduces, and the presence of negative-feedback makes translinear loop for two-stage calculation amplification The bias voltage that device output stage provides is more stable.

Fig. 6 is a kind of great current operation amplifier based on CDMOS technique with current-limiting protection function of the utility model DC current gain and phase margin simulation curve, the DC current gain of the utility model circuit is 102.6dB, phase margin 73 , gain margin 18.87dB, the i.e. circuit have very strong amplifying power and stability.

Fig. 7 is that the maximum undistorted exchange of the utility model two-stage calculation amplifier circuit exports situation, can from simulation result To find out, the utility model can export the alternating current of 380mA.

Fig. 8 is current limliting size simulation curve when the utility model two-stage calculation amplifier circuit output is shorted to VDD, from As a result it can be seen that the maximum value of operational amplifier short circuit output realizes current-limiting function in 822mA or so well in, and Substantially meet industrial needs.

Fig. 9 is current limliting size simulation curve when the utility model two-stage calculation amplifier circuit output is shorted to GND, from As a result it can be seen that the maximum value of operational amplifier short circuit output realizes current-limiting function in 853mA or so well in, and Industrial needs are substantially met, can be used for driving voice coil inductance, the buffer of High-current output.

Claims

1. a kind of power operational amplifier based on CDMOS technique with current-limiting protection function, it is characterised in that: including the first order Operation amplifier unit, second level operation amplifier unit, current-limiting protection unit, biasing circuit；

The biasing circuit is connect with first order operation amplifier unit, second level operation amplifier unit, is used for first order operation Amplifying unit and second level operation amplifier unit provide corresponding bias voltage；

The output end of the first order operation amplifier unit is connect with the input terminal of second level operation amplifier unit, for providing height DC current gain；

The input terminal of the second level operation amplifier unit is connect with the output end of first order operation amplifier unit, for increasing by the The maximum amplitude of oscillation of level-one operation amplifier element output signal；

The current-limiting protection unit is connect with the output end of second level operational amplifier unit, when output electric current overrate Afterwards, current-limiting protection circuit by the second level operation amplifier unit output one fixed value is limited to the grid voltage of pipe, without by The influence of the variation of input does not flow it through super-high-current to pipe with protection output and damages.

2. the power operational amplifier based on CDMOS technique with current-limiting protection function according to claim 1, feature Be: the first order operation amplifier unit includes the Foldable cascade amplifying circuit that NMOS inputs pipe, collapsible total Source is total to grid amplifying circuit using active load technology, improves the DC current gain of first order amplifier unit, Foldable cascade is put Big circuit includes the first to the 8th NMOS tube, first to fourth PMOS tube, wherein the grid of the first NMOS tube, the second NMOS tube Grid connects input signal VIN+, VIN-respectively, and the source electrode of the source electrode of the first NMOS tube and the second NMOS tube connects and is connected to third The drain electrode of the drain electrode of NMOS tube, the source electrode of third NMOS tube and the 4th NMOS tube is connected, the source electrode ground connection of the 4th NMOS tube, the The grid of three NMOS tubes, the 4th NMOS tube grid be connected and access biasing circuit offer voltage bias VB；The grid of first PMOS tube Pole is connected with the grid of the second PMOS tube and accesses the voltage bias VB 1 of biasing circuit offer, the source electrode of the first PMOS tube and second The source electrode of PMOS tube connects power supply, the drain electrode phase of the drain electrode of the first PMOS tube and the source electrode of third PMOS tube and the second NMOS tube Even, the drain electrode of the second PMOS tube is connected with the drain electrode of the source electrode of the 4th NMOS tube and the first NMOS tube, the grid of third PMOS tube Pole is connected with the grid of the 4th PMOS tube and accesses the voltage bias VB 2 of biasing circuit offer, the drain electrode of third PMOS tube and the 5th The grid of NMOS tube is connected with drain electrode, the grid of the 6th NMOS tube, the grid of the 7th NMOS tube, the grid of the 8th NMOS tube, The drain electrode of the source electrode and the 7th NMOS tube of 5th NMOS tube is connected, the source electrode ground connection of the 7th NMOS tube, the source of the 6th NMOS tube Pole is connected with the drain electrode of the 8th NMOS tube, the source electrode ground connection of the 8th NMOS tube.

3. the power operational amplifier based on CDMOS technique with current-limiting protection function according to claim 2, feature Be: the second level operation amplifier unit includes being made of the 9th NMOS tube, the 5th PMOS tube, is mentioned for output to tube grid For stablizing the transconductance linearity loop circuit of bias；The Class-AB output-stage circuit being made of the 7th PMOS tube, the 11st NMOS tube； It is made of first resistor, second resistance, first capacitor, the second capacitor, the compensation circuit for miller compensation；By load resistance The output loading constituted with load capacitance；The drain electrode of 4th PMOS tube and the grid of the 7th PMOS tube, the 5th PMOS tube The drain electrode of source electrode, the 9th NMOS tube is connected, and the source electrode of the 7th PMOS tube accesses power supply, the drain electrode and the 9th of the 5th PMOS tube It is connected after the source electrode of NMOS tube is connected and with the grid of the drain electrode of the 6th NMOS tube, the 11st NMOS tube, the 5th PMOS tube Grid accesses the bias VP1 that biasing circuit provides, the bias VP2 that the grid access biasing circuit of the 9th NMOS tube provides, the tenth The source electrode of one NMOS tube is grounded, and the drain electrode of the 11st NMOS tube is connected with the drain electrode of the 7th PMOS tube constitutes output end OUT；Miller One end of first resistor is connected with the grid of the 7th PMOS tube in compensation circuit, the other end of first resistor and first capacitor One end is connected, and the other end of first capacitor connects output end OUT, the grid phase of one end of second resistance and the 11st NMOS tube Even, the other end of second resistance is connect with one end of the second capacitor, and the other end of the second capacitor connects output end OUT；Load electricity One termination output end OUT of resistance, the other end ground connection of load resistance, a termination output end OUT of output load capacitance, output are negative Carry the other end ground connection of capacitor.

4. the power operational amplifier based on CDMOS technique with current-limiting protection function according to claim 3, feature Be: the current-limiting protection circuit includes the 6th PMOS tube, the 8th to the 13rd PMOS tube, the tenth NMOS tube, the 12nd to the 18 NMOS tubes, third to the 6th resistance；One termination power of the 3rd resistor, the other end of 3rd resistor connect the 9th respectively The source electrode of the source electrode of PMOS tube, the 8th PMOS tube, a termination power of the 4th resistance, the tenth PMOS of another termination of the 4th resistance The source electrode of pipe, the grid of the 8th PMOS tube connect the grid of the 7th PMOS tube, and the drain electrode of the 8th PMOS tube meets output end OUT, and the 9th The grid of PMOS tube is connected with the source electrode of the grid of the tenth PMOS tube, the tenth PMOS tube, the drain electrode and the tenth of the 9th PMOS tube The drain electrode of three NMOS tubes, the 6th PMOS tube grid be connected, the grid of the tenth PMOS tube and drain electrode and the 14th NMOS tube Drain electrode is connected, and the source electrode of the 6th PMOS tube connects power supply, and the drain electrode of the 6th PMOS tube connects the grid of the 7th PMOS tube, and the 13rd The grid of NMOS tube, the grid of the 14th NMOS tube, the grid of the 15th NMOS tube and the grid phase of drain electrode, the 16th NMOS tube Connection, the source electrode of the 13rd NMOS tube, the source electrode of the 14th NMOS tube, the source electrode of the 15th NMOS tube, the 16th NMOS tube Source electrode ground connection, the drain electrode of the 16th NMOS tube connect the drain electrode of the 11st PMOS tube, grid, the 12nd PMOS of the 11st PMOS tube The grid of the grid of pipe, the 13rd PMOS tube, source electrode, the 13rd PMOS of the source electrode of the 11st PMOS tube, the 12nd PMOS tube The source electrode of pipe connects power supply, and the drain electrode of the 12nd PMOS tube is connect with the grid of the drain electrode of the 17th NMOS tube, the tenth NMOS tube, The drain electrode of tenth NMOS tube is connected with the grid of the 11st NMOS tube, the source electrode ground connection of the tenth NMOS tube, the 17th NMOS tube Grid and the drain electrode of the 13rd PMOS tube, the grid of the 18th NMOS tube, the 18th NMOS tube drain electrode be connected, the 17th The source electrode of NMOS tube connects the source electrode of one end of the 5th resistance, the 12nd NMOS tube, and the other end of the 5th resistance is grounded, and the 18th The source electrode of NMOS tube connects one end of the 6th resistance, the other end ground connection of the 6th resistance, the grid and the 11st of the 12nd NMOS tube The grid of NMOS tube is connected, and the drain electrode of the 12nd NMOS tube meets output end OUT.

5. the power operational amplifier based on CDMOS technique with current-limiting protection function according to claim 4, feature Be: the biasing circuit provides bias voltage VB, VB1, VB2 for first order operation amplifier unit, is second level operation amplifier Unit provides bias voltage VP1, VP2, and biasing circuit includes the 14th to the 27th PMOS tube, the 19th to the 33rd NMOS tube；Wherein the source electrode of the 14th PMOS tube connects power supply, and the drain electrode of the 14th PMOS tube connects the source electrode of the 15th PMOS tube, the The grid of 15 PMOS tube and drain electrode are connected and link together with the grid of the 14th PMOS tube puts for Foldable cascade The drain electrode that big circuit provides the 2, the 15th PMOS tube of voltage bias VB is connected with the drain electrode of the 19th NMOS tube；The source of 19th NMOS tube Pole is connected with the drain electrode of the 21st NMOS tube, and the source electrode of the 21st NMOS tube, the source electrode of the 22nd NMOS tube are grounded, The drain electrode of 22nd NMOS tube is connected with the source electrode of the 20th NMOS tube, grid, the 20th NMOS of the 19th NMOS tube The drain electrode of grid, the 20th NMOS tube of the grid of pipe, the grid of the 21st NMOS tube, the 22nd NMOS tube is connected to one It rises and provides voltage bias VB for Foldable cascade amplifying unit；The drain electrode and the drain electrode phase of the 17th PMOS tube of 20th NMOS tube Connection, the grid exterior control voltage VOH/VOL of the 17th PMOS tube, the source electrode of the 17th PMOS tube connect the 16th PMOS tube Drain electrode, the external a reference source bias voltage VREF of the grid of the 16th PMOS tube, the source electrode of the 16th PMOS tube connect power supply；Tenth The source electrode of eight PMOS tube connects power supply, the drain electrode of the 18th PMOS tube, the leakage of the grid, the 24th NMOS tube of the 18th PMOS tube Pole links together and provides voltage bias VB 1 for first order operation amplifier unit；The source electrode of 24th NMOS tube connects the 26th The drain electrode of NMOS tube, the source electrode ground connection of the 26th NMOS tube, the grid of the grid of the 24th NMOS tube, the 25th NMOS tube Pole, the grid of the 26th NMOS tube, the 27th NMOS tube grid be connected to VB, the source electrode of the 27th NMOS tube connects Ground, the drain electrode of the 27th NMOS tube connect the source electrode of the 25th NMOS tube, and the drain electrode of the 25th NMOS tube connects the 28th The grid of the source electrode of NMOS tube, the 23rd NMOS tube, the drain electrode of the 28th NMOS tube connect the 19th PMOS tube grid and Drain electrode, the source electrode of the 19th PMOS tube connect power supply, the grid and the grid leak pole phase of the 29th NMOS tube of the 28th NMOS tube Connection generates bias VP2 and provides bias for transconductance linearity loop circuit in the operation amplifier unit of the second level；29th NMOS tube Source electrode connects grid and the drain electrode of the 30th NMOS tube, the source electrode ground connection of the 30th NMOS tube, the grid of the 29th NMOS tube, the The drain electrode of 29 NMOS tubes, the drain electrode of the 21st PMOS tube are connected, the source electrode and the 20th of the 21st PMOS tube The drain electrode of PMOS tube and the drain electrode of the 23rd NMOS tube are connected, the source electrode ground connection of the 23rd NMOS tube, and the 20th The source electrode of PMOS tube connects power supply, and the grid of the 20th PMOS tube is connected to VB1 together with the grid of the 22nd PMOS tube, and second The grid of 11 PMOS tube and the grid of the 23rd PMOS tube are connected to VB2 together；The source electrode of 22nd PMOS tube connects electricity Source, the drain electrode of the 22nd PMOS tube connect the source electrode of the 23rd PMOS tube, and the drain electrode of the 23rd PMOS tube connects the 25th The grid of the source electrode of PMOS tube, the 27th PMOS tube, the source electrode of the 27th PMOS tube connect power supply, the 25th PMOS tube It is in second level operation amplifier unit that grid, the grid of the 26th PMOS tube and drain electrode, which link together and generate bias VP1, Transconductance linearity loop circuit provides bias, and the source electrode of the 26th PMOS tube connects grid and the drain electrode of the 24th PMOS tube, and second The source electrode of 14 PMOS tube connects power supply, and the grid leak of the 26th PMOS tube is extremely connected and is connected in the drain electrode of the 32nd NMOS tube Together, the source electrode of the 32nd NMOS tube connects the drain electrode of the drain electrode of the 27th PMOS tube, the 33rd NMOS tube, and the 33rd The source electrode of NMOS tube is grounded, the 32nd NMOS tube, the 33rd NMOS tube grid link together and be connected to VB；Described The grid of 31 NMOS tubes, the drain electrode of the 31st NMOS tube, the drain electrode of the 25th PMOS tube link together, and the 30th The source electrode of one NMOS tube is grounded.

6. the power operational amplifier based on CDMOS technique with current-limiting protection function according to claim 2, feature It is: in the first order operation amplifier unit, the transistor channel breadth length ratio of the first to the 8th NMOS tube is respectively 250/1, 250/1,60/1,30/1,50/1,50/1,25/1,25/1, the transistor channel breadth length ratio of first to fourth PMOS tube is respectively 50/1、50/1、150/1、150/1。

7. the power operational amplifier based on CDMOS technique with current-limiting protection function according to claim 3, feature Be: in the second level operation amplifier unit, the 5th PMOS tube, the transistor channel breadth length ratio of the 7th PMOS tube are respectively 250/1,17000/1, the 9th NMOS tube, the transistor channel breadth length ratio of the 11st NMOS tube are respectively 75/1,5040/1, and first Resistance, second resistance resistance value be 14.3KW, first capacitor, the capacitance of the second capacitor are 4.3pF, the resistance value of load resistance For 100W, the capacitance of load capacitance is 10pF.

8. the power operational amplifier based on CDMOS technique with current-limiting protection function according to claim 4, feature Be: in the current-limiting protection circuit, the 6th PMOS tube, the transistor channel breadth length ratio of the 8th to the 13rd PMOS tube are respectively 15/1,200/1,50/1,50/1,150/1,150/1,250/1, the crystal of the tenth NMOS tube, the 12nd to the 18th NMOS tube Pipe trench road width is long than being respectively 7.5/1,120/1,250/1,250/1,60/1,30/1,50/1,50/1, third to the 6th resistance Resistance value be respectively 57.6W, 45.8KW, 19W, 38.2 KW.

9. the power operational amplifier based on CDMOS technique with current-limiting protection function according to claim 5, feature Be: in the biasing circuit, the transistor channel breadth length ratio of the 14th to the 27th PMOS tube is respectively 10/1,60/1, 41.7/1, the 50/1,20/1,40/1,20/1,60/1,10/1,30/1,400/1,250/1,250/1,400/1, the 19th to The transistor channel breadth length ratio of 33 NMOS tubes is respectively 20/1,10/1,10/1,5/1,120/1,20/1,10/1,10/1, 5/1、75/1、75/1、120/1、20/1、20/1、10/1。