CN208806918U - A kind of video optical multiplexer based on FPGA - Google Patents
A kind of video optical multiplexer based on FPGA Download PDFInfo
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- CN208806918U CN208806918U CN201821867226.1U CN201821867226U CN208806918U CN 208806918 U CN208806918 U CN 208806918U CN 201821867226 U CN201821867226 U CN 201821867226U CN 208806918 U CN208806918 U CN 208806918U
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Abstract
The utility model discloses a kind of video optical multiplexers based on FPGA; circuit board including shell and setting inside the shell, circuit board include optical module, transceiving chip, control circuit, Ethernet switching chip, Ethernet interface, protection circuit, network transformer integrated chip；Optical module is connect with external fiber plug, is also connect with transceiving chip, and transceiving chip and Ethernet switching chip are connected to control circuit；Ethernet interface is connect with external ethernet plug, and Ethernet interface and protection circuit connection are also connect with network transformer integrated chip, network transformer integrated chip is connect with Ethernet switching chip；Optical module includes that a fiber connector and signal processing circuit, fiber connector are connect with external fiber plug, and fiber connector has positive data spasm foot, the cathode data spasm foot of the signal for receiving the transmission of external fiber plug.The utility model can reinforce receiving and transmitting signal stability on video optical multiplexer.
Description
Technical field
The utility model relates to optical transmitter and receiver technical field, specially a kind of video optical multiplexer based on FPGA.
Background technique
Video light end be used to be converted by external analog video signal data after optical signal by subsequent optical fiber into
There have been exceptions during going and transmit at a distance, but receive and dispatch if on video optical multiplexer to signal, i.e.,
Make on subsequent optical fiber to signal transmission guarantee dynamics it is big also of no avail again, guarantee video optical multiplexer on receiving and transmitting signal it is steady
It is qualitative to be just particularly important.
Utility model content
In view of the deficienciess of the prior art, the purpose of this utility model is to provide a kind of video light end based on FPGA
Machine can reinforce receiving and transmitting signal stability on video optical multiplexer.
To achieve the above object, the utility model provides following technical solution: a kind of video optical multiplexer based on FPGA,
Circuit board including shell and setting inside the shell, the circuit board includes optical module, transceiving chip, control circuit, Ethernet
Exchange chip, Ethernet interface, protection circuit, network transformer integrated chip；The optical module is connect with external fiber plug,
It is also connect with transceiving chip, the transceiving chip and Ethernet switching chip are connected to control circuit；The Ethernet interface
It being connect with external ethernet plug, the Ethernet interface and protection circuit connection are also connect with network transformer integrated chip,
The network transformer integrated chip is connect with Ethernet switching chip；The optical module includes a fiber connector and signal
Processing circuit, the fiber connector are connect with external fiber plug, and the fiber connector has for receiving external fiber
Positive data spasm foot, the cathode data spasm foot of the signal of plug transmission, the cathode data spasm foot are connected with resistance
It being connected to the control circuit after 1R11, the node that the resistance 1R11 is connected to the control circuit is grounded after being also connected with resistance 1R22,
It is also connected with resistance 1R17 and is followed by power supply；The anode data spasm foot connects to the control circuit after being connected with resistance 1R10, institute
It states after the node that resistance 1R10 is connected to the control circuit is also connected with resistance 1R23 and is grounded, be also connected with resistance 1R18 and be followed by electricity
Source, the resistance 1R10 and resistance 1R11 resistance value are 0 Europe；The anode data spasm foot connects after being also connected with capacitor 1C3
To transceiving chip, the anode data pin is grounded after being connected with resistance 1R20, and the cathode data spasm foot is also connected with electricity
It is connected to transceiving chip after holding 1C4, the cathode data pin is grounded after being also connected with resistance 1R19.
The fiber connector also has for sending a signal to external fiber as a further improvement of the utility model,
Carry out the coffin upon burial foot, cathode data of the positive data of plug are carried out the coffin upon burial foot；The anode data, which are carried out the coffin upon burial after foot is connected with capacitor 1C2, is connected to receipts
Send out chip, anode data foot of carrying out the coffin upon burial is also connected with resistance 1R7 and is followed by power supply, is grounded after being also connected with resistance 1R16, described
Cathode data foot of carrying out the coffin upon burial is connected with after capacitor 1C1 and is connected to transceiving chip, and cathode data foot of carrying out the coffin upon burial is also connected with resistance 1R6
It is followed by power supply, is grounded after being also connected with resistance 1R15.
The positive data, which are carried out the coffin upon burial after foot is also connected with resistance 1R8, as a further improvement of the utility model, is connected with
Connected to the control circuit after resistance 1R3, the anode data carry out the coffin upon burial foot be also connected with after resistance 1R9 be connected with resistance 1R2 after with
Control circuit connection；The resistance 1R3 be also connected with resistance 1R5 with the resistance 1R8 node connecting after with resistance 1R2 and resistance
The node of 1R9 connection is connected, and resistance 1R4, the resistance value of the resistance 1R8 and resistance 1R9 are also connected between two nodes
For 0 Europe.
Wherein four data transmission pins of the Ethernet interface connect respectively as a further improvement of the utility model,
It is connect after being connected to resistance 6R20, resistance 6R21, resistance 6R22, resistance 6R23 with network transformer, which transmits pin
It is also connected with first gas discharge tube, second gas discharge tube, the grounding pin ground connection of the first gas discharge tube, in addition two
Pin connect with two of them data transmission pin respectively, and the grounding pin of the second gas discharge tube is grounded, and in addition two
Pin is connect with remaining two data transmission pin respectively；The protection circuit uses SLVU2 chip, the SLVU2 core
Piece is all connected with four data transmission pins.
It as a further improvement of the utility model, further include power-up time delay circuit, the power-up time delay circuit includes field
Effect tube chip, triode Q1, triode Q2；There are four drain leads, three source leads, one for the field effect tube chip tool
A gate lead, four drain leads connect to the control circuit after being mutually shorted, to export the power supply after delay to control
Circuit, the drain electrode are grounded after being also connected with capacitor 1EC2, are grounded after being also connected with capacitor 20C1；Three source leads are mutual
It is shorted and is connect after being connected with resistance R114 with gate lead, the gate lead is connected to three poles after being also connected with resistance R115
The collector of pipe Q1；The emitter of the triode Q1 is grounded, and base stage is connected with capacitor EC8 after being connected with switching diode ZD1
After be grounded, the switching diode ZD1 anode connect with the base stage of triode Q1, cathode is connect with capacitor EC8；The switch
The cathode of diode ZD1 is connect after being also connected with resistance R117 with the emitter of triode Q2；The collector of the triode Q2
Ground connection, the base stage of the triode Q2 is grounded after being connected with resistance R118, is also connected with after resistance R116 and switching diode ZD1
Cathode connection；The base stage of the triode Q2 is additionally coupled to the source lead of field effect tube chip, the field effect tube chip
Source lead connect with external power supply power supply.
The source lead of the field effect tube chip is also connected with capacitor 1EC1 as a further improvement of the utility model,
After be grounded, which is grounded after being also connected with Transient Suppression Diode, the plus earth of the Transient Suppression Diode, bear
Pole is connect with source lead.
It as a further improvement of the utility model, further include the reset circuit being electrically connected with control circuit；The control
Circuit and reset circuit connect to power supply；The reset circuit includes the first reset chip, and first reset chip has
First reset pin, the first grounding pin, the first power pins, the first resetting pin；First weight of first reset chip
Set pin, the first reset pin connects to the control circuit, the first grounding pin ground connection of first reset chip, the first electricity
Source pin connects power supply；It is provided with count threshold in first reset chip, when control circuit sends reset signal to the first weight
When setting pin, the first reset chip reset count numerical value, when the first reset chip count value is more than count threshold, first is multiple
Position chip, which is sent, to be resetted fortunately to control circuit, and control circuit re-powers.
The first reset pin of first reset chip is connected with resistance as a further improvement of the utility model,
It is connected to the control circuit after R112, first reset pin is also connected with the second reset chip, the second reset chip tool
There are the second reset pin, second source pin, the second grounding pin；The second grounding pin ground connection, second source pin connect
Power supply；Second reset pin is connected to the first reset pin.
The resistance R112 is connected with respect to the other end of the first reset pin as a further improvement of the utility model,
Needle is arranged, for row's needle set there are two stitch, one of stitch the first width opposite with resistance R112 is that the other end of pin connects,
Another stitch is connected to power supply, when two stitch for arranging needle are shorted by external jumper cap, the one of the opposite row's needle of resistance R112
End is pulled up by power supply.
Assembling assembly is provided on the shell as a further improvement of the utility model, the assembling assembly includes
It is fixedly connected with grafting pedestal and clamping latch fitting on the shell；The clamping latch fitting is fixedly connected with grafting pedestal, and is clamped
Latch fitting has elasticity；Inserting groove is offered on the grafting pedestal, the inserting groove is adapted with the flanging of outside DIN clamp rail,
The flanging of DIN clamp rail can be plugged into inserting groove；One end of the clamping latch fitting is fixedly connected on grafting pedestal, and the other end is stuck up
It rises and is stirred for manpower, the clamping latch fitting and differential pedestal junction offer clamping groove, the folding of the clamping groove and DIN clamp rail
While being adapted, the flanging of DIN clamp rail be can be plugged into clamping groove；The clamping latch fitting is provided with guiding surface, when DIN clamp rail
Flanging and guiding surface are inconsistent and when continuing to squeeze guiding surface, and clamping latch fitting is extruded deformation, the flanging insertion of DIN clamp rail
Clamping latch fitting restores after into clamping groove；Limit buckle is additionally provided on the grafting pedestal, the limit buckle is located at inserting groove slot
Mouthful, when the flanging of DIN clamp rail is inserted into inserting groove, limit buckle clasps the flanging of DIN clamp rail.
The beneficial effects of the utility model are sent to control after the signal received is carried out serioparallel exchange by transceiving chip
Circuit processed, while the signal received is also carried out serioparallel exchange by control circuit, control circuit compares its own and goes here and there and turn at this time
Signal and transceiving chip after changing are sent to the signal of control circuit, if deviation occurs in its comparison, mean control circuit
Or one of serioparallel exchange goes wrong between transceiving chip, notifies remote port to retransmit signal at this time, until control
Circuit is consistent with the result of transceiving chip serioparallel exchange, if different always, means circuit operation irregularity, service personnel can
To overhaul in time, carried out for serioparallel exchange using single transceiving chip compared to the prior art, this programme can be to avoid transmitting-receiving
The error of chip serioparallel exchange, there is deviation in the signal for causing control circuit to receive, while can also detect in circuit in time
Whether transceiving chip or control circuit are problematic, can overhaul in time, and deviation of signal bring is avoided to influence.
Detailed description of the invention
Fig. 1 is the optical module signal transfering circuit schematic diagram of the utility model；
Fig. 2 is the Ethernet interface signal transfering circuit schematic diagram of the utility model；
Fig. 3 is the power on delay circuit diagram of the utility model；
Fig. 4 is the reset circuit schematic diagram of the utility model；
Fig. 5 is the shell mechanism schematic diagram of the utility model；
Fig. 6 is the assembling assembly structural schematic diagram of the utility model.
Drawing reference numeral: 1, shell；11, optical module；12, transceiving chip；13, control circuit；14, Ethernet switching chip；
15, Ethernet interface；16, circuit is protected；17, network transformer integrated chip；181, first gas discharge tube；182, the second gas
Body discharge tube；2, circuit board；23, power-up time delay circuit；231, field effect tube chip；232, Transient Suppression Diode；3, it assembles
Component；31, grafting pedestal；311, inserting groove；32, it is clamped latch fitting；321, guiding surface；322, clamping groove；4, limit buckle；7, multiple
Position circuit；71, the first reset chip；72, the second reset chip；73, needle is arranged.
Specific embodiment
The utility model is described in further detail below in conjunction with embodiment given by attached drawing.
Referring to Fig.1 shown in -6, a kind of video optical multiplexer based on FPGA of the present embodiment, including shell 1 and setting are outside
Circuit board 2 in shell 1, which is characterized in that the circuit board 2 includes optical module 11, transceiving chip 12, control circuit 13, ether
Net exchange chip 14, Ethernet interface 15, protection circuit 16, network transformer integrated chip 17；The optical module 11 and outside
Optical fiber plug connection, also connect with transceiving chip 12, the transceiving chip 12 and Ethernet switching chip 14 are connected to control
Circuit 13；The Ethernet interface 15 is connect with external ethernet plug, and the Ethernet interface 15 is connect with protection circuit 16,
It is also connect with network transformer integrated chip 17, the network transformer integrated chip 17 is connect with Ethernet switching chip 14；
The optical module 11 includes a fiber connector and signal processing circuit, and the fiber connector and external fiber plug connect
It connects, the fiber connector has the positive data spasm foot of the signal for receiving the transmission of external fiber plug, cathode data
Spasm foot, the cathode data spasm foot are connect after being connected with resistance 1R11 with control circuit 13, the resistance 1R11 and control
The node that circuit 13 connects is grounded after being also connected with resistance 1R22, is also connected with resistance 1R17 and is followed by power supply；The anode data
Spasm foot is connect after being connected with resistance 1R10 with control circuit 13, and the node that the resistance 1R10 is connect with control circuit 13 also connects
It is grounded after being connected to resistance 1R23, is also connected with resistance 1R18 and is followed by power supply, the resistance 1R10 and resistance 1R11 resistance value are 0
Europe；The anode data spasm foot is connected to transceiving chip 12 after being also connected with capacitor 1C3, and the anode data pin is connected with
It is grounded after resistance 1R20, the cathode data spasm foot is connected to transceiving chip 12, the cathode number after being also connected with capacitor 1C4
It is grounded after being also connected with resistance 1R19 according to pin.
Through the above technical solutions, control circuit 13 passes through video reception electricity common in existing video optical multiplexer
The video terminals such as road and external camera are attached, and are received the vision signal that external video terminal sends over, are then passed through
Signal is carried out conversion and is sent to transceiving chip 12 (TLK2521) by control circuit 13, and then transceiving chip 12 by signal and is being gone here and there
Optical module 11 is converted and be sent to, external fiber is transmitted a signal to by optical module 11, at this time the signal processing of optical module 11
Circuit is filtered 11 received signal of optical module, pressure stabilizing and electro-optic conversion, then passes through fiber connector and external fiber
Connection, while control circuit 13 is also connect with the fiber connector of optical module 11, is gone here and there and is turned to be integrated in the control circuit 13
It changes and is core with the FPGA of parallel-serial conversion and circuit of its peripheral circuit composition with control function is set；Control circuit 13 is right
The signal received is sent to fiber connector after carrying out parallel-serial conversion, at this time the signal processing by connecting with fiber connector
Circuit carries out electro-optic conversion, then the signal after electro-optic conversion is transferred on external fiber by fiber connector；When optical fiber connects
Connector is the optical signal received can be carried out photoelectric conversion when receiving signal by signal processing circuit, then pass through light
Positive data spasm foot and cathode data spasm foot on fine connector send the data to control circuit 13 and transceiving chip 12,
It is sent to control circuit 13 after the signal received is carried out serioparallel exchange by transceiving chip 12, while control circuit 13 also will
The signal received carries out serioparallel exchange, and control circuit 13 compares the signal and transceiving chip 12 after its own serioparallel exchange at this time
Be sent to the signal of control circuit 13, if there is deviation in its comparison, mean control circuit 13 or transceiving chip 12 it
Between one of serioparallel exchange go wrong, at this time notify remote port retransmit signal, until control circuit 13 and transmitting-receiving core
The result of 12 serioparallel exchange of piece is consistent, if different always, means circuit operation irregularity, service personnel can examine in time
It repairs, is carried out for serioparallel exchange using single transceiving chip 12 compared to the prior art, this programme can be to avoid transceiving chip 12
Serioparallel exchange error, there is deviation in the signal for causing control circuit 13 to receive, while can also detect in circuit and receive in time
It sends out chip 12 or whether control circuit 13 is problematic, can overhaul in time, deviation of signal bring is avoided to influence.
After control circuit 13 receives the vision signal of external video terminal, pass through Ethernet switching chip 14
(RTL8305SC) signal is subjected to protocol conversion, and signal is stablized and amplified by network transformer integrated chip 17,
Then host computer is transmitted a signal to by Ethernet interface 15；The protection circuit 16 of setting is also integrated to network transformer simultaneously
Communication between chip 17 and Ethernet interface 15 is protected, and is avoided Ethernet interface 15 by instantaneous pressure, is led to network
The a series of subsequent conditioning circuit damage such as transformer integrated chip 17 and Ethernet switching chip 14.
Resistance 1R17, the resistance 1R18 of setting are used as pull-up resistor, when fiber connector is transferred to the letter of control circuit 13
When number being high level, since one end of pull-up resistor connects to power supply, it is high electricity that pull-up resistor, which can draw high the signal, at this time
Flat, the electrical signal levels for avoiding fiber connector from transmitting are unstable；The resistance 1R22 of setting, one end of resistance 1R23 are grounded, energy
It is enough to be grounded after reducing the electric current of signal, and then the level of signal is dragged down when fiber connector transmission telecommunications number is low level,
The electrical signal levels for further avoiding fiber connector transmission are unstable；Control circuit 13 can be allowed to receive through the above scheme
The signal arrived is more stable；The resistance of the resistance 1R10 and resistance 1R11 of setting are 0 Europe, may be used as fuse and then protect
Control circuit 13.
Resistance 1R19, the resistance 1R20 of setting are identical as resistance 1R22, resistance 1R23 effect, and transceiving chip 12 can be improved
The stability of the signal received, the capacitor 1C3 and capacitor 1C4 of setting are used as coupled capacitor, the stability of signal can be improved.
As an improved specific embodiment, the fiber connector also has to be inserted for sending a signal to external fiber
Carry out the coffin upon burial foot, cathode data of the positive data of head are carried out the coffin upon burial foot；The anode data, which are carried out the coffin upon burial after foot is connected with capacitor 1C2, is connected to transmitting-receiving
Chip 12, anode data foot of carrying out the coffin upon burial is also connected with resistance 1R7 and is followed by power supply, is grounded after being also connected with resistance 1R16, described
Cathode data foot of carrying out the coffin upon burial is connected with after capacitor 1C1 and is connected to transceiving chip 12, and cathode data foot of carrying out the coffin upon burial is also connected with resistance
1R6 is followed by power supply, is grounded after being also connected with resistance 1R15.
Through the above technical solutions, resistance 1R15, the resistance 1R16 of setting are identical as resistance 1R22, resistance 1R23 function；
Resistance 1R6, resistance 1R7 are identical as resistance 1R17, resistance 1R18 function, and the signal that transceiving chip 12 is sent can be improved
Stability；The capacitor 1C1 and capacitor 1C2 of setting can be further improved the signal of the transmission of transceiving chip 12 as coupled capacitor
Stability.
As an improved specific embodiment, the anode data, which are carried out the coffin upon burial after foot is also connected with resistance 1R8, is connected with electricity
Connect after resistance 1R3 with control circuit 13, the anode data carry out the coffin upon burial foot be also connected with after resistance 1R9 be connected with after resistance 1R2 and
Control circuit 13 connects；The resistance 1R3 be also connected with resistance 1R5 with the resistance 1R8 node connecting after with resistance 1R2 and resistance
The node of 1R9 connection is connected, and resistance 1R4, the resistance value of the resistance 1R8 and resistance 1R9 are also connected between two nodes
For 0 Europe.
Through the above technical solutions, when control circuit 13 sends the circuit of parallel-serial conversion to fiber connector, setting
Resistance 1R2 and resistance 1R3 can carry out current limliting to signal；The resistance 1R8 and resistance 1R9 of setting can be as fuses in turn
Protect control circuit 13.
As an improved specific embodiment, wherein four data transmission pins of the Ethernet interface 15 connect respectively
It is connect after being connected to resistance 6R20, resistance 6R21, resistance 6R22, resistance 6R23 with network transformer integrated chip 17, four numbers
It is also connected with first gas discharge tube 181, second gas discharge tube 182 according to transmission pin, the first gas discharge tube 181
Grounding pin ground connection, in addition two pins are connect with two of them data transmission pin respectively, the second gas discharge tube 182
Grounding pin ground connection, in addition two pins respectively with remaining two data transmission pin connect；The protection circuit 16 is adopted
With SLVU2 chip, the SLVU2 chip is all connected with four data transmission pins.
Through the above technical solutions, the resistance 6R20 of setting, resistance 6R21, resistance 6R22, resistance 6R23 can be to data
The electric signal transmitted on pin carries out current limliting, reduces the size of current entered in network transformer integrated chip 17, effectively increases
It is powered on the safety on road, network transformer integrated chip 17 is protected；The first gas discharge tube 181 and the second gas of setting
Body discharge tube 182 can choose B3D090 model, can make a response rapidly to zooming transient voltage, can increase ether
The lightning protection and Anti-surging performance of web frame, for setting varistor, varistor performance can decay at any time, and gas
Discharge tube will not, and the discharge capacity of gas-discharge tube is big, and the voltage range that can be born is big.SLVU2 chip is as a kind of
Electrostatic discharge protection chip has eight pins, corresponding two-by-two to can connect four data transmission pins, without extra pin
Waste.
It further include power-up time delay circuit 23 as an improved specific embodiment, the power-up time delay circuit 23 includes
Field effect tube chip 231, triode Q1, triode Q2；There are four drain leads, three sources for the tool of field effect tube chip 231
Pole pin, a gate lead, four drain leads are connect after being mutually shorted with control circuit 13, after output delay
Power supply is grounded after being also connected with capacitor 1EC2 to control circuit 13, the drain electrode, is grounded after being also connected with capacitor 20C1；Described in three
Source lead is mutually shorted and connect after being connected with resistance R114 with gate lead, and the gate lead is also connected with resistance R115
It is connected to the collector of triode Q1 afterwards；The emitter of the triode Q1 is grounded, after base stage is connected with switching diode ZD1
It is grounded after being connected with capacitor EC8, the anode of the switching diode ZD1 is connect with the base stage of triode Q1, cathode and capacitor EC8
Connection；The cathode of the switching diode ZD1 is connect after being also connected with resistance R117 with the emitter of triode Q2；Three pole
The grounded collector of pipe Q2, the base stage of the triode Q2 are grounded after being connected with resistance R118, be also connected with after resistance R116 with
The cathode of switching diode ZD1 connects；The base stage of the triode Q2 is additionally coupled to the source lead of field effect tube chip 231,
The source lead of the field effect tube chip 231 is connect with external power supply power supply.
Through the above technical solutions, wherein field effect tube chip 231 can be used using IRF7410 model, triode Q1
9013, triode Q2 uses 9012, and the specification that wherein switching diode ZD1 is selected is 3V, when switching diode ZD1 is reversely received
It can be connected when the voltage of 3V；Wherein four drain electrodes of field effect tube chip 231 are shorted, and are equivalent to each drain electrode and electricity at this time
Source connection can also allow it to weld more stable, even if there is void when welding on the circuit board 2 field effect tube chip 231
The part pin of weldering also has other pins that can weld fitting on the circuit board 2, the part burden of service personnel is reduced, wherein three
It is a that source electrode are shorted can also serve the same role.When external power supply powers on, external power supply enters capacitor by capacitor R116
EC8 charges to capacitor EC8, when the voltage on capacitor EC8 be charged to 3V and more than when, switching diode ZD1 conducting, at this time
Voltage of the base stage of triode Q1 by 2.3V or more, triode Q1 conducting, so that the gate lead of field effect tube chip 231
Voltage is pulled low, and is a kind of P-channel metal-oxide-semiconductor, when gate lead voltage since the field effect tube chip 231 of selection is IRF7410
Source lead and drain lead conducting when for low level, at this time due to being connected with resistance between source lead and gate lead
R114, the voltage of source lead maintains the voltage value of external power supply input at this time, without as the voltage of gate lead
It is pulled low；At this time since external power supply can be postponed by entering control circuit after field effect tube chip 231 to capacitor EC8 charging
13 time can have certain time-delay that external power supply is allowed to be stablized；When external power supply power-off, capacitor EC8 starts to discharge, this
When divided by resistance R116 and resistance R118 due to the voltage of capacitor EC8, the voltage that the base stage of triode Q2 is subject at this time compared with
Small, the emitter of triode Q2 is pulled to voltage value when capacitor EC8 discharges at this time, at this time the voltage of triode Q2 emitter
Greater than the voltage of triode Q2 base stage, the emitter and base stage of triode Q2 is connected, and the electricity that capacitor EC8 is stored leads to
Triode Q2 release is crossed, the electricity that capacitor EC8 is stored after avoiding external power supply from powering off cannot rapidly deplete, and influence to prolong next time
Shi Xiaoguo.When the capacitor 1EC2 of setting can export the power supply after stablizing with scene effect tube chip 231, make the power supply to capacitor
1EC2 charges, and then postpones again, so that relatively early be filtered again by the power supply of field effect tube chip 231, setting
Capacitor 20C1 can filter the power supply postponed by 1EC2 by capacitor 20C1, so that power supply is more stable.The present embodiment
Delay pattern compared to it is existing by controller come timing, turning on the switch element after timing reaches certain value, allowing electricity
Source enters other equipment, and this existing way can not protect controller itself, and the present embodiment can be to controller itself
It is protected.
As an improved specific embodiment, the source lead of the field effect tube chip 231 is also connected with capacitor
It is grounded after 1EC1, which is grounded after being also connected with Transient Suppression Diode 232, the Transient Suppression Diode 232
Plus earth, cathode are connect with source lead.
Through the above technical solutions, external power supply can first charge to capacitor 1EC1 when external power supply power supply electrifying,
And then accomplish further to be delayed, the required capacity of capacitor 1EC2 or capacitor EC8 can be shared at this time, and then reduce capacitor
The volume of 1EC2 or capacitor EC8, so that circuit volume is smaller, simultaneously because the bigger price of the capacity of capacitor EC8 is higher, and
Price increase is relatively obvious, and the capacitor 1EC1 being arranged herein also can be reduced cost.Transient Suppression Diode 232 can effectively be prevented
It is only struck by lightning and subsequent conditioning circuit is caused to puncture and be burnt, and then improve the stability of circuit and extend the service life of circuit.
It further include the reset circuit 7 being electrically connected with control circuit 13 as an improved specific embodiment；The control
Circuit 13 and reset circuit 7 connect to power supply；The reset circuit 7 includes the first reset chip 71, first reset coil
Piece 71 has the first reset pin, the first grounding pin, the first power pins, the first resetting pin；First reset chip
The first of 71 resets pin, the first reset pin is connect with control circuit 13, the first ground connection of first reset chip 71
Pin ground connection, the first power pins connect power supply；It is provided with count threshold in first reset chip 71, when control circuit 13 is sent out
When sending reset signal to the first resetting pin, 71 reset count numerical value of the first reset chip, when 71 count number of the first reset chip
When value is more than count threshold, the first reset chip 71, which is sent, to be resetted fortunately to control circuit 13, and control circuit 13 re-powers.
Through the above technical solutions, the first reset chip 71 of setting can use CAT824TTDI, counting threshold is carried
Value, the resetting of the first reset chip 71 counts after the first resetting pin receives the reset signal that control circuit 13 exports, if first
Reset chip 71 never receives reset signal, and counting in the first reset chip 71 is more than count threshold, then first is multiple
For position chip 71 by the first reset pin output reset signal to control circuit 13, the first reset pin only need to be with control circuit 13
In control chip reset signal receive pin connection can restart control chip, and then allow control circuit 13 reset restart,
It avoids 13 program of control circuit from running stuck phenomenon, can rework after re-starting control circuit 13.
As an improved specific embodiment, the first reset pin of first reset chip 71 is connected with resistance
It is connect after R112 with control circuit 13, first reset pin is also connected with the second reset chip 72, second reset coil
Piece 72 has the second reset pin, second source pin, the second grounding pin；The second grounding pin ground connection, second source
Pin connects power supply；Second reset pin is connected to the first reset pin.
Through the above technical solutions, the second reset chip 72 of setting can use PT7M7809TT, setting in the chip
There is voltage threshold, when the voltage that second source pin receives is more than 200ms lower than voltage threshold state, the second reset is drawn
Foot will output reset signal to control circuit 13 control chip reset signal receive pin, at this time control circuit 13 reset
Restart, avoid due to operating voltage is unstable and it is relatively low cause circuit work abnormal, can be to avoid after re-starting control circuit 13
Caused by being controlled due to control circuit 13 the phenomenon that spread of voltage, so that the circuit of the present embodiment is more stable, anti-interference energy
Power is stronger.
As an improved specific embodiment, the resistance R112 is connected with row with respect to the other end of the first reset pin
Needle 73, for the tool of row's needle 73 there are two stitch, one of stitch the first width opposite with resistance R112 is that the other end of pin connects
It connects, another stitch is connected to power supply, and when two stitch for arranging needle 73 are shorted by external jumper cap, resistance R112 is opposite to arrange needle
73 one end is pulled up by power supply.
Through the above technical solutions, can use jumper cap when user does not need to use reset circuit 7 is shorted row's needle 73
Two stitch, one end of the opposite row's needle 73 of resistance R112 can be pulled to high level by power supply at this time, and then allow control circuit
The reset signal of 13 control chip receives pin and is always maintained at high level, and so that it will not by the first reset chip 71 and second
The interference for the reset signal that reset chip 72 exports, it is this to facilitate user's regulatory function in such a way that jumper cap is shorted, it is not required to
Software is changed, so that the work of control circuit 13 is more stable.
As an improved specific embodiment, assembling assembly 3 is provided on the shell 1, the assembling assembly 3 includes
The grafting pedestal 31 and clamping latch fitting 32 being fixedly connected on shell 1；The clamping latch fitting 32 and the fixed company of grafting pedestal 31
It connects, and be clamped latch fitting 32 there is elasticity；Inserting groove 311, the inserting groove 311 and outside are offered on the grafting pedestal 31
The flanging of DIN clamp rail is adapted, and the flanging of DIN clamp rail can be plugged into inserting groove 311；One end of the clamping latch fitting 32 is fixed
It is connected on grafting pedestal 31, other end tilting is stirred for manpower, and the clamping latch fitting 32 is offered with differential pedestal junction
Clamping groove 322, the clamping groove 322 are adapted with the flanging of DIN clamp rail, and the flanging of DIN clamp rail can be plugged into clamping groove 322
In；The clamping latch fitting 32 is provided with guiding surface 321, when the flanging and guiding surface 321 of DIN clamp rail are inconsistent and continue
When squeezing guiding surface 321, clamping latch fitting 32 is extruded deformation, clamping lock after the flanging of DIN clamp rail is embedded into clamping groove 322
Part 32 restores；Limit buckle 4 is additionally provided on the grafting pedestal 31, the limit buckle 4 is located at 311 notch of inserting groove, when DIN card
When the flanging of rail is inserted into inserting groove 311, limit buckle 4 clasps the flanging of DIN clamp rail.
Through the above technical solutions, when user needs to install intelligent acess digital SPC exchange, it can be by cabinet
DIN clamp rail is installed in sub, then a wherein side edgefold for DIN clamp rail is inserted into inserting groove 311, inserting groove 311 is right at this time
The wherein side of DIN clamp rail is installed, and then rotates Ethernet switch by fulcrum of the side edgefold, until being clamped latch fitting 32
Inconsistent with another side edgefold of DIN clamp rail, user can stir clamping latch fitting 32 with hand at this time, at this time the flanging of DIN clamp rail
It can be embedded into clamping groove 322, after the flanging of DIN clamp rail is embedded into clamping groove 322, user discharges clamping latch fitting 32,
The recovery of clamping latch fitting 32 can be fixed the flanging of DIN clamp rail at this time, and the present embodiment facilitates user installation intelligent acess number
Word programme-controlled exchange, and the DIN clamp rail being arranged is very universal in industrial application, can be adapted in industrial application, and
Cooperate assembling assembly 3 that can allow the more firm stabilization of installation of intelligent acess digital SPC exchange by DIN clamp rail, pacifies simultaneously
Assembly and disassembly are efficient and convenient.When the side of DIN clamp rail is installed with inserting groove 311, and carry out the flanging installation of the other side
When, it is only necessary to side that Ethernet switch is installed using DIN clamp rail is turned to the other side of itself and DIN clamp rail as fulcrum
Flanging fits, and continues to rotate simultaneously, is affixed the guiding surface 321 for being clamped latch fitting 32 with the side edgefold and merges mutual extrusion,
Since clamping latch fitting 32 has elasticity, clamping latch fitting 32 can be allowed to generate deformation under the action of guiding surface 321, at this time
People's manual toggle clamping latch fitting 32 is not needed, it can be by clamping latch fitting 32 outwardly against when DIN card by guiding surface 321
After the flanging of rail is embedded into clamping groove 322, clamping latch fitting 32 restores, and is clamped 32 conduplication side of latch fitting at this time and is fixed.When
After one side edgefold of DIN clamp rail is inserted into inserting groove 311, and using the side edgefold as fulcrum rotate Ethernet switch when,
In the course of rotation, the flanging of DIN clamp rail can be embedded into limit buckle 4, and 4 conduplication side of limit buckle is limited at this time, make it
It will not deviate from from inserting groove 311, only first unlock the clamping latch fitting 32 of the other side and DIN clamp rail, and rotate backward ether
The flanging of limit buckle 4 and DIN clamp rail could be allowed to be detached from after network switch to limit, this structure is simple, is effectively increased simultaneously
The stability and reliability installed between Ethernet switch and DIN clamp rail.
The above is only the preferred embodiment of the utility model, and the protection scope of the utility model is not limited merely to
Above-described embodiment, technical solution belonging to the idea of the present invention belong to the protection scope of the utility model.It should refer to
Out, for those skilled in the art, it is without departing from the principle of the utility model it is several improvement and
Retouching, these improvements and modifications also should be regarded as the protection scope of the utility model.
Claims (10)
1. a kind of video optical multiplexer based on FPGA, including shell (1) and the circuit board (2) being arranged in shell (1), feature
It is, the circuit board (2) includes optical module (11), transceiving chip (12), control circuit (13), Ethernet switching chip
(14), Ethernet interface (15), protection circuit (16), network transformer integrated chip (17)；The optical module (11) and outside
Optical fiber plug connection, also connect with transceiving chip (12), the transceiving chip (12) and Ethernet switching chip (14) are all connected with
To control circuit (13)；The Ethernet interface (15) connect with external ethernet plug, the Ethernet interface (15) and guarantor
Protection circuit (16) connection, also connect with network transformer integrated chip (17), the network transformer integrated chip (17) and with
Too net exchange chip (14) connects；The optical module (11) includes a fiber connector and signal processing circuit, the optical fiber
Connector is connect with external fiber plug, and the fiber connector has the signal for receiving the transmission of external fiber plug just
According to spasm foot, cathode data spasm foot, the cathode data spasm foot is connected with after resistance 1R11 and control circuit (13) number of poles
Connection, the node that the resistance 1R11 is connect with control circuit (13) are grounded after being also connected with resistance 1R22, are also connected with resistance
1R17 is followed by power supply；The anode data spasm foot is connect after being connected with resistance 1R10 with control circuit (13), the resistance
The node that 1R10 is connect with control circuit (13) is grounded after being also connected with resistance 1R23, is also connected with resistance 1R18 and is followed by power supply,
The resistance 1R10 and resistance 1R11 resistance value are 0 Europe；The anode data spasm foot is connected to receipts after being also connected with capacitor 1C3
It sends out chip (12), the anode data pin is grounded after being connected with resistance 1R20, and the cathode data spasm foot is also connected with electricity
It is connected to transceiving chip (12) after holding 1C4, the cathode data pin is grounded after being also connected with resistance 1R19.
2. the video optical multiplexer according to claim 1 based on FPGA, which is characterized in that the fiber connector also has
Carry out the coffin upon burial foot, cathode data of positive data for sending a signal to external fiber plug are carried out the coffin upon burial foot；The anode data are carried out the coffin upon burial foot
It being connected to transceiving chip (12) after being connected with capacitor 1C2, anode data foot of carrying out the coffin upon burial is also connected with resistance 1R7 and is followed by power supply,
It is grounded after being also connected with resistance 1R16, the cathode data carry out the coffin upon burial after foot is connected with capacitor 1C1 and are connected to transceiving chip (12), institute
It states cathode data foot of carrying out the coffin upon burial to be also connected with resistance 1R6 and be followed by power supply, be grounded after being also connected with resistance 1R15.
3. the video optical multiplexer according to claim 2 based on FPGA, which is characterized in that the anode data carry out the coffin upon burial foot also
It is connected with after resistance 1R8 after being connected with resistance 1R3 and is connect with control circuit (13), anode data foot of carrying out the coffin upon burial is also connected with electricity
It is connect after being connected with resistance 1R2 after resistance 1R9 with control circuit (13)；The resistance 1R3 is also connected with the resistance 1R8 node connecting
It is connected after having resistance 1R5 with resistance 1R2 and resistance the 1R9 node connecting, is also connected with resistance 1R4 between two nodes,
The resistance value of the resistance 1R8 and resistance 1R9 is 0 Europe.
4. the video optical multiplexer according to claim 3 based on FPGA, which is characterized in that the Ethernet interface (15)
Wherein four data transmission pins are connected separately with after resistance 6R20, resistance 6R21, resistance 6R22, resistance 6R23 and network transformation
Device integrated chip (17) connection, four data transmission pins are also connected with first gas discharge tube (181), second gas electric discharge
Manage (182), the first gas discharge tube (181) grounding pin ground connection, in addition two pins respectively with two of them data
Pin connection is transmitted, the grounding pin ground connection of the second gas discharge tube (182), in addition two pins are respectively with remaining two
A data transmission pin connection；The protection circuit (16) uses SLVU2 chip, and the SLVU2 chip and four data are transmitted
Pin is all connected with.
5. the video optical multiplexer according to claim 4 based on FPGA, which is characterized in that further include power-up time delay circuit
(23), the power-up time delay circuit (23) includes field effect tube chip (231), triode Q1, triode Q2；The field-effect tube
There are four drain lead, three source leads, a gate lead, four drain leads are mutually shorted chip (231) tool
It is connect afterwards with control circuit (13), gives control circuit (13) to export the power supply after delay, which is also connected with capacitor 1EC2
After be grounded, be grounded after being also connected with capacitor 20C1；Three source leads are mutually shorted and are connected with after resistance R114 and grid
The connection of pole pin, the gate lead are also connected with the collector that triode Q1 is connected to after resistance R115；The triode Q1
Emitter ground connection, base stage is connected with after switching diode ZD1 be connected with capacitor EC8 after be grounded, the switching diode ZD1's
Anode is connect with the base stage of triode Q1, and cathode is connect with capacitor EC8；The cathode of the switching diode ZD1 is also connected with electricity
It is connect after resistance R117 with the emitter of triode Q2；The base stage of the grounded collector of the triode Q2, the triode Q2 connects
It is grounded after being connected to resistance R118, is connect after being also connected with resistance R116 with the cathode of switching diode ZD1；The triode Q2's
Base stage is additionally coupled to the source lead of field effect tube chip (231), the source lead of the field effect tube chip (231) and outside
Power supply connection.
6. the video optical multiplexer according to claim 5 based on FPGA, which is characterized in that the field effect tube chip
(231) source lead is grounded after being also connected with capacitor 1EC1, after which is also connected with Transient Suppression Diode (232)
Ground connection, the plus earth of the Transient Suppression Diode (232), cathode are connect with source lead.
7. the video optical multiplexer according to claim 6 based on FPGA, which is characterized in that further include and control circuit (13)
The reset circuit (7) of electrical connection；The control circuit (13) and reset circuit (7) connect to power supply；The reset circuit (7)
Including the first reset chip (71), first reset chip (71) has the first reset pin, the first grounding pin, the first electricity
Source pin, the first resetting pin；The first resetting pin, the first reset pin of first reset chip (71) are electric with control
Road (13) connection, the first grounding pin ground connection of first reset chip (71), the first power pins connect power supply；Described first
It is provided with count threshold in reset chip (71), when control circuit (13) send reset signal to the first resetting pin, first
Reset chip (71) reset count numerical value, when the first reset chip (71) count value is more than count threshold, the first reset coil
Piece (71), which sends to reset, fortunately gives control circuit (13), and control circuit (13) re-powers.
8. the video optical multiplexer according to claim 7 based on FPGA, which is characterized in that first reset chip (71)
The first reset pin be connected with resistance R112 after connect with control circuit (13), first reset pin is also connected with second
Reset chip (72), second reset chip (72) have the second reset pin, second source pin, the second grounding pin；
The second grounding pin ground connection, second source pin connect power supply；Second reset pin is connected to the first reset pin.
9. the video optical multiplexer according to claim 8 based on FPGA, which is characterized in that the resistance R112 is with respect to first
The other end of reset pin is connected with row needle (73), and there are two stitch, one of stitch and resistance for row's needle (73) tool
R112 is connected with respect to the other end that the first width is pin, another stitch is connected to power supply, when two stitch quilts of row needle (73)
When external jumper cap is shorted, resistance R112 is opposite, and the one end for arranging needle (73) is pulled up by power supply.
10. the video optical multiplexer according to claim 9 based on FPGA, which is characterized in that be provided on the shell (1)
Assembling assembly (3), the assembling assembly (3) include the grafting pedestal (31) being fixedly connected on shell (1) and clamping latch fitting
(32)；The clamping latch fitting (32) is fixedly connected with grafting pedestal (31), and is clamped latch fitting (32) with elasticity；The grafting bottom
It is offered inserting groove (311) on seat (31), the inserting groove (311) is adapted with the flanging of outside DIN clamp rail, DIN clamp rail
Flanging can be plugged into inserting groove (311)；One end of clamping latch fitting (32) is fixedly connected on grafting pedestal (31), another
End tilts and stirs for manpower, and the clamping latch fitting (32) and differential pedestal junction offer clamping groove (322), the clamping groove
(322) it is adapted with the flanging of DIN clamp rail, the flanging of DIN clamp rail can be plugged into clamping groove (322)；The clamping latch fitting
(32) guiding surface (321) are provided with, when flanging and guiding surface (321) of DIN clamp rail are inconsistent and continue to squeeze guiding tiltedly
When face (321), clamping latch fitting (32) is extruded deformation, and the flanging of DIN clamp rail is clamped latch fitting after being embedded into clamping groove (322)
(32) it restores；It is additionally provided with limit buckle (4) on the grafting pedestal (31), the limit buckle (4) is located at inserting groove (311) slot
Mouthful, when the flanging of DIN clamp rail be inserted into inserting groove (311) it is interior when, limit buckle (4) clasps the flanging of DIN clamp rail.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821867226.1U CN208806918U (en) | 2018-11-13 | 2018-11-13 | A kind of video optical multiplexer based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821867226.1U CN208806918U (en) | 2018-11-13 | 2018-11-13 | A kind of video optical multiplexer based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208806918U true CN208806918U (en) | 2019-04-30 |
Family
ID=66239636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821867226.1U Withdrawn - After Issue CN208806918U (en) | 2018-11-13 | 2018-11-13 | A kind of video optical multiplexer based on FPGA |
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| Country | Link |
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| CN (1) | CN208806918U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194937A (en) * | 2018-11-13 | 2019-01-11 | 浙江恒捷通信科技有限公司 | A kind of video optical multiplexer based on FPGA |
-
2018
- 2018-11-13 CN CN201821867226.1U patent/CN208806918U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194937A (en) * | 2018-11-13 | 2019-01-11 | 浙江恒捷通信科技有限公司 | A kind of video optical multiplexer based on FPGA |
| CN109194937B (en) * | 2018-11-13 | 2024-02-13 | 浙江恒捷通信科技有限公司 | Video optical transmitter and receiver based on FPGA |
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