CN208402210U - Circuit board structure with gap filling layer - Google Patents
Circuit board structure with gap filling layer Download PDFInfo
- Publication number
- CN208402210U CN208402210U CN201821173040.6U CN201821173040U CN208402210U CN 208402210 U CN208402210 U CN 208402210U CN 201821173040 U CN201821173040 U CN 201821173040U CN 208402210 U CN208402210 U CN 208402210U
- Authority
- CN
- China
- Prior art keywords
- filling layer
- joint filling
- overlay coating
- layer
- connection terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000011248 coating agent Substances 0.000 claims abstract description 41
- 238000000576 coating method Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000007747 plating Methods 0.000 abstract description 8
- 239000000463 material Substances 0.000 description 15
- 238000003466 welding Methods 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000006071 cream Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000011469 building brick Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000001680 brushing effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 fluororesin Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
The utility model provides a circuit board structure with layer of caulking, include: a substrate, a gap filling layer and a surface plating layer. The substrate has a plurality of connection terminals. The joint filling layer is formed between the connecting terminals, and the surface of the connecting terminals is lower than the surface of the joint filling layer. The surface plating layers are respectively formed on the surfaces of the connecting terminals, and each surface plating layer is provided with an upper surface and at least one side surface. Wherein, the gap filling layer at least partially covers the side surface of the surface coating, and the difference between the surface of the gap filling layer and the upper surface of the surface coating is less than 5 μm.
Description
Technical field
The utility model is the structure in relation to a kind of printed circuit board.
Background technique
With the trend toward miniaturization of electronic product, circuit board also needs production ground more plus frivolous, the conductor wire on circuit board
The arrangement of road and connection terminal is also more and more intensive, therefore the design and manufacture institute's facing challenges of route are also higher and higher.
Since the gap between connection terminal is smaller and smaller, when connection terminal surface formed overlay coating after, be easy because away from
From too close to and occur short circuit problem.On the other hand, when the electronic building brick needs being set on circuit board are relatively large number of
When tin cream is welded, excessive tin cream is also easy to be in contact with other electronic building bricks or connection terminal and lead to short circuit.
Therefore how to reduce the generation of circuit board short circuit problem, and the wide usage of circuit board is improved, is intended to for the utility model
The technical task of solution.
Utility model content
In view of this, the circuit with joint filling layer the main purpose of the utility model is to provide a kind of wide usage is hardened
Structure.
In order to reach above-mentioned purpose, the utility model provides a kind of board structure of circuit with joint filling layer, comprising: a base
Plate, a joint filling layer and an overlay coating.Substrate has multiple connection terminals.Joint filling layer is formed between connection terminal, and is connected
Terminal surfaces are lower than joint filling layer surface.Overlay coating is respectively formed in connection terminal surface, and overlay coating has a upper surface
An and at least side surface.Wherein, joint filling layer is at least partly covered in the side surface of overlay coating, and joint filling layer surface and surface are plated
The offset of layer upper surface is less than 5 μm.
The joint filling layer includes one first joint filling layer and one second joint filling layer.Second joint filling layer be formed in the first joint filling layer it
On, the first joint filling layer is filled in the gap of connection terminal, and the second joint filling layer is at least partly covered in the side surface of overlay coating.
The upper surface of the overlay coating can be higher than, be flush to or lower than joint filling layer surface.
By adjusting the thickness of overlay coating, connection terminal is made to be applicable to the setting of different electronic modules, and can be promoted
On the other hand the wide usage of board structure of circuit with joint filling layer is carried out exhausted using the joint filling layer being filled between connection terminal
Edge, and can avoid connection terminal too close to when caused short circuit problem.
The detailed content of other effects and embodiment in relation to the utility model, cooperation Detailed description of the invention are as follows.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application, for those of ordinary skill in the art, without creative efforts,
It can also be obtained according to these attached drawings other attached drawings.
Figure 1A to Fig. 1 E is provided the production process sectional view of the substrate of tool soldermask layer by the utility model；
Fig. 2A to Fig. 2 E is the production of the board structure of circuit first embodiment provided by the utility model with joint filling layer
Process sectional view；
Fig. 3 A figure to Fig. 3 D be the board structure of circuit second embodiment provided by the utility model with joint filling layer system
Make process sectional view.
Symbol description
1 10 substrate of board structure of circuit with joint filling layer
101 first surface, 102 second surface
11 face copper, 111 connection terminal
12 first anti-welding 121 first joint filling layers of material layer
13 second anti-welding material layers 131 are open
132 second joint filling layer, 14 overlay coating
141 upper surface, 142 side surface
9 brushing wheels
Specific embodiment
Firstly, please referring to Figure 1A to Fig. 1 E, Figure 1A to Fig. 1 E is provided the system of the substrate of tool soldermask layer by the utility model
Make process sectional view.Firstly, providing a substrate 10, substrate 10 has a first surface 101 and second surface 102, and substrate 10
It can be lamina structure or multilayer composite sheet structure, and substrate 10 can be flexible circuit board (Flexible Printed
Circuit, FPC) substrate or rigid circuit board (Printed Circuit Board, PCB) substrate.In this present embodiment,
First surface 101 is laminated to be had thin copper foil (being not shown in the drawing) and can carry out copper facing, in 101 forming face of first surface of substrate 10
Copper 11 (as shown in Figure 1A).Then, multiple to be formed in 10 surface of substrate with route image transfer technology by 11 image conversion of face copper
Connection terminal 111 (as shown in Figure 1B), and after graphical, there is gap between connection terminal 111.Wherein, connection terminal 111
For the part contacted in the board structure of circuit with joint filling layer with scolding tin or routing, and it is common to make connection terminal 111
Material can be copper.
Please refer to Fig. 1 C, then, be coated with anti-welding material in the first surface 101 of substrate 10, with formed covering substrate 10 and
The anti-welding material layer 12 of the first of connection terminal 111.First anti-welding material layer 12 is an insulating layer, and anti-welding material can are as follows: epoxy
Resin, silicone resin, polyimide resin, phenolic resin, fluororesin, silica or aluminium oxide.Then, in the first anti-welding material
After 12 solidification of layer, the soldermask layer 12 on 111 surface of connection terminal can be brushed with brushing wheel 9, between connection terminal 111
Gap forms the first joint filling layer 121, and the first joint filling layer 121 then can be used as insulation and be used (as referring to figure 1E).
Fig. 2A to Fig. 2 E is please referred to, Fig. 2A to Fig. 2 E is the board structure of circuit provided by the utility model with joint filling layer
The production process sectional view of first embodiment.Hookup 1C is coated with anti-welding material in connection terminal 111 and first in Fig. 2A
On joint filling layer 121, to form the second anti-welding material layer 13 for being covered in connection terminal 111 and the first joint filling layer 121.Second is anti-
The wlding bed of material 13 is also the insulating layer formed by anti-welding material.Then, in the second anti-welding 13 uplifting window of material layer, whereby formation pair
It should be in the opening 131 and the second joint filling layer 132 (as shown in Figure 2 B) of 111 position of connection terminal.It then, can be with chemical plating
(chemical plating) or the mode of plating form overlay coating 14 in 111 surface of connection terminal, have with acquisition one and fill out
Stitch the board structure of circuit 1 of layer.Wherein, overlay coating 14 has a upper surface 141 and a side surface 142, and the second joint filling layer 132
(as shown in Figure 2 C) is at least partly covered on the side surface 142 of overlay coating 14.The material of the overlay coating 14 can are as follows:
Nickel, gold, silver, palladium or its alloy.
Please continue to refer to shown in Fig. 2 C, Fig. 2 D and Fig. 2 E, when the upper surface of overlay coating 14 141 is higher than the second joint filling layer
When 132 surface (as shown in Figure 2 C), the offset on 132 surface of upper surface 141 and the second joint filling layer of overlay coating 14 less than 5 μm,
And 132 part of the second joint filling layer is covered on the side surface 142 of overlay coating 14；When the upper surface of overlay coating 14 141 flushes
When the second joint filling 132 surface of layer (as shown in Figure 2 D), 132 surface of upper surface 141 and the second joint filling layer of overlay coating 14
Offset is 0 μm, and the second joint filling layer 132 is completely covered by the side surface 142 of overlay coating 14；When the upper table of overlay coating 14
When face 141 is lower than the second joint filling 132 surface of layer (as shown in Figure 2 E), the upper surface 141 of overlay coating 14 and the second joint filling layer 132
The offset on surface is less than 5 μm, and the second joint filling layer 132 is completely covered by the side surface 142 of overlay coating 14.Herein, institute
Stating " offset " refers to two surfaces in the spacing of thickness direction.
Though the first surface 101 that the present embodiment is only set forth in substrate 10 forms connection terminal 111, the first joint filling layer 121, opens
The embodiment of the 131, second joint filling layer 132 of mouth and overlay coating 14, but in practical application, aforementioned components can also be formed in base
The second surface 102 of plate 10, or, it can be formed simultaneously on first surface 101 and second surface 102, without with the present embodiment
The embodiment proposed is limited.
Fig. 3 A to Fig. 3 D is please referred to, Fig. 3 A to Fig. 3 D is the board structure of circuit provided by the utility model with joint filling layer
The production process sectional view of second embodiment.Hookup 1C is in a manner of etching or brushing to connection terminal 111 in Fig. 3 A
It carries out one and subtracts copper step, make the surface of connection terminal 111 lower than 121 surface of the first joint filling layer.It then, can be with chemical plating or plating
Mode in 111 surface of connection terminal formed overlay coating 14 with obtain one with joint filling layer board structure of circuit 1.Wherein, table
The upper surface 141 of face coating 14 can also be higher than (as shown in Figure 3B), be flush to (as shown in Figure 3 C) or lower than (as shown in Figure 3D)
The surface of first joint filling layer 121, and the offset on 121 surface of the upper surface 141 of overlay coating 14 and the first joint filling layer is also smaller than 5 μ
M, and the first joint filling layer 121 be can be partially covered or be completely covered by the side surface 142 of overlay coating 14.The overlay coating 14
Material also may be used are as follows: nickel, gold, silver, palladium or its alloy.Connect though the first surface 101 that the present embodiment is only set forth in substrate 10 is formed
The embodiment of connecting terminal 111, the first joint filling layer 121 and overlay coating 14, but in practical application, aforementioned components can also be formed
In the second surface 102 of substrate 10, or, it can be formed simultaneously on first surface 101 and second surface 102, without with this reality
The embodiment that example is proposed is applied to be limited.
Based on above-mentioned design, the made board structure of circuit 1 with joint filling layer of the utility model can plate by adjusting surface
The thickness of layer 14, makes connection terminal 111 be applicable to the setting of different electronic modules, and can promote the circuit board with joint filling layer
The wide usage of structure.For example, when set electronic building brick needs relatively large number of tin cream to be welded, table can be made
The upper surface 141 of face coating 14 is lower than the circuit board with joint filling layer on first joint filling layer 121 (or second joint filling layer 132) surface
Structure 1.So when tin cream injection is set to the opening of 111 position of connection terminal, tin cream can be limited to the range of opening, and
It can avoid the excessive caused short circuit problem of tin cream.Or when set electronic building brick needs the electrical contact of larger area
When, the upper surface 141 that can make overlay coating 14 is higher than having for first joint filling layer 121 (or second joint filling layer 132) surface and fills out
The board structure of circuit 1 for stitching layer, can so increase the contact area of electronic building brick Yu connection terminal 111.On the other hand, due to filling out
The the first joint filling layer 121 filled between connection terminal 111 have effects that insulation, and can avoid connection terminal 111 too close to
When caused short circuit problem.
Embodiment described above and/or embodiment are only the preferable realities to illustrate to realize the utility model technology
Example and/or embodiment are applied, not the embodiment of the utility model technology is made any form of restriction, any this field
Technical staff, in the range for not departing from technological means disclosed in the content of the present invention, when can make a little change or modification
For other equivalent embodiments, but still it should be regarded as technology identical with the utility model in essence or embodiment.
Claims (5)
1. a kind of board structure of circuit with joint filling layer characterized by comprising
One substrate has multiple connection terminals；
One joint filling layer, is formed between those connection terminals, and those connection terminal surfaces are lower than the joint filling layer surface；And
One overlay coating is respectively formed in those connection terminal surfaces, and the overlay coating has a upper surface and at least side
Surface；
Wherein, which is at least partly covered in the side surface of the overlay coating, and the joint filling layer surface and the overlay coating
The offset of upper surface is less than 5 μm.
2. as described in claim 1 with the board structure of circuit of joint filling layer, which is characterized in that the joint filling layer is filled out including one first
Seam layer and one second joint filling layer, the second joint filling layer are formed on the first joint filling layer, which is filled in those
The gap of connection terminal, and the second joint filling layer is at least partly covered in the side surface of the overlay coating.
3. as described in claim 1 with the board structure of circuit of joint filling layer, which is characterized in that the upper surface of the overlay coating is high
In the joint filling layer surface.
4. as described in claim 1 with the board structure of circuit of joint filling layer, which is characterized in that the upper surface of the overlay coating is neat
It puts down in the joint filling layer surface.
5. as described in claim 1 with the board structure of circuit of joint filling layer, which is characterized in that the upper surface of the overlay coating is low
In the joint filling layer surface.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107123223A TWI742297B (en) | 2018-07-05 | 2018-07-05 | Circuit board structure having gap filling layer |
| TW107123223 | 2018-07-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208402210U true CN208402210U (en) | 2019-01-18 |
Family
ID=65128880
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810817336.5A Active CN110691456B (en) | 2018-07-05 | 2018-07-24 | Circuit board structure with joint filling layer |
| CN201821173040.6U Active CN208402210U (en) | 2018-07-05 | 2018-07-24 | Circuit board structure with gap filling layer |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810817336.5A Active CN110691456B (en) | 2018-07-05 | 2018-07-24 | Circuit board structure with joint filling layer |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN110691456B (en) |
| TW (1) | TWI742297B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112566352A (en) * | 2019-09-25 | 2021-03-26 | 李家铭 | Circuit structure with anti-laser seam filling layer and manufacturing method thereof |
| CN112566371A (en) * | 2019-09-25 | 2021-03-26 | 李家铭 | Circuit structure with gap filling layer and manufacturing method thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009099619A (en) * | 2007-10-12 | 2009-05-07 | Fujitsu Ltd | Core substrate and its manufacturing method |
| KR101156896B1 (en) * | 2010-07-09 | 2012-06-21 | 삼성전기주식회사 | Semiconductor package substrate and manufacturing method of the same |
| TWI451826B (en) * | 2012-05-28 | 2014-09-01 | Zhen Ding Technology Co Ltd | Multilayer printed circuit board and method for manufacturing same |
| KR101388787B1 (en) * | 2012-07-25 | 2014-04-23 | 삼성전기주식회사 | Solder ball mounting apparatus, solder ball mounting system and method for mounting solder ball using the same |
| WO2017038713A1 (en) * | 2015-08-31 | 2017-03-09 | 住友ベークライト株式会社 | Method for manufacturing printed wiring board, and method for manufacturing semiconductor device |
| CN207099433U (en) * | 2017-06-09 | 2018-03-13 | 同泰电子科技股份有限公司 | Circuit board structure |
| TWM568017U (en) * | 2018-07-05 | 2018-10-01 | 同泰電子科技股份有限公司 | Circuit board structure having caulking layer |
-
2018
- 2018-07-05 TW TW107123223A patent/TWI742297B/en active
- 2018-07-24 CN CN201810817336.5A patent/CN110691456B/en active Active
- 2018-07-24 CN CN201821173040.6U patent/CN208402210U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112566352A (en) * | 2019-09-25 | 2021-03-26 | 李家铭 | Circuit structure with anti-laser seam filling layer and manufacturing method thereof |
| CN112566371A (en) * | 2019-09-25 | 2021-03-26 | 李家铭 | Circuit structure with gap filling layer and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI742297B (en) | 2021-10-11 |
| CN110691456B (en) | 2022-12-23 |
| TW202007234A (en) | 2020-02-01 |
| CN110691456A (en) | 2020-01-14 |
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| GR01 | Patent grant |