CN208400877U - A kind of film flip LED chips - Google Patents
A kind of film flip LED chips Download PDFInfo
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- CN208400877U CN208400877U CN201820853430.1U CN201820853430U CN208400877U CN 208400877 U CN208400877 U CN 208400877U CN 201820853430 U CN201820853430 U CN 201820853430U CN 208400877 U CN208400877 U CN 208400877U
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Abstract
The utility model discloses a kind of film flip LED chips, including LED wafer, the LED wafer includes the first semiconductor layer, active layer, the second semiconductor layer, reflecting layer and the first passivation layer being sequentially arranged on the first semiconductor layer, set on the first passivation layer surface and extend to first electrode on the first semiconductor layer, through the first passivation layer and the second electrode on reflecting layer is set, first electrode and second electrode mutually insulated；The second passivation layer, the first bonded layer, the second bonded layer and the silicon base being sequentially arranged in LED wafer；First pad, first pad runs through silicon base, the second bonded layer, the first bonded layer and the second passivation layer, and is conductively connected with first electrode；Second pad, second pad runs through silicon base, the second bonded layer, the first bonded layer and the second passivation layer, and is conductively connected with second electrode.The film flip LED chips of the utility model, not only improve the external quantum efficiency of chip, while chip current being made to be evenly distributed.
Description
Technical field
The utility model relates to LED technology field more particularly to a kind of film flip LED chips.
Background technique
LED (Light Emitting Diode, light emitting diode) be it is a kind of using Carrier recombination when release energy shape
At luminous semiconductor devices, LED chip is with power consumption is low, coloration is pure, the service life is long, small in size, the response time is fast, energy conservation and environmental protection
Equal many advantages.
Existing LED chip mainly includes packed LED chip, flip LED chips and vertical LED chip.With forward LED core
Piece is compared with vertical LED chip, and flip LED chips, which have, exempts from wire-bonding package, more preferable, the resistance to heavy current impact of heat dissipation, outer quantum effect
The higher advantage of rate.
Existing flip LED chips generally form epitaxial layer and electrode on a sapphire substrate, are then welded on chip
On substrate, and the light that epitaxial layer issues is issued from one side of substrate.But can partially be absorbed by substrate by the light that epitaxial layer issues,
To reduce the external quantum efficiency of LED chip.
Existing method is to fix flip LED chips on a silicon substrate by way of bonding, then serves as a contrast sapphire
Bottom carries out glass.The patent of Publication No. CN107910406A discloses the LED chip and its manufacturing method of a kind of membrane structure,
Its manufacturing method includes: to make chip bonding electrode layer in crystal column surface, and chip bonding electrode layer passes through shallow slot and N-GaN layers of company
It connects；Wafer is bonded with the silicon substrate for being vapor-deposited with bonded layer, silicon substrate lower electrode layer is deposited in a surface of silicon substrate, silicon substrate
Silicon substrate bonding electrode layer is deposited in another surface, and chip bonding electrode layer is bonded with silicon substrate bonding electrode layer；It will be blue
Jewel substrate desquamation performs etching to form opening in release surface, and opening extends to reflecting layer by N-GaN layers of surface；Above-mentioned
The opening that step obtains makes chip positive terminal pad layer.Above-mentioned patent is performed etching in release surface, to be formed by N-GaN layers
Surface extend to the opening in reflecting layer, and positive terminal pad is formed on reflecting layer, and the electrode for being located at silicon substrate lower surface is
As negative terminal pad, wherein the area of positive terminal pad and negative terminal pad difference is larger, is easy to cause the current distribution of chip not
, in addition, electric current, which is needed, could excite MQW quantum well radiation, to mention by structures such as silicon substrate, bonded layers from reflecting layer
The high thermal resistance of chip.
Summary of the invention
Technical problem to be solved by the utility model is to provide a kind of film flip LED chips, improve the outer of chip
Quantum efficiency, while chip current being made to be evenly distributed.
In order to solve the above-mentioned technical problem, the utility model provides a kind of film flip LED chips, which is characterized in that
Include:
LED wafer, the LED wafer include the first semiconductor layer, are sequentially arranged in active layer on the first semiconductor layer, the
Two semiconductor layers, reflecting layer and the first passivation layer, set on the first passivation layer surface and extend on the first semiconductor layer first
Through the first passivation layer and the second electrode on reflecting layer is arranged in, first electrode and second electrode mutually insulated in electrode；
The second passivation layer, the first bonded layer, the second bonded layer and the silicon base being sequentially arranged in LED wafer；
First pad, first pad run through silicon base, the second bonded layer, the first bonded layer and the second passivation layer, and
It is conductively connected with first electrode；
Second pad, second pad run through silicon base, the second bonded layer, the first bonded layer and the second passivation layer, and
It is conductively connected with second electrode；
The third passivation layer of silicon substrate surface, the first pad and the second pad side wall is set.
As an improvement of the above scheme, the diameter upper right of the first pad and the second pad is successively decreased down.
As an improvement of the above scheme, the first electrode on the first passivation layer is equal with the height of second electrode.
As an improvement of the above scheme, face of the area of the first electrode on the first passivation layer less than the first passivation layer
Product.
As an improvement of the above scheme, the LED wafer further includes set on saturating between the second semiconductor layer and reflecting layer
Bright conductive layer.
As an improvement of the above scheme, it further includes on reflecting layer that the LED wafer, which further includes set on the LED wafer,
Metal barrier.
As an improvement of the above scheme, metal barrier is covered on the surface and two sides in the reflecting layer, and extends over
In the two sides of transparency conducting layer.
As an improvement of the above scheme, the area of the silicon base is equal to the area of substrate.
As an improvement of the above scheme, the silicon base is non-conductive silicon wafer.
Implement the utility model, has the following beneficial effects:
1, the utility model provides a kind of film flip LED chips, and the structure of first electrode is optimized, by
One electrode is arranged in the default surface of the first passivation layer and extends on the first semiconductor layer, is electrically connected with the first semiconductor layer,
So that the current distribution of chip is more uniform, shorten the flow path of electric current, convenient for by first electrode draw with the first pad into
Row is conductively connected.
2, in order to cooperate the structure to first electrode to optimize, the utility model passes through the first passivation layer and the second passivation
The mutual cooperation of layer, so that first electrode and second electrode mutually insulated, and enable the first bonded layer that LED wafer is set
On.
3, the diameter upper right of the first pad and the second pad is successively decreased down, can only reduce the damage to each layer structure, also
The material to form pad can be reduced, cost is reduced.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of film flip LED chips of the utility model；
Fig. 2 is a kind of structural schematic diagram of film flip LED chips of another embodiment of the utility model；
Fig. 3 is a kind of production flow diagram of film flip LED chips of the utility model；
Fig. 4 is the production flow diagram of the utility model LED wafer；
Fig. 5 is the flow chart that the utility model performs etching LED semi-finished product.
Specific embodiment
It is practical new to this below in conjunction with attached drawing to keep the purpose of this utility model, technical solution and advantage clearer
Type is described in further detail.
Referring to Fig. 1, the utility model provides a kind of film flip LED chips, comprising:
LED wafer, the LED wafer include the first semiconductor layer 21, are sequentially arranged in active on the first semiconductor layer 21
The 22, second semiconductor layer 23 of layer, reflecting layer 40 and the first passivation layer 50 set on 50 surface of the first passivation layer and extend to the first half
First electrode 24 in conductor layer 21, through the first passivation layer 50 and the second electrode 25 that is arranged on reflecting layer 30, the first electricity
25 mutually insulated of pole 24 and second electrode；
The second passivation layer 60, the first bonded layer 71, the second bonded layer 72 and the silicon base 80 being sequentially arranged in LED wafer；
First pad 91, first pad 91 run through silicon base 80, the second bonded layer 72, the first bonded layer 71 and second
Passivation layer 60, and be conductively connected with first electrode 24；
Second pad 92, second pad 92 run through silicon base 80, the second bonded layer 72, the first bonded layer 71 and second
Passivation layer 60, and be conductively connected with second electrode 25；
The third passivation layer 90 of 92 side wall of 80 surface of silicon base, the first pad 91 and the second pad is set.
First semiconductor layer 21 and the second semiconductor layer 23 are gallium nitride-based semiconductor, and active layer 22 is gallium nitride base
Active layer.In addition, the material of the first semiconductor layer 21 of the application other embodiments offer, the second semiconductor layer 23 and active layer 22
Matter can also be other materials, be not particularly limited to this application.Wherein, the first semiconductor layer 21 can be N-type semiconductor
Layer, then the second semiconductor layer 23 is p type semiconductor layer；Alternatively, the first semiconductor layer 21 is p type semiconductor layer, and the second half lead
Body layer 23 is that n type semiconductor layer needs according to reality the conduction type of the first semiconductor layer 21 and the second semiconductor layer 23
Using being designed, this application is not particularly limited.
It should be noted that the structure of first electrode is optimized in the utility model, by first electrode 24 draw with
First pad 91 is conductively connected, and the first electrode 24 is arranged in the default surface of the first passivation layer 50 and extends to first
It on semiconductor layer 21, is electrically connected with the first semiconductor layer 21, so that the current distribution of chip is more uniform, shortens the flowing of electric current
Path, convenient for first electrode extraction to be conductively connected with the first pad.
Existing first electrode is directly formed in the first semiconductor layer, when flip-chip to be welded on substrate, with
The pad of one electrode connection needs to extract first electrode through multilayered structure.Alternatively, increasing the thickness of first electrode
Degree, directly exposes first electrode, still, will increase the cost of chip in this way and increases the voltage of chip, and the first electricity
It is easy to be in contact with other structures and generate short circuit.
Wherein, area of area of the first electrode 24 on the first passivation layer 50 less than the first passivation layer 50.Preferably, exist
First electrode 24 on first passivation layer 50 is equal with the height of second electrode 25, in this way convenient for subsequent with the first pad 91 and the
Two pads 92 form connection.
Wherein, second passivation layer 60 is covered on 50 surface of first electrode 24, second electrode 25 and the first passivation layer, the
Two passivation layers 60 further insulate first electrode 24 and second electrode 25, prevent first electrode 24 and second electrode 25 from sending out
Raw electrical connection；Secondly, the second passivation layer 60 is also used to insulate first electrode 24, second electrode 25 and the first bonded layer 70
Come, so that the first bonded layer 70 can be arranged in LED wafer.Third passivation layer 90 is for protecting the first pad 91 and second
Pad 92 prevents pad from falling in welding, and the first pad 91 and the second pad 92 is insulated.Preferably, first is blunt
Change layer 50, the second passivation layer 60 and third passivation layer 90 to be made of insulating material.
The diameter upper right of first pad 91 and the second pad 92 is successively decreased down, can not only reduce the damage to each layer structure
Wound, can also reduce the material to form pad, reduce cost.
Preferably, the first pad 91 is arranged on the second predeterminable area of silicon base 80 and extends in first electrode 24,
Second pad 92 is arranged on the third predeterminable area of silicon base 90 and extends in second electrode 25.More preferably, the first pad
91 and second pad 92 area equation.
Preferably, the area of the silicon base is equal to the area of substrate, and the silicon base is non-conductive silicon wafer.Using face
The big non-conductive silicon wafer such as product, in order to provide enough support forces to LED wafer in subsequent removal substrate.
Referring to fig. 2, the carrier of LED wafer flocks together in order to prevent, the light extraction efficiency of high chip, and the LED is brilliant
Circle further includes set on the transparency conducting layer 30 between the second semiconductor layer 23 and reflecting layer 40.The material of the transparency conducting layer 30
For indium tin oxide.
Metallic reflection migration in reflecting layer 40 in order to prevent, improves the external quantum efficiency of chip, the LED wafer is also wrapped
Include the metal barrier 41 being set on reflecting layer 40.
Wherein, the metal barrier 41 is covered on the surface and two sides in the reflecting layer 40, and extends over transparent
The two sides of conductive layer 30 effectively prevent the anti-raw migration of the metal in reflecting layer 40 and transparency conducting layer 30, guarantee reflecting layer 40
Reflectivity and avoid chip occur short circuit.
Referring to Fig. 3, the production method of film flip LED chips described above, comprising the following steps:
S101: providing LED wafer, and the LED wafer includes substrate, and the first semiconductor layer for being sequentially arranged on substrate has
Active layer, the second semiconductor layer, reflecting layer and the first passivation layer set on the first passivation layer surface and extend on the first semiconductor layer
First electrode, through the first passivation layer and the second electrode on reflecting layer is set, first electrode and second electrode are mutually exhausted
Edge.
The carrier of LED wafer flocks together in order to prevent, the light extraction efficiency of high chip, and the LED wafer further includes
Transparency conducting layer between the second semiconductor layer and reflecting layer.
Metallic reflection migration in reflecting layer in order to prevent, improves the external quantum efficiency of chip, the LED wafer further includes
Metal barrier on reflecting layer.
Specifically, referring to fig. 4, form LED wafer the following steps are included:
S201: substrate is provided.
The material of the substrate can be sapphire, silicon carbide or silicon, or other semiconductor materials, the present embodiment
In substrate be preferably Sapphire Substrate.
S202: substrate surface formed epitaxial layer, the epitaxial layer include the first semiconductor layer being sequentially arranged on substrate,
Active layer and the second semiconductor layer；
Specifically, the first semiconductor layer provided by the embodiments of the present application and the second semiconductor layer are gallium nitride-based semiconductor
Layer, active layer are gallium nitride base active layer；In addition, the first semiconductor layer provided by the embodiments of the present application, the second semiconductor layer and
The material of active layer can also be other materials, be not particularly limited to this application.
Wherein, the first semiconductor layer can be n type semiconductor layer, then the second semiconductor layer is p type semiconductor layer；Alternatively,
First semiconductor layer is p type semiconductor layer, and the second semiconductor layer is n type semiconductor layer, for the first semiconductor layer and second
The conduction type of semiconductor layer needs to be designed according to practical application, is not particularly limited to this application.
It should be noted that being equipped with caching between the substrate and the epitaxial layer in the other embodiments of the application
Rush layer (not shown).
S203: performing etching the epitaxial layer, forms the exposed region for being etched to the first semiconductor layer.
Specifically, using photoresist or SiO2As exposure mask, and use inductively coupled plasma etching technique or reaction
Ion etching etching technics performs etching the epitaxial layer, through second semiconductor layer and active layer and extends to described
First semiconductor layer exposes first semiconductor layer, to form exposed region.Due to photoresist and SiO2Have
High etching ratio, convenient for etching, so that the etching pattern needed for being formed, improves the precision of etching.In the other embodiments of the application
In, it can also be using the substance of other high etching selection ratios as exposure mask.Exposed region is also used in addition to being used to form first electrode
As Cutting Road.
In order to improve the light extraction efficiency of chip, the side light extraction efficiency of epitaxial layer is improved, the shape of the exposed region is
Inverted trapezoidal.In the other embodiments of the application, the shape of the exposed region can also be polygon.
S204: transparency conducting layer, reflecting layer and metal barrier are sequentially formed on second semiconductor layer, is obtained
LED first product.
Using photoresist or SiO2As exposure mask, it is deposited using electron beam evaporation process in second semiconductor layer surface
Layer of transparent conductive layer.Wherein, vapor deposition temperature is 0-300 DEG C, oxygen flow 5-20sccm, and vapor deposition chamber vacuum degree is 3.0-
10.0E-5, evaporation time 100-300min.When temperature is deposited lower than 0 DEG C, transparency conducting layer can not obtain enough energy
It is migrated, the transparency conducting layer of formation is second-rate, and defect is more；When temperature is deposited higher than 300 DEG C, temperature is excessively high, film
Energy is excessive to be not easy to deposit on epitaxial layer, and deposition rate is slack-off, and efficiency reduces.When oxygen flow is less than 5sccm, oxygen stream
Measure it is too low, transparency conducting layer oxidation it is insufficient, film quality is bad, oxygen flow be greater than 20sccm when, oxygen flow is too big, thoroughly
Bright conductive layer excessive oxidation, film layer defect concentration increase.When evaporation time is less than 100min, film needs higher deposition rate
It can be only achieved required thickness, deposition rate is too fast, and atom has little time to migrate, therefore film growth quality is poor, and defect is more.It is preferred that
, vapor deposition temperature is 290 DEG C, oxygen flow 10sccm, and vapor deposition chamber vacuum degree is 3.0*10-5-10.0*10-5。
Wherein, the material of the transparency conducting layer is indium tin oxide, but not limited to this.Indium and tin in indium tin oxide
Ratio is 70-99:1-30.Preferably, the ratio of indium and tin is 95:5 in indium tin oxide.Transparency conducting layer is favorably improved in this way
Conductive capability, prevent carrier from flocking together, also improve chip light extraction efficiency.
Using photoresist or SiO2As exposure mask, by electron beam evaporation plating or magnetron sputtering depositing operation, described transparent
The surface of conductive layer is sequentially depositing to form reflecting layer and metal barrier.Reflecting layer is made of Ag.In other implementations of the application
In example, the reflecting layer further includes one or more of Ti, W, N and Ni metal, in reflecting layer other than containing Ag metal
The middle above-mentioned element of addition can not only improve the luminous reflectanc in reflecting layer, and can also lower the transfer ability of Ag.The metal
Barrier layer is made of one or more of Ti, W, Pd, Rh, Pt and Al.
Wherein, the metal barrier is covered on the surface and two sides in the reflecting layer, and extends in electrically conducting transparent
The two sides of layer effectively prevent the anti-raw migration of the metal in reflecting layer and transparency conducting layer, guarantee the reflectivity in reflecting layer and avoid
Short circuit occurs for chip.
S205: the first passivation layer is formed on the LED first product；
Using chemical vapor deposition process or physical gas-phase deposition, it is blunt that first is formed on the surface of the LED first product
Change layer.Wherein, first passivation layer is covered on the surface of the first semiconductor layer of exposed region, and is covered on metal barrier
Surface and side on, and extend on the side of active layer.First passivation layer is for protecting LED first product, so that first
Electrode and second electrode mutually insulated avoid chip that short circuit occurs.Preferably, first passivation layer is by SiO2And Si3N4System
At.In the other embodiments of the application, first passivation layer can also be electrically insulated material composition by other.
S206: performing etching first passivation layer, forms third hole and the quarter being etched on the first semiconductor layer
It loses to the 4th hole on metal barrier.
The first passivation layer metal is carved using electric induction coupled plasma dry etch process wet-etching technology
Erosion forms through the first passivation layer and is etched to the third hole of the first semiconductor layer surface, is formed through the first passivation layer simultaneously
It is etched to the 4th hole of metal barrier layer surface.
S207: the deposited metal in the first passivation layer surface and third hole forms first electrode, sinks in the 4th hole
Product metal, forms second electrode.
Gold is deposited in the first passivation layer surface and third hole using electron beam evaporation plating, hot evaporation or magnetron sputtering technique
Category forms first electrode, forms second electrode in the 4th inner hole deposition product metal.In order to enable the current distribution of chip is more uniform,
The flow path of electric current is shortened, convenient for first electrode extraction is conductively connected with the first pad, the first electrode setting
The first passivation layer default surface and extend in third hole, be electrically connected with the first semiconductor layer.Existing first electrode
It is directly formed in the first semiconductor layer, when flip-chip to be welded on substrate, the pad needs connecting with first electrode are passed through
Multilayered structure is worn, first electrode could be extracted.Alternatively, increasing the thickness of first electrode, directly first electrode is exposed
Come, still, will increase the cost of chip in this way and increase the voltage of chip, and first electrode is easy to be in contact with other structures
And generate short circuit.
Wherein, area of the area of the first electrode on the first passivation layer less than the first passivation layer, and first electrode
With second electrode mutually insulated.Preferably, the first electrode on the first passivation layer is equal with the height of second electrode, in this way
It is connected convenient for subsequent formed with the first pad and the second pad.
The first electrode and second electrode are by several made of metal of one of Cr, Al, Ti, Pt, Au, Ni, Ag and W
At.
S102: the second passivation layer and the first bonded layer are formed in LED wafer.
Using chemical vapor deposition process or physical gas-phase deposition, it is blunt that second is formed on the surface of the LED wafer
Change layer.Preferably, second passivation layer is by SiO2And Si3N4It is made.In the other embodiments of the application, described second is blunt
Changing layer can also be electrically insulated material composition by other.
It deposits to form the first bonded layer in second passivation layer surface using vacuum metal deposition technology.Preferably, institute
The first bonded layer is stated to be made of one or both of Au and Sn metal.
Wherein, second passivation layer is covered on first electrode, second electrode and the first passivation layer surface, the second passivation layer
Further first electrode and second electrode are insulated, first electrode and second electrode is prevented to be electrically connected；Secondly, second
Passivation layer is also used to insulate at electrode and the first bonded layer, so that the first bonded layer can be formed in LED wafer.
S103: silicon base is provided, the second bonded layer is formed on.
It deposits to form the second bonded layer in silicon substrate surface using vacuum metal deposition technology.Wherein, second bonded layer
Material and the first bonded layer are identical or different.
Preferably, the area of the silicon base is equal to the area of substrate, and the silicon base is non-conductive silicon wafer.Using face
The big non-conductive silicon wafer such as product, in order to provide enough support forces to LED wafer in subsequent removal substrate.
S104: the first bonded layer is bonded with the second bonded layer, forms LED semi-finished product.
The first bonded layer will be bonded using vacuum hotpressing bonding techniques with the second bonded layer, silicon base setting will be existed
In LED wafer, LED semi-finished product are formed.
Thermocompression bonding technology is that the materials such as gold, tin, gallium is made to become melting state by heating method, then passes through pressurization side
Formula makes to be bonded between material, cools down later, thus different substrates is bonded together, and adhesive surface is more uniform, simple process,
Convenient for operation.
Wherein, thermocompression bonding temperature is 200-300 DEG C, and thermocompression bonding pressure is 300-2000kg/m2.Thermocompression bonding temperature
When less than 200 DEG C, material is difficult to melt completely, influences bonding effect；When thermocompression bonding temperature is greater than 300 DEG C, temperature is excessively high, breaks
The structure of bad LED wafer, influences illumination effect.Thermocompression bonding pressure is less than 300kg/m2When, it bonds between material not close, glues
Conjunction face is unevenly smooth；Thermocompression bonding pressure is greater than 2000kg/m2When, it needs to purchase additional equipment, increases cost.
S105: performing etching the LED semi-finished product, forms the first hole for being etched to first electrode surface and is etched to
Second hole of second electrode surface.
In order to which the etching depth of the first hole and the second hole is identical, workload is reduced, shortens etch period, the first hole
The top in reflecting layer is respectively positioned on the second hole.
It for the ease of etching, reduces and forms the material of pad, the diameter upper right of the first hole and the second hole is successively decreased down.
Referring to Fig. 5, the LED semi-finished product are performed etching, comprising the following steps:
S301: the silicon base is performed etching using dry etch process, the second bonding layer surface is etched to, first
The first hole is formed above electrode, it is rectangular at the second hole on the second electrode.
The silicon base is performed etching using inductively coupled plasma dry etch process, in the top of first electrode
It is formed and runs through the silicon base, and be etched to the first hole of the second bonding layer surface, formed and run through in the top of second electrode
The silicon base, and it is etched to the second hole of the second bonding layer surface.
S302: using wet-etching technology in the first hole and the second hole the second bonded layer and the first bonded layer into
Row etching, so that the first hole and the second hole are etched to the second passivation layer respectively.
Wet etching is carried out using the etching liquid made of one or more of KI, HCl and chloroazotic acid solution, to the first hole
The second bonded layer in hole and the second hole and the etching of the first bonded layer, so that the first hole and the second hole are extended through to the
The surface of two passivation layers.
S303: the second passivation layer in the first hole and the second hole is carved using dry or wet etch technique
Erosion, so that the first hole is etched to first electrode surface, the second hole is etched to second electrode surface.
Wherein, wet-etching technology is performed etching using HF etching solution, to second in the first hole and the second hole
Passivation layer performs etching, so that the first hole is through to first electrode surface, the second hole is through to second electrode surface.It is preferred that
, the diameter of the first hole and the second hole successively decreases from top to bottom.
LED semi-finished product are once etched by dry or wet etch technique with existing, direct etching to first
Electrode is compared with the lithographic method of second electrode, and the application is etched by carrying out classification three times to the first hole and the second hole,
It can be directed to different structures and the lithographic method different at component selections, improve the yield of etching, reduce the damage to each layer structure
Wound；Secondly, the diameter etched every time can be controlled so that the diameter of the first hole and the second hole from top to bottom into
Row successively decreases.
S106: third passivation layer is formed in the side wall of the surface of silicon base, the first hole and the second hole.
Using chemical vapor deposition process or physical gas-phase deposition, in the surface of the silicon base, the first hole
With deposition third passivation layer in the second hole, then the first hole and the second hole are performed etching, by first electrode and second
Electrode exposes, thus the side wall of the first hole and the second hole formed third passivation layer, for protect the first pad and
Second pad, by the first pad and the second pads insulated.Preferably, the third passivation layer is by SiO2And Si3N4It is made.At this
In the other embodiments of application, the third passivation layer can also be electrically insulated material composition by other.
S107: depositing one layer of metal in the first hole and the second hole, forms the first pad and the second pad.
First pad is formed in the first hole deposited metal using electron beam evaporation plating, hot evaporation or magnetron sputtering technique,
Deposited metal forms the second pad in second hole.First pad is electrically connected with first electrode, the second pad and second electrode electricity
Connection, and the first pad and the second pad mutually insulated.Preferably, the first pad is arranged on the second predeterminable area of silicon base
And extend in the first hole, the second pad is arranged on the third predeterminable area of silicon base and extends in the second hole.The
The area equation of one pad and the second pad.
First pad is made of one or both of Au and Sn metal, the material of the second pad and the first pad phase
It is same or different.
S108: substrate is removed.
Above disclosed is only a kind of preferred embodiment of the utility model, certainly cannot be practical to limit with this
Novel interest field, therefore equivalent variations made according to the claim of the utility model still belong to what the utility model was covered
Range.
Claims (9)
1. a kind of film flip LED chips characterized by comprising
LED wafer, the LED wafer include the first semiconductor layer, are sequentially arranged in active layer on the first semiconductor layer, the second half
Conductor layer, reflecting layer and the first passivation layer set on the first passivation layer surface and extend to first electrode on the first semiconductor layer,
Through the first passivation layer and the second electrode on reflecting layer is set, first electrode and second electrode mutually insulated；
The second passivation layer, the first bonded layer, the second bonded layer and the silicon base being sequentially arranged in LED wafer；
First pad, first pad run through silicon base, the second bonded layer, the first bonded layer and the second passivation layer, and with the
The connection of one electrodes conduct；
Second pad, second pad run through silicon base, the second bonded layer, the first bonded layer and the second passivation layer, and with the
The connection of two electrodes conducts；
The third passivation layer of silicon substrate surface, the first pad and the second pad side wall is set.
2. film flip LED chips according to claim 1, which is characterized in that the diameter of the first pad and the second pad
Upper right is successively decreased down.
3. film flip LED chips according to claim 1, which is characterized in that the first electricity on the first passivation layer
Pole is equal with the height of second electrode.
4. film flip LED chips according to claim 1, which is characterized in that the first electricity on the first passivation layer
Area of the area of pole less than the first passivation layer.
5. film flip LED chips according to claim 1, which is characterized in that the LED wafer further includes being set to second
Transparency conducting layer between semiconductor layer and reflecting layer.
6. film flip LED chips according to claim 5, which is characterized in that the LED wafer further includes being set to reflection
Metal barrier on layer.
7. film flip LED chips according to claim 6, which is characterized in that metal barrier is covered on the reflection
The surface and two sides of layer, and extend in the two sides of transparency conducting layer.
8. film flip LED chips according to claim 1, which is characterized in that the area of the silicon base is equal to substrate
Area.
9. film flip LED chips according to claim 1, which is characterized in that the silicon base is non-conductive silicon wafer.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108470812A (en) * | 2018-06-04 | 2018-08-31 | 佛山市国星半导体技术有限公司 | A kind of film flip LED chips and preparation method thereof |
| CN110600592A (en) * | 2019-10-11 | 2019-12-20 | 佛山市国星半导体技术有限公司 | Flip LED chip and manufacturing method thereof |
| CN114883469A (en) * | 2022-07-07 | 2022-08-09 | 华灿光电（浙江）有限公司 | Light emitting diode chip for improving current conduction and preparation method thereof |
| CN115832128A (en) * | 2023-02-16 | 2023-03-21 | 江西兆驰半导体有限公司 | Preparation method of LED chip |
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2018
- 2018-06-04 CN CN201820853430.1U patent/CN208400877U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108470812A (en) * | 2018-06-04 | 2018-08-31 | 佛山市国星半导体技术有限公司 | A kind of film flip LED chips and preparation method thereof |
| CN108470812B (en) * | 2018-06-04 | 2024-07-12 | 佛山市国星半导体技术有限公司 | Thin film flip LED chip and manufacturing method thereof |
| CN110600592A (en) * | 2019-10-11 | 2019-12-20 | 佛山市国星半导体技术有限公司 | Flip LED chip and manufacturing method thereof |
| CN114883469A (en) * | 2022-07-07 | 2022-08-09 | 华灿光电（浙江）有限公司 | Light emitting diode chip for improving current conduction and preparation method thereof |
| CN114883469B (en) * | 2022-07-07 | 2022-11-29 | 华灿光电（浙江）有限公司 | Light emitting diode chip for improving current conduction and preparation method thereof |
| CN115832128A (en) * | 2023-02-16 | 2023-03-21 | 江西兆驰半导体有限公司 | Preparation method of LED chip |
| CN115832128B (en) * | 2023-02-16 | 2024-03-12 | 江西兆驰半导体有限公司 | Preparation method of LED chip |
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