CN208314762U - The I/O extension of CPLD a kind of and server master board and electronic product based on it - Google Patents
The I/O extension of CPLD a kind of and server master board and electronic product based on it Download PDFInfo
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- CN208314762U CN208314762U CN201821003582.9U CN201821003582U CN208314762U CN 208314762 U CN208314762 U CN 208314762U CN 201821003582 U CN201821003582 U CN 201821003582U CN 208314762 U CN208314762 U CN 208314762U
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Abstract
This application discloses the I/O extension of CPLD a kind of and based on its server master board and electronic product, the I/O extension mainly include it is multiple extend out chip using what plural serial stage mode connected, and any extend out the expansible N number of I/O pin of chip；The input terminal that the first order extends out chip is used to acquire the input terminal connection that N number of first serial input signals, output end and the second level extend out chip；The input terminal that the second level extends out chip is also used to acquire N number of second serial input signals；The input terminal of output end and CPLD that afterbody extends out chip connects；The CLK signal output end and SHIFT_LOAD_CONTROL signal output end of CPLD is connect with multiple input terminals for extending out chip respectively.The IO quantity of CPLD can be greatly increased, is conducive to reduce the entire occupied space of CPLD chip in the case where occupying seldom CPLD pin by the I/O extension in the application, to be conducive to space utilization and the resource optimization of equipment where CPLD.
Description
Technical field
This application involves server master board design fields, more particularly to the I/O extension and base of a kind of CPLD
In its server master board and electronic product.
Background technique
CPLD (Complex Programmable Logic Device, Complex Programmable Logic Devices) chip is service
Important component on device mainboard, traditional server realize switching on and shutting down timing control by the CPLD chip on server master board
And the monitoring to key logic signal.In the server of a new generation, since server supports PFR (Platform Firmware
Resilience, platform firmware restore) function, need to realize the content authentication of main control chip FW by CPLD chip,
It is exactly that, when the FW information in flash is tampered, can be restored by the hardware access and advanced algorithm of CPLD.In order to
The server for matching a new generation needs CPLD chip to provide greater number of CPLD IO.
Currently, the CPLD chip comprising more logical resources is usually selected in order to increase the quantity of I/O pin, at present
CPLD solution is concentrated mainly on Intel Max series, Lattice XO3 series and Microsemi etc., and resource extent is about
It, can be with IO quantity at 200~300 in 2K LUTs.It, should by taking existing mainboard Lattice CPLD logic control chip as an example
CPLD chip shares 256 IO, and for realizing functions such as timing control, error monitoring and fan control, logical resource includes
2K LUTs.While carrying out IO expansion to CPLD chip, it will lead to and correspondingly expand its logical resource.The CPLD external connection
Each group VR controls chip and CPU/PCH (Platform Controller Hub, platform courses center) key signal, the CPLD
It is additionally coupled to the communication link of BMC, for realizing the reading of CPLD version and remote reflash function.
However, in current CPLD chip structure, since I/O pin quantity being upshiftd on the basis of original CPLD chip
To 200-300, the I/O pin quantity directly connecting with CPLD is too many, so that the occupied mainboard plate face area of CPLD chip is too
Greatly, be unfavorable for server master board space make full use of and resource optimization.
Summary of the invention
This application provides the I/O extension of CPLD a kind of and based on its server master board and electronic product, with solution
CPLD chip occupancy mainboard plate face area certainly in the prior art is too big, is unfavorable for making full use of and providing for server master board space
The problem of source optimization.
In order to solve the above-mentioned technical problem, the embodiment of the present application discloses following technical solution:
A kind of I/O extension of CPLD, the I/O extension include: it is multiple connected using plural serial stage mode it is outer
Expand chip, and any expansible N number of I/O pin of chip, N >=2 and N of extending out is natural number；
It is multiple to extend out the first order in chip and extend out the input terminal of chip for acquiring N number of first serial input signals, it is described
The output end that the first order extends out chip is connect with the input terminal that the second level extends out chip；
The input terminal that the second level extends out chip is also used to acquire N number of second serial input signals；
Multiple input terminals for extending out output end and CPLD that afterbody in chip extends out chip connect；
The CLK signal output end of the CPLD is connect with multiple input terminals for extending out chip respectively, for extend out chip
Sample frequency is provided；
The SHIFT_LOAD_CONTROL signal output end of the CPLD is connect with multiple input terminals for extending out chip respectively,
For providing control signal to extend out chip.
Optionally, the chip that extends out is to turn serial logic chip parallel.
Optionally, the model for turning serial logic chip parallel are as follows: 74HC165PW.
Optionally, I/O pin quantity N≤8.
Optionally, the sample frequency for extending out chip is equal with the clock frequency of CPLD, and the clock frequency of CPLD≤
15MHz。
A kind of server master board based on I/O extension is provided in the CPLD of the server master board above-described
I/O extension.
A kind of electronic product based on I/O extension is provided with above-described IO in the CPLD of the electronic product and expands
Extending apparatus.
Optionally, the electronic product includes: PC machine, mobile phone and interchanger.
The technical solution that embodiments herein provides can include the following benefits:
The application provides the I/O extension of CPLD a kind of, which includes that multiple use plural serial stage modes connect
What is connect extends out chip, and any extends out the expansible N number of I/O pin of chip.It is multiple to extend out the first order in chip and extend out the defeated of chip
Enter end and extends out the input of chip with the second level for acquiring N number of first serial input signals, the output end that the first order extends out chip
End connection, and the second level extends out the input terminal of chip and is also used to acquire N number of second serial input signals, it is multiple to extend out in chip most
Rear stage extend out chip output end and CPLD input terminal connect, CPLD to it is multiple extend out chip output CLK signal and
SHIFT_LOAD_CONTROL signal is respectively used to extend out chip and providing sample frequency and control signal.CPLD in the application
I/O extension, in multiple connection types for extending out chip, by the way of chip plural serial stage, so that previous stage extends out
The serial signal of chip output extends out the input signal of chip as rear stage, and final only afterbody extends out the output of chip
End is connected to a pin of CPLD, therefore, in the case where occupying seldom CPLD pin, can greatly increase the IO of CPLD
Quantity is conducive to reduce the entire occupied space of CPLD chip, to be conducive to the space utilization and money of equipment where CPLD
Source optimization.
The application also provides a kind of server master board based on I/O extension, is provided in the CPLD of the server master board
Above-described I/O extension.Since the I/O extension is by the way of chip plural serial stage, and each extend out chip energy
2-8 I/O pin is enough extended, the output end that only afterbody extends out chip is connected to a pin of CPLD.Therefore, this Shen
In server master board structure please, in the case where occupying seldom CPLD pin, the IO quantity of CPLD can be greatly increased, from
And support the PFR function of server, and the occupied server master board plate face area of CPLD chip is greatly reduced, favorably
In server master board space make full use of and resource optimization.
The application also provides a kind of electronic product based on I/O extension, is provided in the CPLD chip of the electronic product
Above-described I/O extension.Since the I/O extension is by the way of chip plural serial stage, and each extend out chip energy
2-8 I/O pin is enough extended, the output end that only afterbody extends out chip is connected to a pin of CPLD.Therefore, this Shen
I/O extension used by electronic product please can greatly increase CPLD in the case where occupying seldom CPLD pin
IO quantity, be conducive to resource optimization, and improve the space utilization rate of electronic product.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The application can be limited.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without creative efforts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of the I/O extension of CPLD provided by the embodiment of the present application.
Specific embodiment
In order to make those skilled in the art better understand the technical solutions in the application, below in conjunction with the application reality
The attached drawing in example is applied, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described implementation
Example is merely a part but not all of the embodiments of the present application.Based on the embodiment in the application, this field is common
The application protection all should belong in technical staff's every other embodiment obtained without making creative work
Range.
The application in order to better understand explains in detail presently filed embodiment with reference to the accompanying drawing.
Referring to Fig. 1, Fig. 1 is a kind of structural schematic diagram of the I/O extension of CPLD provided by the embodiment of the present application.By
Fig. 1 it is found that the I/O extension in the present embodiment mainly include it is multiple be sequentially connected in series extend out chip, and any extend out core
The expansible N number of I/O pin of piece, wherein N >=2 and N are natural number.That is, multiple in the present embodiment extend out between chip
Connection type are as follows: chip plural serial stage, previous stage extend out chip output serial signal extend out the defeated of chip as rear stage
Enter signal.
It is multiple to extend out the first order in chip to extend out the input terminal of chip serial defeated for acquiring N number of first in the present embodiment
Enter signal, the output end that the first order extends out chip is connect with the input terminal that the second level extends out chip；The second level extends out the defeated of chip
Enter end and is also used to acquire N number of second serial input signals；It is multiple extend out afterbody in chip extend out the output end of chip with
The input terminal of CPLD connects；The CLK signal output end of CPLD is connect with multiple input terminals for extending out chip respectively, for extend out
Chip provides sample frequency；The SHIFT_LOAD_CONTROL signal output end of CPLD respectively with multiple input terminals for extending out chip
Connection, for providing control signal to extend out chip.
Chip is extended out it is found that defining and sharing M in the present embodiment in conjunction with Fig. 1, comprising: IO EXPANDER_1, IO
EXPANDER_2 ... and IO EXPANDER_M, and this M extend out chip and are sequentially connected in series.The first order extends out chip
IO EXPANDER_1, IO EXPANDER_1 is for acquiring N number of first serial input signals；It is IO that the second level, which extends out chip,
EXPANDER_2, IO EXPANDER_2 are for acquiring N number of second serial input signals；And so on, m-th extends out chip and is
IO EXPANDER_M, IO EXPANDER_M is for acquiring N number of M serial input signals.Wherein m-th extends out chip I/O
EXPANDER_M is that afterbody extends out chip, and the input terminal of IO EXPANDER_M connects N number of M serial input signals and outer
Expand the output end of chip I/O EXPANDER_M-1, the output end of IO EXPANDER_M is connected to the input terminal of CPLD, therefore, should
I/O extension only passes through the pin that IO EXPANDER_M occupies CPLD, so that it may collect multiple signal conditions.
CPLD exports CLK signal, i.e. clock signal to multiple chips that extend out respectively in the present embodiment.Pass through control CPLD's
Output clock frequency can guarantee the sample frequency for extending out chip, so that it is guaranteed that various frequencies can be collected in time by extending out chip
The signal of rate, especially certain signals for needing CPLD quick response, by improving the output clock frequency of CPLD, to improve
The sample frequency of chip is extended out, and then useful signal edge can be collected in time.
Further, in the I/O extension structure of the present embodiment, the sample frequency of chip and the clock frequency of CPLD are extended out
Rate is equal, and clock frequency≤15MHz of CPLD.The maximum output clock frequency of CPLD is determined by extending out chip in the present embodiment
It is fixed, if the frequency acquisition for extending out chip is too high, extend out chip can not normal response CPLD clock signal, also just can not be normal
Work.Turn serial logic chip parallel according to employed in the present embodiment, the clock frequency of CPLD preferably≤15MHz, this when
Clock frequency had both been able to satisfy the sample requirement for extending out chip, it is ensured that collects the signal of various frequencies, and it is too high to be unlikely to frequency, leads
Cause, which extends out chip, cannot respond to CPLD.In practical applications, it is also necessary to which consideration extends out chip institute can collected signal intensity feelings
Condition can not collect some fast-changing signals, extend out the lowest frequency of chip if the frequency acquisition for extending out chip is not high enough
Rate value determines that its required signal condition acquired of different practical applications is different according to the practical application of I/O extension,
Therefore, CPLD is not also identical to the clock frequency that chip is exported is extended out.
CPLD also exports SHIFT_LOAD_CONTROL signal to multiple chips that extend out respectively in the present embodiment, for for
A chip that extends out provides control signal.
Further, in this embodiment extending out chip using serial logic chip is turned parallel, this kind of logic chips can
Response external clock signal controls signal by receiving, and multiple signals deposit of one acquisition is turned string parallel with certain frequency
Row inside logic chip register, and give to parallel and turn serial logic chip output.That is, the IO in the present embodiment expands
The parallel input of multiple IO is converted to serial data bit stream by turning serial logic chip parallel by extending apparatus, that is, by one
N number of serial signal deposit of secondary acquisition extends out the internal register of chip, and is transmitted to the output end for extending out chip.Wherein, N number of
Between serial signal be concurrency relation, be transmitted to extend out the output end of chip signal be serial signal, multistage extend out chip it
Between data are transmitted by serial signal line.
The serial logic chip that turns parallel in the present embodiment can be using the chip of model 74HC165PW.74HC165PW
74HC165 is provided in chip, 74HC165 is the shift register that 8 bit synchronizations input parallel, asynchronous serial exports, can be at end
Grade obtains the serial output signal stream of extended chip combinations at different levels, is passed so that multistage be realized to extend out between chip by serial signal
Data are sent, and then realize the extension of multiple IO.
The value range of N in the present embodiment are as follows: N≤8, that is, any extend out the expansible 2-8 I/O pin of chip.
In conclusion in the I/O extension of the present embodiment CPLD, it is multiple to extend out the company that plural serial stage is used between chip
Mode is connect, it is multiple to extend out by serial signal transfer data between chip, and previous stage extends out the serial signal work of chip output
The input signal of chip is extended out for rear stage, the output end that afterbody extends out chip final only be connected to CPLD one draws
Foot can greatly reduce the occupied sky of CPLD therefore it may only be necessary to which multiple signals can be acquired by occupying a pin of CPLD
Between and resource, increase CPLD IO quantity on the basis of, be conducive to improve CPLD where equipment space utilization rate and resource
Optimization rate.It moreover, the I/O extension structure in the application is simple, not will increase the stack-designs such as PCB, can be avoided to increase yet
Add the quantity of I/O pin and select the case where possessing the CPLD of more logical resource, advantageously reduces power consumption and save the cost.By
In the application while increasing I/O pin, the increase of corresponding logical resource not will cause, therefore, the application is applicable in very much
It is more in IO demand, while the application scenarios of logical resource abundance.
The application also provides a kind of server master board based on I/O extension, sets in the CPLD chip of the server master board
The I/O extension being equipped in embodiment illustrated in fig. 1.
Since in the server master board of the application, I/O extension is extended out by the way of chip plural serial stage, and each
Chip can extend multiple I/O pins, and the output end that only afterbody extends out chip is connected to a pin of CPLD.Therefore,
In the server master board structure of the application, in the case where occupying seldom CPLD pin, the IO number of CPLD can be greatly increased
Amount, to support the PFR function of server.Moreover, because only taking up seldom CPLD pin in the server master board structure, make
It obtains the entire occupied server master board plate face area of CPLD chip to greatly reduce, is conducive to the abundant benefit in server master board space
With and resource optimization.
The application also provides a kind of electronic product based on I/O extension, is arranged in the CPLD chip in the electronic product
There is the I/O extension in embodiment illustrated in fig. 1.Wherein, electronic product includes PC machine, mobile phone and interchanger etc..
Since in the electronic product of the application, I/O extension each extends out core by the way of chip plural serial stage
Piece can extend 2-8 I/O pin, and the output end that only afterbody extends out chip is connected to a pin of CPLD.Therefore,
I/O extension used by the electronic product of the application can be greatly increased in the case where occupying seldom CPLD pin
The IO quantity of CPLD is conducive to resource optimization, and improves the space utilization rate of electronic product.
The above is only the specific embodiment of the application, is made skilled artisans appreciate that or realizing this Shen
Please.Various modifications to these embodiments will be apparent to one skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of I/O extension of CPLD, which is characterized in that the I/O extension includes: multiple using plural serial stage mode
Connection extends out chip, and any expansible N number of I/O pin of chip, N >=2 and N of extending out is natural number；
It is multiple to extend out the first order in chip and extend out the input terminal of chip for acquiring N number of first serial input signals, described first
The output end that grade extends out chip is connect with the input terminal that the second level extends out chip；
The input terminal that the second level extends out chip is also used to acquire N number of second serial input signals；
Multiple input terminals for extending out output end and CPLD that afterbody in chip extends out chip connect；
The CLK signal output end of the CPLD is connect with multiple input terminals for extending out chip respectively, for providing to extend out chip
Sample frequency；
The SHIFT_LOAD_CONTROL signal output end of the CPLD is connect with multiple input terminals for extending out chip respectively, is used for
Control signal is provided to extend out chip.
2. the I/O extension of CPLD according to claim 1 a kind of, which is characterized in that the chip that extends out is parallel turns
Serial logic chip.
3. the I/O extension of CPLD according to claim 2 a kind of, which is characterized in that described to turn serial logic core parallel
The model of piece are as follows: 74HC165PW.
4. the I/O extension of CPLD according to claim 1 a kind of, which is characterized in that I/O pin quantity N≤8.
5. the I/O extension of CPLD according to claim 1 a kind of, which is characterized in that the sampling frequency for extending out chip
Rate is equal with the clock frequency of CPLD, and clock frequency≤15MHz of CPLD.
6. a kind of server master board based on I/O extension, which is characterized in that be provided in the CPLD of the server master board
I/O extension described in any one of claim 1-5.
7. a kind of electronic product based on I/O extension, which is characterized in that setting is had the right in the CPLD of the electronic product
It is required that I/O extension described in any one of 1-5.
8. a kind of electronic product based on I/O extension according to claim 7, which is characterized in that the electronic product
It includes: PC machine, mobile phone and interchanger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821003582.9U CN208314762U (en) | 2018-06-27 | 2018-06-27 | The I/O extension of CPLD a kind of and server master board and electronic product based on it |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821003582.9U CN208314762U (en) | 2018-06-27 | 2018-06-27 | The I/O extension of CPLD a kind of and server master board and electronic product based on it |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110687997A (en) * | 2019-09-06 | 2020-01-14 | 苏州浪潮智能科技有限公司 | Method and device for dynamically adjusting power consumption of FPGA |
| CN110990231A (en) * | 2019-11-08 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Display assembly, mainboard and server of CPLD version |
| CN111124974A (en) * | 2019-12-25 | 2020-05-08 | 西安易朴通讯技术有限公司 | Interface expansion device and method |
| CN113204804A (en) * | 2021-04-25 | 2021-08-03 | 山东英信计算机技术有限公司 | Security module, server mainboard and server |
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2018
- 2018-06-27 CN CN201821003582.9U patent/CN208314762U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110687997A (en) * | 2019-09-06 | 2020-01-14 | 苏州浪潮智能科技有限公司 | Method and device for dynamically adjusting power consumption of FPGA |
| CN110687997B (en) * | 2019-09-06 | 2021-06-11 | 苏州浪潮智能科技有限公司 | Method and device for dynamically adjusting power consumption of FPGA |
| CN110990231A (en) * | 2019-11-08 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Display assembly, mainboard and server of CPLD version |
| CN111124974A (en) * | 2019-12-25 | 2020-05-08 | 西安易朴通讯技术有限公司 | Interface expansion device and method |
| CN111124974B (en) * | 2019-12-25 | 2024-01-26 | 西安易朴通讯技术有限公司 | Interface expanding device and method |
| CN113204804A (en) * | 2021-04-25 | 2021-08-03 | 山东英信计算机技术有限公司 | Security module, server mainboard and server |
| CN113204804B (en) * | 2021-04-25 | 2022-03-22 | 山东英信计算机技术有限公司 | Security module, server mainboard and server |
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