CN208272972U - A kind of single wire communication circuit - Google Patents
A kind of single wire communication circuit Download PDFInfo
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- CN208272972U CN208272972U CN201820810045.9U CN201820810045U CN208272972U CN 208272972 U CN208272972 U CN 208272972U CN 201820810045 U CN201820810045 U CN 201820810045U CN 208272972 U CN208272972 U CN 208272972U
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Abstract
A kind of single wire communication circuit, the single wire communication circuit includes signal processing circuit, the signal processing circuit is for receiving and handling external pulse signal CLK1, then corresponding data position DATA is exported, and generate synchronous triggering signal of the synchronization signal CLK2 as subsequent conditioning circuit, use an input signal transmission line, just the communication of intermodule can be realized by time-multiplexed mode, simultaneously in the case where no clock transfer line, the synchronization signal by data is generated using signal of communication, to trigger the transmission and storage that single line communication system carries out data bit, to reduce the call format of signal of communication and the clock frequency requirement of transmitting-receiving side, improve communication efficiency and quality.The single wire communication circuit is also particularly suitable for prime and is the communication system of wireless communication module, and the structural complexity and cost of wireless communication module can be effectively reduced.
Description
Technical field
The utility model relates to field of communication technology, in particular to a kind of single wire communication circuit.
Background technique
With the continuous development of science and technology, communication becomes indispensable function between distinct device or module.Presently, there are
Primary communication mode be wire communication and wireless communication, difference be whether signal sending end and receiving end have signal wire company
Connect, for wireless communication, structure is complicated for circuit module, also need to complete signal using antenna to send and receive, cost compared with
Height, and vulnerable to environmental disturbances.In fact, wireless communication physical layer can be evolved into single line communication, it finally also can be by wirelessly sending out
It penetrates and converts a signal into wire communication with receiving module.Traditional wired communication mode mainly has serial communication and parallel communications,
Wherein parallel communications can realize the different positions of the data one-to-one synchronous transfer between different port, therefore efficiency of transmission is higher,
But parallel communications will cause greatly increasing for cost when carrying out telecommunication or long numeric data communicates；When serial communication removes
It outside clock line and ground wire, is only communicated by a transmission line, it supports the successively transmission of data bit, and cost is relatively low.
Serial communication is there are two kinds of communication modes of serial asynchronous communication and distant serial synchronous telecommunications, wherein serial asynchronous communication
Sending and receiving end needs a transmission line and a ground wire connection, and distant serial synchronous telecommunications need a transmission line, a clock line
It is connected with a ground wire.For serial asynchronous communication, since sending and receiving end does not connect clock line, the clock of transmitting terminal and receiving end
Signal disunity, therefore communication system is more demanding to the clock signal of recipient.Serial asynchronous communication only allows once to send
One data, and the data bit transmitted is limited, also needs to increase additional information bit, carries out big data according to serial asynchronous communication
Amount transmission, not only transmission rate is low, communication efficiency with communicate correctness also and can decline.For distant serial synchronous telecommunications, due to transmitting-receiving
There are clock line connection, transmitting terminal and receiving end clock signal synchronization in end, therefore can realize and once transmit multiple data, efficiency of transmission
High and correctness is high, but due to that need to transmit clock signal toward contact while transmitting terminal sends signal, leads to the structure of transceiver
Complexity, cost increase.
Summary of the invention
The purpose of this utility model is that in view of the above-mentioned drawbacks in the prior art, provide a kind of single line communication method and its
Circuit realizes the efficient communication of intermodule on the basis of transmission line is few, cost is relatively low and circuit structure is simple.
For achieving the above object, the utility model adopts the technical scheme that a kind of single wire communication circuit, described
Single wire communication circuit includes signal processing circuit, and the signal processing circuit is used to receiving and handling external pulse signal CLK1,
Then corresponding data position DATA is exported, and generation is believed by the synchronization signal CLK2 of data bit as the synchronous triggering of subsequent conditioning circuit
Number.The single wire communication circuit includes signal processing circuit, and the signal processing circuit is for receiving and handling external pulse letter
Then number CLK1 exports corresponding data position DATA, and generates synchronous triggering signal of the synchronization signal CLK2 as subsequent conditioning circuit,
In each data bit DATA establish a capital the CLK1 signal for needing at least one number of pulses really, and each synchronization signal CLK2 by
First pulse in pulse signal CLK1 generates.For the correct identification for guaranteeing signal of communication, from inputting the pulse signal
CLK1 to the time for generating the synchronization signal CLK2 should be greater than the input pulse CLK1 middle arteries and go out now to arrive end-of-pulsing
Total time, i.e. t1> TPulsei, i=1,2,3,4；Before the synchronization signal CLK2 should appear in the second group pulse signal, i.e. Ti (i=
1,2,3) > t2。
In addition, the utility model also proposes following attached technical scheme: the signal processing circuit includes interconnected
Edging trigger circuit and delay circuit, input pulse CLK1 obtains data bit DATA after the triggering is along processing of circuit, described
Reset signal of the reset signal RST1 as edging trigger circuit that delay circuit generates, the edging trigger circuit pass through described in prolong
When trigger signal of the synchronization signal CLK2 as subsequent conditioning circuit that generates of circuit.
The edging trigger circuit is chosen as d type flip flop 1 and d type flip flop 2 interconnected, the d type flip flop 1 and D touching
It sends out device 2 and external signal is received by a signal line, the D input terminal of the d type flip flop 1 is supply voltage VDD, the D triggering
The D input terminal of device 2 is the Q output of d type flip flop 1.
The edging trigger circuit is to distinguish single pulse signal and multipulse signal, the d type flip flop 1 and D touching
It sends out device 2 and the input pulse CLK1 is converted into low and high level.
The edging trigger circuit is also chosen as d type flip flop 3 and d type flip flop 4 interconnected, the d type flip flop 3 and D
Trigger 4 receives external signal by a signal line, and the D input terminal of the d type flip flop 3 is supply voltage VDD, the D touching
The D input terminal for sending out device 4 is the QB output end of d type flip flop 4.
The edging trigger circuit is to distinguish odd number pulse signal and even number pulse signal, 3 He of d type flip flop
The input pulse CLK1 is converted to low and high level by the d type flip flop 4.
The single wire communication circuit further includes data storage and output circuit, data storage with described in output circuit warp
Synchronization signal CLK2 triggering, for depositing the output result DATA of the signal processing circuit, after a data are transmitted,
The data storage and output circuit export the data parallel of deposit, use to subsequent module.
The data storage and output circuit include shift register and counter interconnected, the edging trigger electricity
Road is connect with the shift register, and the delay circuit is connect with the shift register and the counter respectively.
The shift register is triggered by the synchronization signal CLK2, by the data of the edging trigger circuit output
DATA carries out shift LD.
The counter by the synchronization signal CLK2 flip-flop number, and finally generate count completion signal COUT and
The trigger signal of reset signal RST2, the count completion signal COUT as subsequent module, the reset signal RST2 are used for
Reset the shift register and the counter.
The single wire communication circuit can preferably be connected after wireless communication module, wireless communication module output end and letter
The signal input part connection of number processing circuit, the signal processing circuit are used to handle the wireless signal after demodulating.
Compared with the prior art, the utility model has the advantages that, it is only necessary to use an input signal transmission line, just can lead to
The communication that time-multiplexed mode realizes intermodule is crossed, while in the case where no clock transfer line, being produced using signal of communication
The raw synchronization signal by data bit, to trigger the transmission and storage that single line communication system carries out data, to reduce signal of communication
Call format and transmitting-receiving side clock frequency requirement, improve communication efficiency and quality.Since the physical layer of wireless communication can be with
It is evolved into single line communication, therefore the single wire communication circuit is also particularly suitable for the communication system that prime is wireless communication module, letter
Single circuit structure and excellent signal processing mode reduces requirement of the system to single line communication, while reducing radio communication mold
The structure complexity and cost of block.
Detailed description of the invention
Fig. 1 is single wire communication circuit and waveform diagram.
Fig. 2 is signal processing circuit and data storage and output circuit Inner Constitution schematic diagram.
Fig. 3 is single wire communication circuit internal element connection schematic diagram.
Fig. 4 is another single wire communication circuit internal element connection schematic diagram.
Fig. 5 is the waveform diagram of single wire communication circuit input and output signal.
Fig. 6 is the connection schematic diagram of single wire communication circuit and wireless communication module
Specific embodiment
In conjunction with the preferred embodiment and its attached drawing is further unrestricted detailed to technical solutions of the utility model work
Explanation.
As shown in Figure 1, a kind of single wire communication circuit, single wire communication circuit includes signal processing circuit, the signal processing
Circuit exports corresponding data position DATA, and generate and believe by the synchronous of data bit for receiving and handling external pulse signal CLK1
Number synchronous triggering signal of the CLK2 as subsequent module.It only needs using an input signal transmission line, it just can be multiple by the time-division
Mode realizes the communication of intermodule, while generating synchronization signal using signal of communication, carries out to trigger single line communication system
The transmission and storage of data improve communication effect to reduce the call format of signal of communication and the clock frequency requirement of transmitting-receiving side
Rate and quality.
Then signal processing circuit exports corresponding data position DATA for receiving and handling external pulse signal CLK1, and
Synchronous triggering signal of the synchronization signal CLK2 as subsequent conditioning circuit is generated, wherein each data bit DATA establishes a capital needs extremely really
The CLK1 signal of few 1 number of pulses, and each synchronization signal CLK2 is generated by first pulse in pulse signal CLK1.
For the correct identification for guaranteeing signal of communication, answered from the time for inputting the pulse signal CLK1 to the generation synchronization signal CLK2
The total time for now arriving end-of-pulsing, i.e. t are gone out greater than the input pulse CLK1 middle arteries1> TPulsei, i=1,2,3,4；The synchronization
Before signal CLK2 should appear in the second group pulse signal, i.e. Ti (i=1,2,3) > t2。
As shown in Fig. 2, signal processing circuit includes edge triggered flip flop and delay circuit, data storage includes with output circuit
Shift register and counter, edging trigger circuit are separately connected with delay circuit, shift register, delay circuit respectively also with
Shift register is connected with the counter, and shift register is connect with counter, and edging trigger circuit is for receiving and handling
Different pulse signal CLK1, and processing result input data is stored and output circuit.When the complete arteries and veins of edging trigger processing of circuit
After rushing signal CLK1, delay circuit generates synchronization signal CLK2 and reset signal RST1, and synchronization signal CLK2 is used for trigger data
Storage and output circuit, specifically, shift register is triggered by synchronization signal CLK2, by the data of edging trigger circuit output
DATA carries out shift LD, and reset signal RST1 is used for reset edge trigger circuit, new pulse signal is facilitated to input.
CLK2 synchronization signal is used as the trigger signal of counter simultaneously, completes when counting, and counter output, which counts, completes letter
Number COUT and reset signal RST2, count completion signal COUT can be used as the trigger signal of subsequent module, and reset signal RST2 is used
In resetting shift register and counter, the signal of a new round is facilitated to transmit, according to actually required data bits, may be selected not
The shift register and counter of isotopic number.
As shown in figure 3, edging trigger circuit includes d type flip flop 1 and d type flip flop 2, d type flip flop 1, D trigger 2 and displacement
Register is sequentially connected, and the D input terminal of d type flip flop 1 is supply voltage VDD, the Q output of d type flip flop 1 and the D of d type flip flop 2
Input terminal is connected, and the Q output of d type flip flop 2 is connected with shift register, when single line communication system receives CLK1 pulse signal
When, if what is received is single pulse signal, d type flip flop 1 and d type flip flop 2 are triggered simultaneously once, although d type flip flop 1 is touched
Hair, but its output end Q is not received by trigger 2, therefore the D input terminal input low level of d type flip flop 2, DATA1 output
Low level；When what is received is dipulse or multipulse signal, d type flip flop 1 and d type flip flop 2 are triggered twice or more simultaneously,
The D input terminal of d type flip flop 2 is the Q output of d type flip flop 1, due to the D input termination supply voltage of d type flip flop 1, so Q is defeated
Outlet exports high level, and DATA1 exports high level, and the pulses switch of input enters at the DATA1 signal exported after low and high level
Shift register carries out displacement preservation.
Preferably, different according to edging trigger circuit, the signal processing circuit can handle different pulse signals, judge
It represents " 0 " or " 1 ", then result input data is stored and output circuit.As shown in figure 4, edging trigger circuit can also be touched by D
It sends out device 3 and d type flip flop 4 is constituted, specific connection is consistent with edging trigger circuit shown in Fig. 3, the letter which is constituted
Number processing circuit can distinguish odd number pulse signal and even number pulse signal, if what is received is odd number pulse signal, D touching
Hair device 3 and d type flip flop 4 while the odd-times that is triggered, the QB output end of d type flip flop 3 exports low level always, due to d type flip flop 4
Original state be reset state, therefore be triggered after odd number, the Q output of d type flip flop 4 exports high level, DATA2 output
High level, when what is received is even number pulse signal, d type flip flop 3 and d type flip flop 4 while the even-times that is triggered, d type flip flop 3
QB output end export low level always, due to d type flip flop 4 original state be reset state, be triggered after even number, D
The Q output of trigger 4 exports low level, and DATA2 exports low level, and the pulses switch of input after low and high level at exporting
DATA2 signal enters shift register and carries out displacement preservation.
Delay circuit is connected with d type flip flop 1 (or d type flip flop 3), shift register respectively, when having pulse signal input, D
The Q output of trigger 1 (or d type flip flop 3) exports high level, and QB output end exports low level, QB output end output at this time
Low level obtains synchronization signal CLK2 by delay circuit, as the trigger signal of shift register and counter, delay circuit
Generate RST1 signal simultaneously, RST1 signal as reset signal is input to d type flip flop 1 and d type flip flop 2, and (or d type flip flop 3 and D are touched
Send out device 4) in, d type flip flop 1 and d type flip flop 2 (or d type flip flop 3 and d type flip flop 4) reset.
Input pulse, which is converted to input DATA signal after low and high level and enters shift register, carries out displacement preservation, delay electricity
Road is connected with counter, and shift register is connected with counter, CLK2 signal simultaneously be used as shift register trigger signal and
The count signal of counter.As shown in figure 5, DATA1 represents the data output of the signal processing circuit of single wire communication circuit 1,
DATA2 represents the data output of the signal processing circuit of single wire communication circuit 2, after counting number arrival estimated position, counter
The end COUT generates pulse, inputs N-bit register as next module input pulse, and by the N position data in shift register
In for subsequent module use, data be stored in register (not shown) after, counter can generate a RST2 reset signal and input
In shift register and counter, resetted.
As shown in fig. 6, single wire communication circuit is preferably connected after wireless communication module, wireless communication module output end
It is connect with the signal input part of signal processing circuit.After wireless signal is received by the antenna, it is transmitted in wireless communication module and is solved
It adjusts, finally exports CLK1 signal and received and handled by signal processing circuit, export corresponding data position DATA, and generate synchronization signal
Synchronous triggering signal of the CLK2 as subsequent module.
The utility model has the beneficial effects that signal processing circuit sends out edging trigger circuit by setting delay circuit
It send and receives data there are the time difference, in register by below in use, front communicates mould with data storage and output circuit
Block can restart work again, receive data, realize the communication between disparate modules using single line communication and simple circuit,
Cost is relatively low, portable high, adaptable, has high economic benefit.In addition, before the single wire communication circuit applies also for
Grade is the communication system of wireless communication module, and simple circuit structure and excellent signal processing mode reduce system to single line
The requirement of communication, while reducing the structure complexity and cost of wireless communication module.
It should be pointed out that above-mentioned preferred embodiment is only to illustrate the technical ideas and features of the present invention, purpose
It is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly, this reality can not be limited with this
With novel protection scope.All equivalent change or modifications according to made by the spirit of the present invention essence, should all cover in this reality
Within novel protection scope.
Claims (11)
1. a kind of single wire communication circuit, it is characterised in that: the single wire communication circuit includes signal processing circuit, at the signal
Reason circuit exports corresponding data position DATA, and generate the synchronization by data bit for receiving and handling external pulse signal CLK1
Synchronous triggering signal of the signal CLK2 as subsequent conditioning circuit.
2. single wire communication circuit according to claim 1, it is characterised in that: the signal processing circuit includes interconnected
Edging trigger circuit and delay circuit, input pulse CLK1 obtains data bit DATA after the triggering is along processing of circuit, described
Reset signal of the reset signal RST1 as edging trigger circuit that delay circuit generates, the edging trigger circuit pass through described in prolong
When trigger signal of the synchronization signal CLK2 as subsequent conditioning circuit that generates of circuit.
3. single wire communication circuit according to claim 2, it is characterised in that: the edging trigger circuit is chosen as being connected with each other
D type flip flop 1 and d type flip flop 2, the d type flip flop 1 and d type flip flop 2 receive external signal, the D touching by a signal line
The D input terminal for sending out device 1 is supply voltage VDD, and the D input terminal of the d type flip flop 2 is the Q output of d type flip flop 1.
4. single wire communication circuit according to claim 3, it is characterised in that: the edging trigger circuit is to distinguish pulse
The input pulse CLK1 is converted to low and high level by signal and multipulse signal, the d type flip flop 1 and the d type flip flop 2.
5. single wire communication circuit according to claim 2, it is characterised in that: the edging trigger circuit is also chosen as mutually interconnecting
The d type flip flop 3 and d type flip flop 4 connect, the d type flip flop 3 and d type flip flop 4 receive external signal, the D by a signal line
The D input terminal of trigger 3 is supply voltage VDD, and the D input terminal of the d type flip flop 4 is the QB output end of d type flip flop 3.
6. single wire communication circuit according to claim 5, it is characterised in that: the edging trigger circuit is to distinguish odd number
The input pulse CLK1 is converted to height by pulse signal and even number pulse signal, the d type flip flop 3 and the d type flip flop 4
Low level.
7. single wire communication circuit according to claim 2, it is characterised in that: the single wire communication circuit further includes data storage
With output circuit, the data storage and output circuit are triggered through the synchronization signal CLK2, for depositing the signal processing
The output result DATA of circuit, after a data are transmitted, data storage and output circuit by the data of deposit simultaneously
Row output, uses to subsequent module.
8. single wire communication circuit according to claim 7, it is characterised in that: the data storage includes mutual with output circuit
The shift register and counter of connection, the edging trigger circuit are connect with the shift register, the delay circuit point
It is not connect with the shift register and the counter.
9. single wire communication circuit according to claim 8, it is characterised in that: the shift register passes through the synchronization signal
The data DATA of the edging trigger circuit output is carried out shift LD by CLK2 triggering.
10. single wire communication circuit according to claim 8, it is characterised in that: the counter passes through the synchronization signal
CLK2 flip-flop number, and finally generate count completion signal COUT and reset signal RST2, the count completion signal COUT work
For the trigger signal of subsequent module, the reset signal RST2 is for resetting the shift register and the counter.
11. single wire communication circuit according to claim 1, it is characterised in that: the single wire communication circuit can also preferably be held in the mouth
It is connected to after wireless communication module, the wireless communication module receives external wireless signals, the wireless communication module through antenna
Output end is connect with the signal input part of the signal processing circuit, and the signal processing circuit is used to handle wireless after demodulating
Signal.
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| CN201820810045.9U CN208272972U (en) | 2018-05-29 | 2018-05-29 | A kind of single wire communication circuit |
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| CN201820810045.9U CN208272972U (en) | 2018-05-29 | 2018-05-29 | A kind of single wire communication circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108494433A (en) * | 2018-05-29 | 2018-09-04 | 深圳市力生美半导体股份有限公司 | A kind of single line communication method and its circuit are realized |
| CN110768778A (en) * | 2019-10-31 | 2020-02-07 | 浙江地芯引力科技有限公司 | Single-wire communication circuit, communication method and communication system |
-
2018
- 2018-05-29 CN CN201820810045.9U patent/CN208272972U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108494433A (en) * | 2018-05-29 | 2018-09-04 | 深圳市力生美半导体股份有限公司 | A kind of single line communication method and its circuit are realized |
| CN108494433B (en) * | 2018-05-29 | 2024-05-03 | 深圳市力生美半导体股份有限公司 | Single-wire communication method and circuit implementation thereof |
| CN110768778A (en) * | 2019-10-31 | 2020-02-07 | 浙江地芯引力科技有限公司 | Single-wire communication circuit, communication method and communication system |
| CN110768778B (en) * | 2019-10-31 | 2024-05-07 | 浙江地芯引力科技有限公司 | Single-wire communication circuit, communication method and communication system |
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