CN208239821U - Time signal assignment circuit, subtraction count device and inverse timing device - Google Patents
Time signal assignment circuit, subtraction count device and inverse timing device Download PDFInfo
- Publication number
- CN208239821U CN208239821U CN201820447277.2U CN201820447277U CN208239821U CN 208239821 U CN208239821 U CN 208239821U CN 201820447277 U CN201820447277 U CN 201820447277U CN 208239821 U CN208239821 U CN 208239821U
- Authority
- CN
- China
- Prior art keywords
- signal
- feedback
- transmission gate
- generation module
- time signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
Abstract
The utility model belongs to electronic watch chip field, disclosing a kind of time signal assignment circuit, subtraction count device and inverse timing device, time signal assignment circuit realizes the logic circuit with assignment function by the logical combination of the first transmission gate, the second transmission gate, third transmission gate, the 4th transmission gate, the 5th transmission gate, the 6th transmission gate, the first NAND gate, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter and the 8th phase inverter；Being sequentially connected seven above-mentioned time signal assignment circuits also according to 60 system subtracter output waveforms simultaneously, and peripheral circuit is cooperated to realize the subtraction count device with 60 system of assignment；The subtraction count device of the utility model is only made of simple logic gate while realizing assignment function, without complicated comparator, memory or microprocessor, therefore is simplified circuit structure, is reduced hardware and software cost.
Description
Technical field
The utility model belongs to electronic watch chip field more particularly to a kind of time signal assignment circuit, subtraction count device
And inverse timing device.
Background technique
In electronic watch integrated circuit, time walking is realized using the method for system, 100 systems of millisecond, the second
60 systems, 60 systems of minute and 24 systems of hour, each system circuit has the pulse signal input of a time
Port is as inputting, and each output signal line in each system is transferred in display circuit, when the walking of time pulse makes
The signal obtained in each system circuit changes, then is shown by display circuit, to obtain the time seen by person.
100 systems of either 100 systems of addition, 60 systems and 24 systems or subtraction, 60 systems and 24 systems, pulse are all
It inputs from the input terminal of system and one by one, then constantly period, so the time seen all is from original state
(original state is typically all 0 or 1) starts counting.
But under specific condition, due to the demand of function, the initial value of time is shown and is just required.As shown in Fig. 1,
Existing 60 system inverse timing device is that former 60 system circuits are connect with display circuit, in stopwatch countdown process, is generally powered on
The initial value of default is 12:00:00 or 00:00:00, if it is desired to countdown 10 seconds 20 minutes 5 hours, this 05:20:
10 be exactly the initial value that user needs, during user's manual key setting time forming time adjustment signal, when passing through
Between system inside the former 60 system circuits of adjustment signal just as 05:20:10 has been transferred in the setting of user, then again from this when
Between start countdown.After starting countdown, former 60 system circuit numerical value are changed with the input of time pulse signal；When
The time goes to some time in countdown process, and user needs to come again after needing to re-start countdown or time countdown
Countdown, at this moment the system logic value of former 60 system circuits has been walked the numerical value to some numerical value or end
00:00:00；Rather than the initial value 05:20:10 of setting.And the demand of user is direct reduction to just setting 05:20:10,
It no longer needs to go to set the time manually again.
A kind of conventional scheme is memory and comparator composition in circuit.During i.e. user sets count down time,
Signal by the signal set in logic system circuit storage into memory, when user resets, in logic system circuit
It is compared with the setting signal stored by comparator, is constantly constantly filled into logic system circuit when inconsistent
Enter pulse, when exactly matching the setting signal of the circuit signal in logic system circuit and storage, stopping pours into arteries and veins
Punching, then the time returns to the numerical value set before.The field-effect tube quantity that the memory and comparator used in this scheme need compared with
Costs that are more, entire circuit increase being given very big, and it is relative complex in design process, and flexibility is low.And has be somebody's turn to do in the market
The electronic watch of function largely uses microprocessor arrangement, because the cost using microprocessor arrangement differs not with above scheme
Greatly, and flexibility is high, and scalability is also high, but the market price is also expensive very much.
The prior art is not possible to provide the relatively simple 60 system subtraction count devices with assignment function of circuit structure.
Utility model content
The utility model provides a kind of time signal assignment circuit, subtraction count device and inverse timing device, it is intended to solve
Certainly the problem of the relatively simple 60 system subtraction count device with assignment function of circuit structure can not be provided of the prior art.
The utility model is realized in this way a kind of time signal assignment circuit, including the first transmission gate, the second transmission
Door, third transmission gate, the 4th transmission gate, the 5th transmission gate, the 6th transmission gate, the first NAND gate, the first phase inverter, the second reverse phase
Device, third phase inverter, the 4th phase inverter, the 5th phase inverter and the 8th phase inverter；
The first input end of first NAND gate be the time signal assignment circuit clock signal terminal, described first
Second input terminal of NAND gate, the The positive phase control end of second transmission gate, the input terminal of the 8th phase inverter and described
The inverted control terminals of third transmission gate collectively form the switch control terminal of the time signal assignment circuit, first NAND gate
Output end and the input terminal of the 5th phase inverter, the The positive phase control end of first transmission gate, the 4th transmission gate
Inverted control terminals, the 5th transmission gate inverted control terminals and the 6th transmission gate The positive phase control end connection, institute
The The positive phase control end for stating the output end of the 5th phase inverter and the inverted control terminals of first transmission gate, the 4th transmission gate connects
Connect, the The positive phase control end of the 5th transmission gate connection and the 6th transmission gate negative control terminal connection, the described 8th
The output end of phase inverter is connect with the The positive phase control end of the inverted control terminals of second transmission gate and the third transmission gate；
The input terminal of first transmission gate is the feedback input end of the time signal assignment circuit, second transmission
The input terminal of door is the assertive signal end of the time signal assignment circuit, the output end of first transmission gate and described second
The input terminal of the output end of transmission gate, the input terminal of first phase inverter and the third transmission gate connects, and described first
The output end of phase inverter is connect with the input terminal of second phase inverter, and the output end of the third transmission gate and the described 4th passes
The input terminal of defeated door connects, the output end and the 5th biography of the output end of second phase inverter and the 4th transmission gate
The input terminal of defeated door connects, and the output end of the 5th transmission gate and the input terminal of the third phase inverter and the described 6th transmit
The input terminal of the input terminal connection of door, the output end of the third phase inverter and the 4th phase inverter collectively forms the time
The display signal output end of signal assignment circuit, the output end of the 4th phase inverter and the output end of the 6th transmission gate are total
With the negative-feedback output end for constituting the time signal assignment circuit.
The utility model also provides a kind of subtraction count device comprising above-mentioned time signal assignment circuit, the subtraction meter
Counting device includes:
Assignment is carried out according to the first data-signal of input, and according to the clock signal of input to the first time signal
It is raw to generate the first of the first display signal and the first negative-feedback output signal the display signal to carry out 60 system subtraction counts
At module；
Show that signal generation module and the 4th display signal generate mould with the second display signal generation module, third
Block connection, according to the second negative-feedback output signal, third shows that signal and the 4th display signal generate the second feedback signal
Second feedback module；
It connect with the first display signal generation module and second feedback module, is believed according to the second time of input
Number carry out assignment, and according to the first negative-feedback output signal and second feedback signal to second time signal into
60 system subtraction count of row shows signal with generate the second display signal and the second negative-feedback output signal described second
Generation module；
It is connect with the second display signal generation module, according to the third time signal of input progress assignment, and according to
The second negative-feedback output signal carries out 60 system subtraction counts to the third time signal and is shown with generating the third
The third of signal and the third negative-feedback output signal shows signal generation module；
Show that signal generation module and the 4th display signal are raw with the second display signal generation module, the third
It is connected at module, according to the second display signal, the third shows that signal and the 4th display signal generate the 4th feedback
4th feedback module of signal；
It connect with the first display signal generation module and the 4th feedback module, is believed according to the 4th time of input
Number carry out assignment, and according to the first negative-feedback output signal and the 4th feedback signal to the 4th time signal into
60 system subtraction count of row is shown with the generate the 4th display signal and the 4th negative-feedback output signal the described 4th
Signal generation module；
It is connect with the 4th display signal generation module, according to the 5th time signal of input progress assignment, and according to
The 4th negative-feedback output signal carries out 60 system subtraction counts to the 5th time signal to generate the 5th display
5th display signal generation module of signal and the 5th negative-feedback output signal；
It is connect with the 5th display signal generation module and the 7th display signal generation module, according to the of input
Six time signals carry out assignment, and are believed according to the 5th negative-feedback output signal and the 7th display signal the 6th time
Number carry out 60 system subtraction counts with generate it is described 6th display signal and the 6th negative-feedback output signal the 6th display
Signal generation module；
It is connect with the 6th display signal generation module and the 7th display signal generation module, according to the described 6th
Show that signal and the 7th display signal generate the 7th feedback module of the 7th feedback signal；
It connect with the 5th display signal generation module and the 7th feedback module, is believed according to the 7th time of input
Number carry out assignment, and according to the 5th negative-feedback output signal and the 7th feedback signal to the 7th time signal into
60 system subtraction count of row shows signal with the generate the 7th display signal and the 7th negative-feedback output signal the 7th
Generation module；
Wherein, the second display signal generation module, the third show signal generation module, the 4th display letter
Number generation module, the 5th display signal generation module, the 6th display signal generation module and the 7th display
Signal generation module is the time signal assignment circuit.
The utility model also provides a kind of inverse timing device comprising above-mentioned subtraction count device, the inverse timing device packet
It includes:
For generating the time signal generation module of the time signal of 60 systems；
It connect with the time signal generation module, for carrying out assignment according to the time signal, and is believed according to pulse
Number and switch control signal to the time signal carry out 60 system subtraction counts with generate display signal the subtraction count
Device；
It is connect with the subtraction count device, the display module that the display signal is shown.
Input terminal by the first transmission gate is the feedback input end of time signal assignment circuit, the input of the second transmission gate
End is the assertive signal end of time signal assignment circuit, the output end of the output end of the first transmission gate and the second transmission gate, first
The input terminal connection of the input terminal and third transmission gate of phase inverter, the input of the output end of the first phase inverter and the second phase inverter
End connection, the output end of third transmission gate are connect with the input terminal of the 4th transmission gate, and the output end of the second phase inverter and the 4th passes
The connection of the input terminal of the output end of defeated door and the 5th transmission gate, the output end of the 5th transmission gate and the input terminal of third phase inverter
It is connected with the input terminal of the 6th transmission gate, the input terminal of the output end of third phase inverter and the 4th phase inverter collectively forms time letter
The output end of the display signal output end of number assignment circuit, the output end of the 4th phase inverter and the 6th transmission gate collectively forms
The negative-feedback output end of the time signal assignment circuit constitutes the logic circuit with assignment function；Simultaneously also according to 60 into
Subtracter output waveform processed is sequentially connected seven above-mentioned time signal assignment circuits, and cooperates peripheral circuit to realize to have
The subtraction count device function of 60 systems of assignment function；Moreover, above-mentioned subtraction count device is connected to time signal generation module
Among display module, the inverse timing device of 60 systems is realized；Subtraction count device is only made of simple logic gate, without multiple
Miscellaneous comparator, memory or microprocessor, therefore circuit structure is simplified, reduce hardware and software cost, above-mentioned increase
The competitiveness of product in market.
Detailed description of the invention
It is novel in order to illustrate more clearly of the technical application in the utility model embodiment, it below will be in embodiment description
Required attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only the one of the utility model
A little embodiments for those of ordinary skill in the art without creative efforts, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the function structure chart of 60 system inverse timing device of the prior art
Fig. 2 is the schematic diagram of time signal assignment circuit provided by the embodiment of the utility model.
Fig. 3 is the subtraction count provided by the embodiment of the utility model including time signal assignment circuit as shown in Figure 2
A kind of function structure chart of device；
Fig. 4 is the subtraction count device provided in an embodiment of the present invention including time signal assignment circuit as shown in Figure 2
A kind of circuit diagram；
Fig. 5 is that the inverse timing device provided by the embodiment of the utility model including subtraction count device as shown in Figure 3 is a kind of
Function structure chart.
Specific embodiment
It is practical new to this below in conjunction with attached drawing to keep the purpose of this utility model, technical solution and advantage clearer
Type embodiment is described in further detail.
Fig. 2 is a kind of structure of time signal assignment circuit provided by the embodiment of the utility model, for ease of description, only
Part relevant to the utility model embodiment is shown, details are as follows:
A kind of time signal assignment circuit, including the first transmission gate COMS1, the second transmission gate COMS2, third transmission gate
COMS3, the 4th transmission gate COMS4, the 5th transmission gate COMS5, the 6th transmission gate COMS6, the first NAND gate NAND1, first are instead
Phase device INV1, the second phase inverter INV2, third phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5 and the 8th
Phase inverter INV8.
Wherein, the first input end of the first NAND gate NAND1 is the clock signal terminal CLK of time signal assignment circuit, the
The second input terminal of one NAND gate NAND1, the second transmission gate COMS2 The positive phase control end CP, the 8th phase inverter INV8 input
The inverted control terminals CN of end and third transmission gate COMS3 collectively form the switch control terminal CTRL of time signal assignment circuit,
The positive phase control of the input terminal of the output end of first NAND gate NAND1 and the 5th phase inverter INV5, the first transmission gate COMS1
Hold CP, the inverted control terminals CN of the 4th transmission gate COMS4, the transmission of the inverted control terminals CN of the 5th transmission gate COMS5 and the 6th
The The positive phase control end CP connection of door COMS6, the inverted control terminals of the output end of the 5th phase inverter INV5 and the first transmission gate COMS1
CN, the The positive phase control end CP connection of the 4th transmission gate COMS4, the The positive phase control end CP connection of the 5th transmission gate COMS5 and
The negative control terminal CN connection of six transmission gate COMS6, the reverse phase of the output end of the 8th phase inverter INV8 and the second transmission gate COMS2
Control terminal CN is connected with the The positive phase control end CP of third transmission gate COMS3.
Wherein, the input terminal S of the first transmission gate COMS1 is the feedback input end DATE of time signal assignment circuit, second
The input terminal S of transmission gate COMS2 is the assertive signal end TIME of time signal assignment circuit, the output of the first transmission gate COMS1
Hold the input of the output end D of D and the second transmission gate COMS2, the input terminal and third transmission gate COMS3 of the first phase inverter INV1
S connection is held, the output end of the first phase inverter INV1 is connect with the input terminal of the second phase inverter INV2, third transmission gate COMS3's
Output end D is connect with the input terminal of the 4th transmission gate COMS4, the output end and the 4th transmission gate COMS4 of the second phase inverter INV2
Output end and the 5th transmission gate COMS5 input terminal connection, the output end of the 5th transmission gate COMS5 and third phase inverter
The input terminal S connection of the input terminal of INV3 and the 6th transmission gate COMS6, the output end and the 4th reverse phase of third phase inverter INV3
The input terminal of device INV4 collectively forms the display signal output end OUT of time signal assignment circuit, and the 4th phase inverter INV4's is defeated
The output end of outlet and the 6th transmission gate COMS6 collectively form the negative-feedback output end OUT_B of time signal assignment circuit.
Optionally, the negative-feedback output end OUT_B of time signal assignment circuit and the feedback of time signal assignment circuit are defeated
Enter DATE is held to connect, so that time signal assignment circuit realizes divide-by-two function.
It is described further below in conjunction with working principle to shown in Fig. 2:
Input signal that there are four above-mentioned time signal assignment circuit tools, specifically:
1, assertive signal: the signal is inputted by the assertive signal end TIME of time signal assignment circuit.By the 60 of generation into
For the time signal of system as assertive signal, assertive signal is initial signal set by user, can be straight in user's reseting procedure
Connect assignment and by time signal assignment circuit output to display module；
2, feedback signal: the signal is inputted by the feedback input end DATE of time signal assignment circuit.The function of feedback signal
It can be similar to the D signal of common two-divider, feedback signal and the negative-feedback output end of time signal assignment circuit are connected
Connect the function of may make time signal assignment circuit to be likewise supplied with two-divider, can also by the input of peripheral coherent signal,
The output signal that may make the display signal output end of time signal assignment circuit is predetermined waveform signal, for example, predetermined waveform
Signal can be the waveform signal of each output end of 60 system subtracters.
3, switch control signal: the signal is inputted by the switch control terminal CTRL of time signal assignment circuit.The signal is used
In the output state of control " assertive signal ", when user resets to initialization time manually, switch, which is opened, promotes " assertive signal "
It is successfully entered in time signal assignment circuit, then carries out being transferred to display module；" feedback signal " is used as the time by no person
The input of signal assignment circuit.
4, clock signal: the signal is inputted by the clock signal terminal CLK of time signal assignment circuit.The function of clock signal
Similar to the clock signal of common two-divider, in the time signal assignment circuit course of work, the conversion of clock signal level
Promote the either on or off of associated transport door in circuit, so that output signal has logicality.
Output signal that there are two above-mentioned time signal assignment circuit tools, specifically:
1, show signal: the signal is exported by the display signal output end OUT of time signal assignment circuit.Show that signal is straight
It connects and is output in display module, there are two sources for the signal: one is the defeated of " switch control signal " selection " assertive signal "
Out, the other is the output waveform for generating and obtaining that cooperates in circuit of " feedback signal " combination " clock signal ".
2, negative-feedback output signal: the signal is exported by the negative-feedback output end OUT_B of time signal assignment circuit.It is negative anti-
The inversion signal that output signal is " display signal " is presented, is assigned as itself circuit negative-feedback input or next time signal
It is worth the input of circuit, major function is the waveform for cooperating adjustment signal.
In the specific implementation process, when switch control signal CTRL is low level, CTRL_B signal and SWTH signal are all
For high level, i.e. the second transmission gate COMS2 and the 5th transmission gate COMS5 is opened, and assertive signal TIME passes through the second transmission gate
COMS2 is transferred to single_A signal, and then single_A signal is passed by the first phase inverter INV1 and the second phase inverter INV2
Defeated to arrive single_B signal, single_B signal is transferred to single_C signal by the 5th transmission gate COMS5, finally by the
Three INV3 and the 4th phase inverter INV4 are directly output to OUT, and which achieves directly directly assign the initialization time set
It is worth display signal output end OUT.
When switch control signal CTRL is high level, the second transmission gate COMS2 is closed, if clock signal clk is also to hold
When continuous high level does not have new pulse to come in, SWTH signal is low level, and the 5th transmission gate CMOS5 is closed, the 6th transmission gate COMS6
It opening, output signal OUT returns again to itself output back to single_C signal by the 6th transmission gate COMS6 later at this time,
There is new clock pulses that can all recycle before coming in constant, so that not starting counting after user's reset initialization time
When, the display that numerical value can be kept for a long time constant, the effect of third phase inverter INV3 and the 4th phase inverter INV4 is provided to circuit
One carrying load ability；The first transmission gate COMS1 is opened simultaneously, and feedback signal DATE is transferred to by the first transmission gate COMS1
Single_A signal, then single_A signal is transferred to single_B by the first phase inverter INV1 and the second phase inverter INV2
Signal, single_B signal is latched at this time.
After user starts counting, clock signal clk starts timing, when the pulse of time signal CLK updates one time,
When low level is come in, SWTH signal is lower, and the first transmission gate COMS1 and the 6th transmission gate COMS6 are closed at this time, the 4th transmission
Door COMS4 and the 5th transmission gate COMS5 is opened, and feedback signal DATE is latched into single_B signal and is transferred to by before
Single_C is output to display signal output end OUT using third phase inverter INV3 and the 4th phase inverter INV4.
If the signal of feedback signal DATE input is the negative-feedback output signal OUT_B of itself, time signal assignment electricity
Road is achieved that the function of two-divider, and feedback signal DATE input can also be required according to output waveform and the collocation of peripheral circuit
Input.
In addition, the utility model embodiment also provides one of the subtraction count device comprising above-mentioned time signal assignment circuit
Kind structure, for ease of description, Fig. 3, which is shown, illustrates only part relevant to the utility model embodiment, and details are as follows:
Above-mentioned subtraction count device includes:
Assignment is carried out according to the first data-signal of input, and first time signal is carried out according to the clock signal of input
60 system subtraction counts show signal generation module 01 with generate the first display signal and the first negative-feedback output signal first.
The initialization values of countdown are set before user's countdown by key, wherein first time signal is initialization
First signal of binary coding of a position of numerical value, the first display signal generation module 01 is according to a positions of initialization values
The primary 60 system subtraction count rule of binary coding generates the first display signal.
Show that signal generation module 03 and the 4th display signal generate mould with the second display signal generation module 02, third
Block connection, according to the second negative-feedback output signal, third shows that signal and the 4th display signal generate the second feedback signal
Second feedback module 08.
With first display signal generation module 01 and the second feedback module 08 connect, according to the second time signal of input into
Row assignment, and 60 system subtraction counts are carried out to the second time signal according to the first negative-feedback output signal and the second feedback signal
To generate the second display signal generation module 02 of the second display signal and the second negative-feedback output signal.
Wherein, the second time signal is the binary coding second signal of a position of initialization values, the second display letter
Number generation module 02 generates the according to the deputy 60 system subtraction count rule of binary coding of a position of initialization values
Two display signals.
Connect with the second display signal generation module 02, according to the third time signal of input progress assignment, and according to the
Two negative-feedback output signals carry out 60 system subtraction counts to third time signal to generate third and show that signal and third are negative anti-
The third for presenting output signal shows signal generation module 03.
Wherein, third time signal is the binary coding tribute signal of a position of initialization values, third display letter
Number generation module 03 generates the according to 60 system subtraction count rules of the binary coding third position of a position of initialization values
Three display signals.
Show that signal generation module 03 and the 4th display signal generate mould with the second display signal generation module 02, third
Block 04 connects, and according to the second display signal, third shows that signal and the 4th display signal generate the 4th of the 4th feedback signal
Feedback module 09.
With first display signal generation module 01 and the 4th feedback module 09 connect, according to the 4th time signal of input into
Row assignment, and 60 system subtraction counts are carried out to the 4th time signal according to the first negative-feedback output signal and the 4th feedback signal
To generate the 4th display signal generation module 04 of the 4th display signal and the 4th negative-feedback output signal.
Wherein, the 4th time signal is the 4th signal of binary coding of a position of initialization values, the 4th display letter
Number generation module 04 generates the according to binary coding the 4th 60 system subtraction count rules of a position of initialization values
Four display signals.
Connect with the 4th display signal generation module 04, according to the 5th time signal of input progress assignment, and according to the
Four negative-feedback output signals carry out 60 system subtraction counts to the 5th time signal to generate the 5th display signal and the 5th negative anti-
Present the 5th display signal generation module 05 of output signal.
Wherein, the 5th time signal is ten first signal of binary coding of initialization values, the 5th display letter
Number generation module 05 generates the according to the primary 60 system subtraction count rule of ten binary codings of initialization values
Five display signals.
It is connect with the 5th display signal generation module 05 and the 7th display signal generation module 07, when according to the 6th of input the
Between signal carry out assignment, and according to the 5th negative-feedback output signal and the 7th display signal to the 6th time signal carry out 60 systems
Subtraction count shows signal generation module 06 with the generate the 6th display signal and the 6th negative-feedback output signal the 6th.
Wherein, the 6th time signal is ten binary coding second signals of initialization values, the 6th display letter
Number generation module 06 generates the according to the deputy 60 system subtraction count rule of ten binary codings of initialization values
Six display signals.
It is connect with the 6th display signal generation module 06 and the 7th display signal generation module 07, according to the 6th display signal
The 7th feedback module 10 of the 7th feedback signal is generated with the 7th display signal.
It connect with the 5th display signal generation module 05 and the 7th feedback module, is carried out according to the 7th time signal of input
Assignment, and 60 system subtraction counts are carried out to the 7th time signal according to the 5th negative-feedback output signal and the 7th feedback signal
To generate the 7th display signal generation module 07 of the 7th display signal and the 7th negative-feedback output signal.
Wherein, the 7th time signal is ten binary coding tribute signal of initialization values, the 7th display letter
Number generation module 07 generates the according to 60 system subtraction count rules of ten of initialization values binary coding third positions
Seven display signals.
Wherein, the second display signal generation module 02, third show that signal generation module the 03, the 4th shows that signal generates mould
Block the 04, the 5th shows that signal generation module the 05, the 6th shows signal generation module 06 and the 7th display signal generation module 07
It is time signal assignment circuit.
Fig. 4 shows the exemplary circuit structure of subtraction count device provided by the embodiment of the utility model, for ease of description,
Part relevant to the utility model embodiment is illustrated only, details are as follows:
First display signal generation module 01 includes first time signal assignment circuit X1, first time signal assignment circuit
Negative-feedback output end OUT_B connect with the feedback input end DATE of first time signal assignment circuit；
Third shows that signal generation module 03 includes third time signal assignment circuit X3, third time signal assignment circuit
Negative-feedback output end OUT_B connect with the feedback input end DATE of third time signal assignment circuit；
5th display signal generation module 05 includes the 5th time signal assignment circuit X5, the 5th time signal assignment circuit
Negative-feedback output end OUT_B connect with the feedback input end DATE of the 5th time signal assignment circuit.
In addition, the second display signal generation module 02 includes the second time signal assignment circuit X2, the 4th display signal is raw
It include the 4th time signal assignment circuit X4 at module 04, the 6th display signal generation module 06 includes the 6th time signal assignment
Circuit X6, the 7th display signal generation module 07 includes the 7th time signal assignment circuit X7.
The switch control of the switch control terminal CTRL of first time signal assignment circuit and the second time signal assignment circuit
Hold the switch control terminal of CTRL, the switch control terminal CTRL of third time signal assignment circuit, the 4th time signal assignment circuit
CTRL, the switch control terminal CTRL of the 5th time signal assignment circuit, the 6th time signal assignment circuit switch control terminal
The switch control terminal CTRL connection of CTRL, the 7th time signal assignment circuit.
Second feedback module 08 include the first XOR gate XOR1, hex inverter INV6, the second NAND gate NAND2 and
7th phase inverter INV7.The second input terminal of the first input end of first XOR gate XOR1 and the first XOR gate XOR1 are respectively
Second input terminal of the first input end of two feedback modules 08 and the second feedback module 08, the output end of the first XOR gate XOR1 with
The input terminal of hex inverter INV6 connects, and the first input end of the second NAND gate NAND2 is the third of the second feedback module 08
Input terminal, the output end of hex inverter INV6 are connect with the second input terminal of the second NAND gate NAND2, the second NAND gate
The output end of NAND2 is connect with the input terminal of the 7th phase inverter INV7, and the output end of the 7th phase inverter INV7 is the second feedback mould
The output end of block 08.
4th feedback module 09 is the second XOR gate XOR2；First input end, the second XOR gate of second XOR gate XOR2
The third input terminal of the second input terminal of XOR2 and the second XOR gate XOR2 are respectively the first input of the 4th feedback module 09
The third input terminal at end, the second input terminal of the 4th feedback module 09 and the 4th feedback module 09, the second XOR gate XOR2's
Output end is the output end of the 4th feedback module 09.
7th feedback module 10 is third XOR gate XOR3；The first input end and third XOR gate of third XOR gate XOR3
The second input terminal of XOR3 is respectively the first input end of the 7th feedback module 10 and the second input terminal of the 7th feedback module 10,
The output end of third XOR gate XOR3 is the output end of the 7th feedback module 10.
It is described further below in conjunction with working principle to shown in Fig. 4:
In the specific implementation process, it is assumed that user setting is in 60 systems with one second speed since initialization values 33
Countdown is spent, when the time goes to default value 16, is resetted again, it at this time can be direct by the initialization values 33 set before
Assignment output, specific work process are as follows: signal TH60_L1, TH60_L2, TH60_L3, TH60_L4, TH60_H1, TH60_
H2, TH60_H3 are the initialization values (such as numerical value 33) being arranged in former 60 system circuits, are respectively the first data-signal
To the 7th data-signal, i.e. respectively a position of the binary coding of a position of initialization values first, initialization values
Binary coding second, the binary coding second of a position of initialization values, initialization values a position binary system
Encode second, ten binary codings first of initialization values, ten binary codings of initialization values the
Ten binary coding third positions of two and initialization values；L1, L2, L3, L4, H1, H2, H3 are with assignment function
The numerical value for being output to display module of the subtraction count device of 60 systems of energy is respectively the binary coding for showing a position of numerical value
First, show numerical value a position binary coding second, show numerical value a position binary coding second, show show
The binary coding second of a position of registration value, ten binary codings first for showing numerical value, show numerical value ten
The binary coding second of position and ten binary coding third positions for showing numerical value；It is switched during user setting
Control signal CTRL is in low level, and the signal waveform of the initialization values set directly passes through time signal assignment circuit biography
It is defeated arrive display module, after user starts timing, switch control signal CTRL is raised, time signal assignment circuit begin to
One second speed of per unit counts downwards, and when counting down to default value (such as numerical value 16), user resets, and switchs at this time
Control signal CTRL is dragged down again, then the initialization values set before are carried out assignment output, reaches memory output with this
Function, without being configured again.
The utility model embodiment also provides a kind of inverse timing device comprising above-mentioned subtraction count device, such as Fig. 5 institute
Show, inverse timing device includes:
For generating the time signal generation module 11 of the time signal of 60 systems.
In specific implementation, time signal generation module 11 can be the original as shown in Figure 1 after removing clock pulse signal
60 system circuits.
It connect with time signal generation module 11, for carrying out assignment according to time signal, and according to pulse signal and opens
It closes control signal and 60 system subtraction counts is carried out to generate the subtraction count device 12 of display signal to time signal.
It is connect with subtraction count device 12, the display module 13 that display signal is shown.
The utility model embodiment passes through the first transmission gate, the second transmission gate, third transmission gate, the 4th transmission gate, the 5th
Transmission gate, the 6th transmission gate, the first NAND gate, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th
The logical combination of phase inverter and the 8th phase inverter realizes the logic circuit with assignment function；Subtract simultaneously also according to 60 systems
Musical instruments used in a Buddhist or Taoist mass output waveform is sequentially connected seven above-mentioned time signal assignment circuits, and peripheral circuit is cooperated to realize with assignment
The subtraction count device function of 60 systems of function；Moreover, above-mentioned subtraction count device is connected to time signal generation module and is shown
Show among module, realizes the inverse timing device of 60 systems；The subtraction count device of the utility model embodiment is only by simply patrolling
Volume door is constituted, and without complicated comparator, memory or microprocessor, therefore simplifies circuit structure, reduces hardware and soft
Part cost, it is above-mentioned to increase the competitiveness of product in market.
The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all practical at this
Within novel spirit and principle, any modification, equivalent replacement, improvement and so on should be included in the guarantor of the utility model
Within the scope of shield.
Claims (8)
1. a kind of time signal assignment circuit, which is characterized in that including the first transmission gate, the second transmission gate, third transmission gate,
Four transmission gates, the 5th transmission gate, the 6th transmission gate, the first NAND gate, the first phase inverter, the second phase inverter, third phase inverter,
Four phase inverters, the 5th phase inverter and the 8th phase inverter；
The first input end of first NAND gate be the time signal assignment circuit clock signal terminal, described first with it is non-
The second input terminal, the The positive phase control end of second transmission gate, the input terminal of the 8th phase inverter and the third of door
The inverted control terminals of transmission gate collectively form the switch control terminal of the time signal assignment circuit, first NAND gate it is defeated
Outlet and the input terminal of the 5th phase inverter, the The positive phase control end of first transmission gate, the reverse phase of the 4th transmission gate
The The positive phase control end of control terminal, the inverted control terminals of the 5th transmission gate and the 6th transmission gate connects, and the described 5th
The output end of phase inverter connect with the The positive phase control end of the inverted control terminals of first transmission gate, the 4th transmission gate, institute
State the The positive phase control end connection of the 5th transmission gate and the negative control terminal connection of the 6th transmission gate, the 8th phase inverter
Output end connect with the The positive phase control end of the inverted control terminals of second transmission gate and the third transmission gate；
The input terminal of first transmission gate is the feedback input end of the time signal assignment circuit, second transmission gate
Input terminal is the assertive signal end of the time signal assignment circuit, the output end of first transmission gate and second transmission
The input terminal connection of the output end of door, the input terminal of first phase inverter and the third transmission gate, first reverse phase
The output end of device is connect with the input terminal of second phase inverter, the output end of the third transmission gate and the 4th transmission gate
Input terminal connection, the output end and the 5th transmission gate of the output end of second phase inverter and the 4th transmission gate
Input terminal connection, the output end of the 5th transmission gate and the input terminal of the third phase inverter and the 6th transmission gate
The input terminal of input terminal connection, the output end of the third phase inverter and the 4th phase inverter collectively forms the time signal
The display signal output end of assignment circuit, the output end of the 4th phase inverter and the common structure of output end of the 6th transmission gate
At the negative-feedback output end of the time signal assignment circuit.
2. time signal assignment circuit as described in claim 1, which is characterized in that the time signal assignment circuit it is negative anti-
Feedback output end is connect with the feedback input end of the time signal assignment circuit.
3. a kind of subtraction count device comprising time signal assignment circuit described in claim 1, which is characterized in that the subtraction
Counter includes:
Assignment is carried out according to the first data-signal of input, and the first time signal is carried out according to the clock signal of input
60 system subtraction counts generate mould with the first display signal for generating the first display signal and the first negative-feedback output signal
Block；
Show that signal generation module and the 4th display signal generation module connect with the second display signal generation module, third
It connects, according to the second negative-feedback output signal, third shows that signal and the 4th display signal generate the second of the second feedback signal
Feedback module；
With it is described first display signal generation module and second feedback module connect, according to the second time signal of input into
Row assignment, and 60 are carried out to second time signal according to the first negative-feedback output signal and second feedback signal
System subtraction count is generated with the second display signal for generating the second display signal and the second negative-feedback output signal
Module；
It is connect with the second display signal generation module, assignment is carried out according to the third time signal of input, and according to described
Second negative-feedback output signal carries out 60 system subtraction counts to the third time signal and shows signal to generate the third
Signal generation module is shown with the third of the third negative-feedback output signal；
Show that signal generation module and the 4th display signal generate mould with the second display signal generation module, the third
Block connection, according to the second display signal, the third shows that signal and the 4th display signal generate the 4th feedback signal
The 4th feedback module；
With it is described first display signal generation module and the 4th feedback module connect, according to the 4th time signal of input into
Row assignment, and 60 are carried out to the 4th time signal according to the first negative-feedback output signal and the 4th feedback signal
System subtraction count shows signal with the generate the 4th display signal and the 4th negative-feedback output signal the described 4th
Generation module；
It is connect with the 4th display signal generation module, assignment is carried out according to the 5th time signal of input, and according to described
4th negative-feedback output signal carries out 60 system subtraction counts to the 5th time signal to generate the 5th display signal
Signal generation module is shown with the 5th of the 5th negative-feedback output signal the；
It is connect with the 5th display signal generation module and the 7th display signal generation module, when according to the 6th of input the
Between signal carry out assignment, and according to the 5th negative-feedback output signal and the 7th display signal to the 6th time signal into
60 system subtraction count of row shows signal with the generate the 6th display signal and the 6th negative-feedback output signal the 6th
Generation module；
It is connect with the 6th display signal generation module and the 7th display signal generation module, according to the 6th display
Signal and the 7th display signal generate the 7th feedback module of the 7th feedback signal；
With it is described 5th display signal generation module and the 7th feedback module connect, according to the 7th time signal of input into
Row assignment, and 60 are carried out to the 7th time signal according to the 5th negative-feedback output signal and the 7th feedback signal
System subtraction count is generated with the 7th display signal for generating the 7th display signal and the 7th negative-feedback output signal
Module；
Wherein, the second display signal generation module, the third show that signal generation module, the 4th display signal are raw
At module, the 5th display signal generation module, the 6th display signal generation module and the 7th display signal
Generation module is the time signal assignment circuit.
4. subtraction count device as claimed in claim 3, which is characterized in that the first display signal generation module includes first
Time signal assignment circuit, the negative-feedback output end of the first time signal assignment circuit and the first time signal assignment
The feedback input end of circuit connects；
The third shows that signal generation module includes third time signal assignment circuit, the third time signal assignment circuit
Negative-feedback output end connect with the feedback input end of the third time signal assignment circuit；
The 5th display signal generation module includes the 5th time signal assignment electricity in the 5th time signal assignment circuit
The negative-feedback output end on road is connect with the feedback input end of the 5th time signal assignment circuit.
5. subtraction count device as claimed in claim 3, which is characterized in that the second feedback module includes the first XOR gate, the 6th
Phase inverter, the second NAND gate and the 7th phase inverter；
Second input terminal of the first input end of first XOR gate and first XOR gate is respectively second feedback
Second input terminal of the first input end of module and second feedback module, the output end of first XOR gate and described the
The input terminal of hex inverter connects, and the first input end of second NAND gate is that the third of second feedback module inputs
End, the output end of the hex inverter connect with the second input terminal of second NAND gate, second NAND gate it is defeated
Outlet is connect with the input terminal of the 7th phase inverter, and the output end of the 7th phase inverter is the defeated of second feedback module
Outlet.
6. subtraction count device as claimed in claim 3, which is characterized in that the 4th feedback module is the second XOR gate；
The first input end of second XOR gate, the second input terminal of second XOR gate and second XOR gate
Third input terminal be respectively the first input end of the 4th feedback module, the 4th feedback module the second input terminal and
The third input terminal of 4th feedback module, the output end of second XOR gate are the output of the 4th feedback module
End.
7. subtraction count device as claimed in claim 3, which is characterized in that the 7th feedback module is third XOR gate；
Second input terminal of the first input end of the third XOR gate and the third XOR gate is respectively the 7th feedback
Second input terminal of the first input end of module and the 7th feedback module, the output end of the third XOR gate are described the
The output end of seven feedback modules.
8. a kind of inverse timing device comprising subtraction count device as claimed in claim 3, which is characterized in that the inverse timing device
Include:
For generating the time signal generation module of the time signal of 60 systems；
Connect with the time signal generation module, for carrying out assignment according to the time signal, and according to pulse signal and
Switch control signal carries out 60 system subtraction counts to the time signal to generate the subtraction count device of display signal；
It is connect with the subtraction count device, the display module that the display signal is shown.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820447277.2U CN208239821U (en) | 2018-03-30 | 2018-03-30 | Time signal assignment circuit, subtraction count device and inverse timing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820447277.2U CN208239821U (en) | 2018-03-30 | 2018-03-30 | Time signal assignment circuit, subtraction count device and inverse timing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208239821U true CN208239821U (en) | 2018-12-14 |
Family
ID=64585340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820447277.2U Active CN208239821U (en) | 2018-03-30 | 2018-03-30 | Time signal assignment circuit, subtraction count device and inverse timing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208239821U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108333915A (en) * | 2018-03-30 | 2018-07-27 | 宗仁科技(平潭)有限公司 | Time signal assignment circuit, subtraction count device and inverse timing device |
-
2018
- 2018-03-30 CN CN201820447277.2U patent/CN208239821U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108333915A (en) * | 2018-03-30 | 2018-07-27 | 宗仁科技(平潭)有限公司 | Time signal assignment circuit, subtraction count device and inverse timing device |
| CN108333915B (en) * | 2018-03-30 | 2023-05-23 | 宗仁科技(平潭)有限公司 | Time signal assignment circuit, down counter and countdown device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103809730B (en) | A kind of low-power consumption wearable device system | |
| US7594126B2 (en) | Processor system and method for reducing power consumption in idle mode | |
| CN103984274B (en) | Digital power gating integrated circuit and method | |
| US3664118A (en) | Electronically controlled timepiece using low power mos transistor circuitry | |
| CN208239821U (en) | Time signal assignment circuit, subtraction count device and inverse timing device | |
| JPH06502264A (en) | Dynamically switchable multi-frequency clock generator | |
| CN106486110B (en) | It is a kind of to support voice real-time decomposition/synthesis gamma bandpass filter group chip system | |
| CN103329064A (en) | Control system | |
| CN108333915A (en) | Time signal assignment circuit, subtraction count device and inverse timing device | |
| CN102034437B (en) | Integrated circuit device and electronic apparatus | |
| CN208335053U (en) | A kind of pulse signal generator | |
| CN102290020B (en) | Digital tube driving chip and household appliance using chip | |
| CN210986064U (en) | T trigger circuit with asynchronous reset | |
| CN105869595B (en) | A kind of display driving system and liquid crystal display | |
| CN111158758B (en) | Method and device for waking up central processing unit | |
| CN210986160U (en) | Mobile phone awakening screen locking structure | |
| JP3878264B2 (en) | Interface device for digital / analog converter | |
| CN105141295A (en) | Self-calibration circuit of built-in clock | |
| CN205899431U (en) | Function signal generator based on singlechip | |
| CN201917900U (en) | Calculator circuit | |
| CN2711801Y (en) | Refreshing time sequence signal generator | |
| TWI284457B (en) | State machine, counter and related method for gating redundant triggering clocks according to initial state | |
| CN108170021A (en) | A kind of electronic watch driving circuit and electronic watch | |
| CN216930002U (en) | Counter and counting chip | |
| CN102035515B (en) | Pulse density modulator for time division-synchronization code division multiple access (TD-SCDMA) and 4G terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 350400 area B, 6th floor, building 17, Taiwan Pioneer Park, beicuo Town, Pingtan County, Fuzhou City, Fujian Province Patentee after: Zongren Technology (Pingtan) Co.,Ltd. Address before: 350400 area B, 6th floor, building 17, Taiwan Pioneer Park, beicuo Town, Pingtan County, Fuzhou City, Fujian Province Patentee before: ZONGREN TECHNOLOGY (PINGTAN) Co.,Ltd. |