CN208208342U - Semiconductor memory cyclic redundancy check device and semiconductor memory - Google Patents
Semiconductor memory cyclic redundancy check device and semiconductor memory Download PDFInfo
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- CN208208342U CN208208342U CN201820593443.XU CN201820593443U CN208208342U CN 208208342 U CN208208342 U CN 208208342U CN 201820593443 U CN201820593443 U CN 201820593443U CN 208208342 U CN208208342 U CN 208208342U
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Abstract
The utility model embodiment discloses the cyclic redundancy check device and semiconductor memory of a kind of semiconductor memory.Cyclic redundancy check device includes storage control, carries out write operation and generation the first verification reading order for providing the first frame check sequence and the first data block；Checking circuit receives after the first data block is performed write operation and is transmitted to the second data block and the first frame check sequence of checking circuit formation, and generates cyclic redundancy check result；Output control circuit is used to generate output order and second clock signal respectively according to the first verification reading order and the first clock signal；Buffer circuit is used to export cyclic redundancy check result according to output order；Output circuit is for receiving second clock signal and exporting cyclic redundancy check result according to second clock signal, so that the clock periodicity postponed at the time of cyclic redundancy check result is exported from output circuit relative to the first verification reading order is the first preset value, the first preset value is the positive integer greater than 1.
Description
Technical field
The utility model relates to semiconductor memory technologies field, in particular to a kind of cyclic redundancy of semiconductor memory
Calibration equipment and semiconductor memory.
Background technique
The cyclic redundancy check for ZQ data block of traditional dynamic random access memory exports cyclic redundancy check
As a result mode is asynchronous mode, when cyclic redundancy check malfunctions as the result is shown, can only know it is in which a period of time
ZQ data block malfunctions in write operation or transmission, therefore the controller of dynamic random access memory was needed this period
All ZQ data blocks re-start write operation, cause the efficiency of dynamic random access memory write-in error correction lower, Bu Nengshi
The demand for answering dynamic random access memory to develop, wherein ZQ data block includes the data block of the input of data signal input.
Therefore, the error correction efficiency for how improving the cyclic redundancy check of the ZQ data block of dynamic random access memory is
Those skilled in the art are badly in need of technical problems to be solved.
Disclosed above- mentioned information are only used for reinforcing the understanding to the background of the utility model in the background technology, therefore it can
It can include the information for not being formed as the prior art that those of ordinary skill in the art are known.
Utility model content
In view of this, the utility model embodiment provides a kind of cyclic redundancy check device and half of semiconductor memory
Conductor memory, at least to solve technical problem present in background technique.
The technical solution of the utility model embodiment is achieved in that one embodiment according to the present utility model, mentions
Supply a kind of cyclic redundancy check device of semiconductor memory, comprising:
Storage control, for providing the first data block and generating the first frame check sequence according to first data block,
The storage control carries out write operation to first data block and for generating the first verification according to said write operation
Reading order；
Checking circuit is connect to receive after first data block is performed write operation and transmit with the storage control
The second data block and first frame check sequence formed to the checking circuit, wherein the checking circuit is according to
Second data block generates the second frame check sequence, and for checking sequence according to first frame check sequence and second frame
Column generate cyclic redundancy check result；
Output control circuit, connect with the storage control with receive the first verification reading order and with first school
The first synchronous clock signal of reading order is tested, the output control circuit is used for according to the first verification reading order and institute
It states the first clock signal and generates output order and second clock signal respectively；
Buffer circuit is connect respectively to store the cyclic redundancy school with the checking circuit and the output control circuit
It tests result and receives the output order, the buffer circuit is used to export the cyclic redundancy check according to the output order
As a result；And
Output circuit is connect respectively with the buffer circuit and the output control circuit to receive by the buffer circuit
The second clock signal that the cyclic redundancy check result of output and reception are exported by the output control circuit, it is described defeated
Circuit is used to export the cyclic redundancy check as a result, so that the cyclic redundancy check knot according to the second clock signal out
Clock periodicity at the time of fruit exports from the output circuit relative to the first verification reading order delay is first pre-
If value, first preset value is the positive integer greater than 1.
As a kind of optional mode, clock week of the first verification reading order relative to said write operating delay
Issue is the second preset value, so as to write at the time of the cyclic redundancy check result is exported from the output circuit relative to described
The clock periodicity for entering operating delay is the sum of the second preset value and the first preset value, and second preset value is just greater than 1
Integer.
As a kind of optional mode, the output control circuit includes:
Delay locked-loop circuit is connect to receive and read command synchronization with first verification with the storage control
First clock signal simultaneously generates third clock signal, and is connect with the output circuit by delay line, to postpone the third
Clock signal generates the second clock signal；
Wherein, the third clock signal shifts to an earlier date at the first time than the first clock signal phase, and the first time is equal to
The third clock signal is transmitted to the time of the output end of the output circuit through the delay line.
As a kind of optional mode, the delay locked-loop circuit is also used for the third clock signal synchronization institute
The first verification reading order is stated to form the second verification reading order；
The output control circuit further include:
Delay circuit is connect to receive the second verification reading order, the delay with the delay locked-loop circuit
Circuit is used to that the second verification reading order to be postponed the second time generation third verification according to first preset value to read
Order；And
Output order generation circuit is connect to receive the third verification reading order, and institute with the delay circuit
Output order generation circuit is stated to connect with the buffer circuit；The output order generation circuit is used for according to receiving
Third verifies reading order and generates the output order, and the output order is exported to the buffer circuit；
Wherein, second time is (the first preset value -1/K) a clock cycle, and K is the natural number greater than 1 and 1/K
Clock cycle, which is greater than from the delay circuit output third verification reading order with the output circuit, receives described follow
Time difference between ring redundancy check result.
Another embodiment according to the present utility model provides a kind of semiconductor memory, including any of the above-described described
Cyclic redundancy check device, the storage control of the cyclic redundancy check device also connect with external central processing unit with
Receive first data block；
The storage control is also connect to receive the cyclic redundancy check as a result, for basis with the output circuit
The cyclic redundancy check result executes write operation to first data block again.
The cyclic redundancy check device of the semiconductor memory of the utility model embodiment includes storage control, verification electricity
Road, output control circuit, buffer circuit and output circuit.Checking circuit with storage control and caching circuit connection, is deposited respectively
Storage controller provides the first frame check sequence and carries out write operation to first data block and provide said write operation production
The first raw verification reading order, in this way, after checking circuit is performed write operation according to first data block received
It is transmitted to the second data block that the checking circuit is formed and generates the second frame check sequence, and according to first frame check sequence
Cyclic redundancy check is generated as a result, buffer circuit stores the cyclic redundancy check result with second frame check sequence.In this way,
Just cyclic redundancy check result has been stored in buffer circuit.Output circuit and caching circuit connection, output control circuit point
It is not connect with buffer circuit and output circuit, output control circuit is connect to receive the first verification reading order with storage control
With the first clock signal for reading command synchronization with the first verification, it is used for according to the first clock signal and the first verification reading order
Output order and second clock signal are generated respectively, and buffer circuit stores cyclic redundancy check as a result, and defeated according to output order
Out, output circuit receives cyclic redundancy check result and second clock signal and exports cyclic redundancy according to second clock signal
Check results, so that relative to first check read at the time of cyclic redundancy check result is exported from the output circuit
The clock periodicity for taking order to postpone is the first preset value, and the first preset value is the positive integer greater than 1.In this way, when in certain a period of time
It carves, the cyclic redundancy check of output circuit output the second data block and when the first data block difference as the result is shown then illustrates first
Data block malfunctions during write operation, and malfunction write operation it is corresponding first verification reading order be the moment it
The first preceding preset value clock cycle can accurately find the corresponding first verification reading order of write operation of error.
The cyclic redundancy check device of the semiconductor memory of the utility model embodiment can accurately find the write operation of error
Corresponding first verification reading order, it is very high to the efficiency of write operation error correction, adapt to the demand of semiconductor memory development.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the utility model is into one
Aspect, embodiment and the feature of step, which will be, to be readily apparent that.
Detailed description of the invention
In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to originally practical
Novel disclosed some embodiments, and should not be taken as the limitation to the scope of the utility model.
Fig. 1 is the schematic diagram of the cyclic redundancy check device of the semiconductor memory of the utility model embodiment；
Fig. 2 is the timing diagram of the example of the cyclic redundancy check device of semiconductor memory shown in FIG. 1.
Description of symbols:
100 storage controls,
200 checking circuits,
210 frame check sequence generation circuits,
220 comparison circuits,
300 output control circuits,
310 delay locked-loop circuits,
311 delay lines,
320 delay circuits,
330 output order generation circuits,
340 register circuits,
400 buffer circuits,
500 output circuits,
The output end of 510 output circuits,
520 output driving circuits,
600 input instruction generation circuitries.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present utility model, it can be modified by various different modes described real
Apply example.Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
Embodiment one
The utility model embodiment provides a kind of cyclic redundancy check device of semiconductor memory, such as Fig. 1 and Fig. 2 institute
Show, comprising:
Storage control 100 checks sequence for providing the first data block and generating first frame according to first data block
Column, storage control 100 carry out write operation to first data block and generate the first school for operating according to said write
Test reading order；
Checking circuit 200 is connect to receive first data block and be performed write operation with the storage control 100
It is transmitted to the second data block and first frame check sequence that the checking circuit is formed afterwards, wherein the checking circuit root
The second frame check sequence is generated according to second data block, and for according to first frame check sequence and second frame
Check that sequence generates cyclic redundancy check result；
Output control circuit 300, connect with the storage control 100 with receive the first verification reading order and with it is described
The first clock signal of command synchronization is read in first verification, and output control circuit 300 is used to read life according to first verification
It enables and first clock signal generates output order and second clock signal respectively；
Buffer circuit 400 is connect with the checking circuit 200 and the output control circuit 300 described to store respectively
Cyclic redundancy check result and reception output order, buffer circuit are used to export the cyclic redundancy school according to the output order
Test result；And
Output circuit 500 is connect respectively with the buffer circuit 400 and the output control circuit 300 to receive by institute
It states the cyclic redundancy check result of buffer circuit output and receives the second clock exported by the output control circuit
Signal, the output circuit are used to export the cyclic redundancy check as a result, so that described follow according to the second clock signal
Clock week at the time of ring redundancy check result is exported from the output circuit relative to the first verification reading order delay
Issue is the first preset value, and first preset value is the positive integer greater than 1.
The cyclic redundancy check device of the semiconductor memory of the utility model embodiment includes storage control, verification electricity
Road, output control circuit, buffer circuit and output circuit.Checking circuit with storage control and caching circuit connection, is deposited respectively
Storage controller provides the first frame check sequence and carries out write operation to first data block and provide said write operation production
The first raw verification reading order, in this way, after checking circuit is performed write operation according to first data block received
It is transmitted to the second data block that the checking circuit is formed and generates the second frame check sequence, and according to first frame check sequence
Cyclic redundancy check is generated as a result, buffer circuit stores the cyclic redundancy check result with second frame check sequence.In this way,
Just cyclic redundancy check result has been stored in buffer circuit.Output circuit and caching circuit connection, output control circuit point
It is not connect with buffer circuit and output circuit, output control circuit is connect to receive the first verification reading order with storage control
With the first clock signal for reading command synchronization with the first verification, it is used for according to the first clock signal and the first verification reading order
Output order and second clock signal are generated respectively, and buffer circuit storage cyclic redundancy check result is simultaneously defeated according to output order
Out, output circuit receives cyclic redundancy check result and second clock signal and exports cyclic redundancy according to second clock signal
Check results, so that relative to first check read at the time of cyclic redundancy check result is exported from the output circuit
The clock periodicity for taking order to postpone is the first preset value, and the first preset value is the positive integer greater than 1.In this way, when in certain a period of time
It carves, the cyclic redundancy check of output circuit output the second data block and when the first data block difference as the result is shown then illustrates first
Data block malfunctions during write operation, and malfunction write operation it is corresponding first verification reading order be the moment it
The first preceding preset value clock cycle can accurately find the corresponding first verification reading order of write operation of error.
The cyclic redundancy check device of the semiconductor memory of the utility model embodiment can accurately find the write operation of error
Corresponding first verification reading order, it is very high to the efficiency of write operation error correction, adapt to the demand of semiconductor memory development.
About the first data block, including at least the data block of data signal input input.In Fig. 2, the first preset value
It is 6, the clock cycle postponed at the time of cyclic redundancy check result is exported from output circuit relative to the first verification reading order
Number is the first preset value.
It is determining for verifying reading order relative to the clock cycle of said write operating delay about first.I.e. described
One verification reading order is the second preset value relative to the clock periodicity of said write operating delay, so that the cyclic redundancy
It is default for second relative to the clock periodicity of said write operating delay at the time of check results are exported from the output circuit
The sum of value and the first preset value, second preset value are the positive integer greater than 1.In Fig. 2, the second preset value is 4.
Since the first verification reading order is determining relative to the clock cycle of said write operating delay, in this way, working as
At a time, the cyclic redundancy check of output circuit output the second data block and when the first data block difference as the result is shown, then
Illustrate that the first data block malfunctions during write operation, and malfunction write operation be the moment before the first preset value and
The first data block of the sum of second preset value clock cycle can accurately find the first data block of write operation error, because
This semiconductor memory only needs the first data block of error re-starting write operation.The utility model embodiment
The cyclic redundancy check device of semiconductor memory can accurately find the first data of error, to write operation error correction
Efficiency is very high, adapts to the demand of semiconductor memory development.
In order to realize at the time of cyclic redundancy check result is exported from output circuit relative to the first verification reading order
The clock periodicity of delay is the first preset value.As depicted in figs. 1 and 2, the needs of output control circuit 300 include:
Delay locked-loop circuit 310 is connect to receive and the first verification reading order with the storage control 100
The first synchronous clock signal simultaneously generates third clock signal, and is connect with the output circuit 500 by delay line 311, with
Postpone the third clock signal and generates the second clock signal；
Wherein, the third clock signal shifts to an earlier date at the first time than the first clock signal phase, and the first time is equal to
The third clock signal is transmitted to the time of the output end 510 of the output circuit through the delay line.
The clock cycle of the first clock signal where write operation is defined as to first clock of the first clock signal
Period, the first preset value indicate that the second preset value is indicated with n with m, and the time for postponing wire delay uses t1It indicates, output circuit prolongs
The slow time uses t2In the case where expression, then the first verification reading order is the nth clock period of the first clock signal, third
It is t that clock signal phase, which was shifted to an earlier date in the time of the first clock signal,1+t2, and then the m+n+1 clock week of third clock signal
The m+n+1 clock cycle of second clock signal is generated after phase delayed wire delay, at the m+n+1 of second clock signal
The clock period shifts to an earlier date t relative to the m+n+1 clock phases of the first clock signal2Time reaches output circuit, when second
Cyclic redundancy check check results in clock signal control output circuit start to export, and output circuit exports cyclic redundancy check knot
Time needed for fruit is exactly t2, cyclic redundancy school at the time of cyclic redundancy check result is exported from output circuit just may be implemented
It is m that result, which is tested, relative to the clock periodicity of the first clock signal delay, due to the first verification reading order and the first clock letter
Number synchronization exactly realizes that cyclic redundancy check result is relative to write-in at the time of cyclic redundancy check result is exported from output circuit
The clock periodicity of operating delay is the sum of the first preset value and the second preset value.In Fig. 2, third clock signal phase shifts to an earlier date
It is 1/4 clock cycle in the time of the first clock signal.
Cyclic redundancy check result is relative to the at the time of in order to realize that cyclic redundancy check result is exported from output circuit
The clock periodicity of one verification reading order delay is the first preset value, when needing to guarantee the m+n+1 of second clock signal
When the clock period reaches output circuit, for cyclic redundancy check result in output circuit, therefore, it is necessary to export to buffer circuit
Cyclic redundancy check result to the output circuit time is controlled.
It would be desirable therefore, as shown in Figure 1, delay locked-loop circuit 310 is also connect to receive the first school with storage control 100
Test reading order；Wherein, delay locked-loop circuit 310 be also used for third clock signal synchronization first verify reading order with
Form the second verification reading order；
Output control circuit 300 further includes delay circuit 320 and output order generation circuit 330；
Delay circuit 320 is connect to receive the second verification reading order, institute with the delay locked-loop circuit 310
Delay circuit is stated for the second verification reading order to be postponed the second time generation third school according to first preset value
Reading order is tested, and is exported to output order generation circuit 330；
Output order generation circuit 330 is connect to receive the third verification reading order with the delay circuit 320,
And the output order generation circuit 330 is connect with the buffer circuit 400；The output order generation circuit 330 is used for
The output order is generated according to the third verification reading order received, and the output order is exported to described slow
Deposit circuit 400；
Wherein, second time is (the first preset value -1/K) a clock cycle, and K is the natural number greater than 1 and 1/K
Clock cycle, which is greater than from the delay circuit output third verification reading order with the output circuit, receives described follow
Time difference between ring redundancy check result.In Fig. 2,1/K clock cycle is 1/2 clock cycle.
Due to the second verification reading order and third clock signal synchronization, then when third verifies reading order relative to third
The time of the delay of clock signal is also (the first preset value -1/K) a clock cycle, 1/K fewer than the first preset value clock cycle
The effect of a clock cycle is, 1/K clock cycle is to stay to do delay circuit output third and verify read command signal to defeated
Instruction generation circuitry out, output order generation circuit generate output order and export to buffer circuit, and buffer circuit receives output
The time that cyclic redundancy check result reaches output circuit is exported after instruction；Meanwhile third clock signal be again phase in advance in
First clock signal, in this way, it is ensured that the time that cyclic redundancy check result reaches output circuit is earlier than second clock
The m+n+1 clock cycle of signal reaches the time of output circuit.
In order to realize that output control circuit obtains the first preset value, as shown in Figure 1, output control circuit 300 further includes posting
Latch circuit 340, delay circuit 320 connect default with the first of the offer of receiving register circuit 340 with register circuit 340
Value.
It needs to export the time service of cyclic redundancy check result in output circuit to realize, it is superfluous not to need output circulation
It is not worked when remaining check results to reach energy-efficient purpose.As shown in Figure 1, delay circuit 320 also needs and output circuit
500 connection；Wherein, delay circuit 320 is also used to generate output enable signal according to the second verification reading order and export extremely
Output circuit 500, output enable signal is significant level within a preset time, and output enable signal is read compared to the second verification
Order delay (the first preset value -1/L) a clock cycle, L is the natural number greater than 1 and L is less than K.In Fig. 2, output is enabled
Signal phase is in advance in output order, it is ensured that output order can centainly control buffer circuit output cyclic redundancy check knot
Fruit.
About the specific structure of output circuit, as shown in Figure 1, output circuit 500 includes output driving circuit 520 and connection
The output pin 510 of output driving circuit, output end 510 of the output pin as output circuit；
Output driving circuit 520 is connect to receive second clock signal with delay line 311, output driving circuit also with delay
Circuit 320 is connected to receive output enable signal, and output driving circuit is also connect to receive cyclic redundancy school with buffer circuit 400
Test result, wherein output driving circuit 520 is used for the control according to output enable signal and second clock signal, driving circulation
Redundancy check result is exported from output pin.
Specific structure about checking circuit is as follows: as shown in Figure 1, checking circuit 200 includes that frame check sequence generates electricity
Road 210 and comparison circuit 220；
Frame check sequence generation circuit 210 connect to receive second data block with the storage control and for producing
Raw second frame check sequence；
Comparison circuit 220 is connect to receive first frame check sequence, and the comparison with the storage control 100
Circuit 220 is connect to receive second frame check sequence with the frame check sequence generation circuit 210；The comparison circuit
220 for generating the cyclic redundancy check result and defeated according to first frame check sequence and second frame check sequence
Out to the buffer circuit 400.
Checking circuit generates cyclic redundancy check result and needs the regular hour.
The cyclic redundancy check device of semiconductor memory is electric to caching by the storage of cyclic redundancy check result in order to realize
Road.As shown in Figure 1, the cyclic redundancy check device of semiconductor memory also need include:
Input instruction generation circuitry 600, connect with checking circuit 200 to receive the first verification reading order, and with caching
Circuit 400 connects；Wherein, the input instruction generation circuitry 600 is used to generate input according to the first verification reading order
Instruct and be output to the buffer circuit 400, to store the circulation superfluous for controlling the buffer circuit 400 for the input instruction
Remaining check results.
After the generation of cyclic redundancy check result, cyclic redundancy check result is stored in by buffer circuit by input instruction
In.
Specifically, buffer circuit is the buffer circuit of first in, first out, corresponding, input instruction generation circuitry is first in, first out
The input instruction generation circuitry of instruction is inputted, output order generation circuit is that the output order of first in, first out input instruction generates electricity
Road.
Embodiment two
The utility model embodiment provides a kind of semiconductor memory, the cyclic redundancy check dress including embodiment one
It sets, the storage control of the cyclic redundancy check device is also connect with external central processing unit to receive first data
Block；
The storage control is also connect to receive the cyclic redundancy check as a result, for basis with the output circuit
The cyclic redundancy check result executes write operation to first data block again.
In the description of the utility model and embodiment, it is to be understood that term "top", "bottom", " height " etc. refer to
The orientation or positional relationship shown be based on the orientation or positional relationship shown in the drawings, be merely for convenience of description the utility model and
Simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation, with specific orientation construction
And operation, therefore should not be understood as limiting the present invention.
In the utility model and embodiment unless specifically defined or limited otherwise, term " setting ", " installation ",
The terms such as " connected ", " connection ", " fixation " shall be understood in a broad sense, for example, it may be being fixedly connected, be also possible to detachably connect
It connects, or integral；It can be mechanical connection, be also possible to be electrically connected, can also be communication；It can be directly connected, it can also be with
Indirectly connected through an intermediary, the connection inside two elements or the interaction relationship of two elements be can be.For this
For the those of ordinary skill in field, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the utility model and embodiment unless specifically defined or limited otherwise, fisrt feature is in second feature
"upper" or "lower" may include that the first and second features directly contact, may include the first and second features be not direct yet
It contacts but by the other characterisation contact between them.Moreover, fisrt feature second feature " on ", " side " and " on
Face " includes fisrt feature right above second feature and oblique upper, or to be merely representative of first feature horizontal height special higher than second
Sign.Fisrt feature under the second feature " below ", " below " and " below " include fisrt feature right above second feature and tiltedly on
Side, or first feature horizontal height is merely representative of less than second feature.
Above disclosure provides many different embodiments or example is used to realize the different structure of the utility model.
In order to simplify the disclosure of the utility model, above the component of specific examples and setting are described.Certainly, they are only
Example, and purpose does not lie in limitation the utility model.In addition, the utility model can in different examples repeat reference numerals
And/or reference letter, this repetition are for purposes of simplicity and clarity, itself not indicate discussed various embodiments
And/or the relationship between setting.In addition, the example of various specific techniques and material that the utility model provides, but this
Field those of ordinary skill can be appreciated that the application of other techniques and/or the use of other materials.
Above description is only a specific implementation of the present invention, but the protection scope of the utility model is not limited to
In this, anyone skilled in the art within the technical scope disclosed by the utility model, it is each can to readily occur in it
Kind change or replacement, these should be covered within the scope of the utility model.Therefore, the protection scope of the utility model
It should be based on the protection scope of the described claims.
Claims (12)
1. a kind of cyclic redundancy check device of semiconductor memory characterized by comprising
Storage control, it is described for providing the first data block and generating the first frame check sequence according to first data block
Storage control carries out write operation to first data block and reads for generating the first verification according to said write operation
Order；
Checking circuit, connect to be performed after write operation to receive first data block with the storage control and is transmitted to institute
State the second data block and first frame check sequence of checking circuit formation, wherein the checking circuit is according to described second
Data block generates the second frame check sequence, and for being produced according to first frame check sequence and second frame check sequence
Raw cyclic redundancy check result；
Output control circuit, connect with the storage control with receive the first verification reading order and with first check read
Take the first clock signal of command synchronization, the output control circuit is used for according to the first verification reading order and described the
One clock signal generates output order and second clock signal respectively；
Buffer circuit is connect respectively to store the cyclic redundancy check knot with the checking circuit and the output control circuit
Fruit and the reception output order, the buffer circuit are used to export the cyclic redundancy check knot according to the output order
Fruit；And
Output circuit is connect respectively with the buffer circuit and the output control circuit to receive and be exported by the buffer circuit
Cyclic redundancy check result and receive the second clock signal that is exported by the output control circuit, the output is electric
Road be used to export the cyclic redundancy check according to the second clock signal as a result, so that the cyclic redundancy check result from
The clock periodicity at the time of output circuit exports relative to the first verification reading order delay is the first preset value,
First preset value is the positive integer greater than 1.
2. the cyclic redundancy check device of semiconductor memory according to claim 1, which is characterized in that first school
Testing the clock periodicity that reading order postpones relative to write operation is the second preset value, so that the cyclic redundancy check result
It is the second preset value and first from clock periodicity at the time of output circuit output relative to said write operating delay
The sum of preset value, second preset value are the positive integer greater than 1.
3. the cyclic redundancy check device of semiconductor memory according to claim 2, which is characterized in that the output control
Circuit processed includes:
Delay locked-loop circuit is connect to receive and read the first of command synchronization with first verification with the storage control
Clock signal simultaneously generates third clock signal, and is connect with the output circuit by delay line, to postpone the third clock
Signal generates the second clock signal；
Wherein, the third clock signal shifts to an earlier date at the first time than the first clock signal phase, and the first time is equal to described
Third clock signal is transmitted to the time of the output end of the output circuit through the delay line.
4. the cyclic redundancy check device of semiconductor memory according to claim 3, which is characterized in that the delay lock
Phase loop circuit is also used for the first verification reading order described in the third clock signal synchronization to form the second verification reading
Order；
The output control circuit further include:
Delay circuit is connect to receive the second verification reading order, the delay circuit with the delay locked-loop circuit
Reading order is verified for the second verification reading order to be postponed the second time generation third according to first preset value；
And
Output order generation circuit is connect to receive the third verification reading order with the delay circuit, and described defeated
Instruction generation circuitry is connect with the buffer circuit out；The output order generation circuit is used for according to the third received
It verifies reading order and generates the output order, and the output order is exported to the buffer circuit；
Wherein, second time is M1 clock cycle, and the first preset value of M1=-1/K, K are the natural number and 1/K greater than 1
A clock cycle is described greater than receiving from the delay circuit output third verification reading order and the output circuit
Time difference between cyclic redundancy check result.
5. the cyclic redundancy check device of semiconductor memory according to claim 4, which is characterized in that the output control
Circuit processed further includes register circuit, and the delay circuit is connect to receive by the register circuit with the register circuit
First preset value provided.
6. the cyclic redundancy check device of semiconductor memory according to claim 4, which is characterized in that the deferred telegram
Road is also used to generate output enable signal according to the second verification reading order and export to the output circuit, the output
Enable signal is significant level within a preset time, wherein the output enable signal reads life compared to second verification
Enable the M2 clock cycle of delay；Wherein, the first preset value of M2=-1/L, L are the natural number greater than 1 and L is less than K.
7. the cyclic redundancy check device of semiconductor memory according to claim 6, which is characterized in that the output electricity
Road includes output driving circuit and the output pin for connecting the output driving circuit, and the output pin is as the output electricity
The output end on road；
The output driving circuit is connect to receive the second clock signal with the delay line, and the output driving circuit is also
It is connect with the delay circuit to receive the output enable signal, the output driving circuit is also connect with the buffer circuit
To receive the cyclic redundancy check result, wherein the output driving circuit is used for according to the output enable signal and institute
The control for stating second clock signal drives the cyclic redundancy check result to export from the output pin.
8. the cyclic redundancy check device of semiconductor memory according to claim 2, which is characterized in that the verification electricity
Road includes:
Frame check sequence generation circuit is connect to receive second data block and for generating second with the storage control
Frame check sequence；
Comparison circuit is connect to receive first frame check sequence, and the comparison circuit and institute with the storage control
The connection of frame check sequence generation circuit is stated to receive second frame check sequence；The comparison circuit is used for according to described first
Frame check sequence and second frame check sequence generate the cyclic redundancy check result and export to the buffer circuit.
9. the cyclic redundancy check device of semiconductor memory according to claim 1, which is characterized in that further include:
Instruction generation circuitry is inputted, is connect with the storage control to receive the first verification reading order；Wherein, described
Input instruction generation circuitry, which is used to generate input according to the first verification reading order, instructs and is output to the buffer circuit,
The input instruction stores the cyclic redundancy check result for controlling the buffer circuit.
10. the cyclic redundancy check device of semiconductor memory according to claim 9, which is characterized in that the caching
Circuit is the buffer circuit of first in, first out, and the input instruction generation circuitry is that the input instruction of first in, first out input instruction generates
Circuit.
11. the cyclic redundancy check device of semiconductor memory according to claim 1, which is characterized in that described first
Data block includes at least the data block of data signal input input.
12. a kind of semiconductor memory, which is characterized in that including any cyclic redundancy school of the claims 1 to 11
Experiment device, the storage control of the cyclic redundancy check device are also connect with external central processing unit to receive described first
Data block；
The storage control is also connect to receive the cyclic redundancy check as a result, for according to the output circuit
Cyclic redundancy check result executes write operation to first data block again.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108288489A (en) * | 2018-04-24 | 2018-07-17 | 睿力集成电路有限公司 | Semiconductor memory cyclic redundancy check device and semiconductor memory |
| WO2022205703A1 (en) * | 2021-04-01 | 2022-10-06 | 长鑫存储技术有限公司 | Semiconductor memory and data writing method |
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2018
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108288489A (en) * | 2018-04-24 | 2018-07-17 | 睿力集成电路有限公司 | Semiconductor memory cyclic redundancy check device and semiconductor memory |
| WO2022205703A1 (en) * | 2021-04-01 | 2022-10-06 | 长鑫存储技术有限公司 | Semiconductor memory and data writing method |
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Effective date of registration: 20191106 Address after: 200336 unit 801, 802, 805, building 1, 1438 Hongqiao Road, Changning District, Shanghai (9th floor, nominal floor) Patentee after: Changxin storage technology (Shanghai) Co., Ltd Address before: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Changxin Storage Technology Co., Ltd. |