CN208127209U - Integrated circuit memory and semiconductor device - Google Patents
Integrated circuit memory and semiconductor device Download PDFInfo
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- CN208127209U CN208127209U CN201820687274.6U CN201820687274U CN208127209U CN 208127209 U CN208127209 U CN 208127209U CN 201820687274 U CN201820687274 U CN 201820687274U CN 208127209 U CN208127209 U CN 208127209U
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Abstract
The utility model provides a kind of integrated circuit memory and semiconductor device.It uses and is vertically arranged active cylinder on substrate to constitute vertical memory transistor, to be conducive to reduce the unit configuration sized of vertical memory transistor on substrate, and then can further reduce the size of integrated circuit memory.Also, the vertical memory transistor of vertical structure has preferably arrangement flexibility, such as can be realized multiple vertical memory transistors is in that six sides are densely arranged, to improve the arrangement closeness of storage unit in integrated circuit memory.
Description
Technical field
The utility model relates to technical field of semiconductors, in particular to a kind of integrated circuit memory, and one kind are partly led
Body integrated circuit device.
Background technique
Semiconductor devices becomes small, keeps its more compact to be suitble to mobile computing to use, and can consume less energy, allows
The service time of battery of charging room is extended.And as the reduction of dimensions of semiconductor devices can also be correspondingly improved circuit
Closeness, to make semiconductor devices that can there is more powerful computing capability.
However, technology development now is constantly subjected to the limitation of the resolution of obtainable lithography apparatus at that time.Specifically
It says, the size of semiconductor devices, such as the minimum dimension of line width CD (Critical Dimension) and line-spacing S (spaces) takes
Certainly in the analytic ability of lithography apparatus, therefore, under the limitation of the minimum feature size obtained by lithography apparatus, it is less than minimum special
The figure of sign size can not be obtained steadily.This will limit the further reduction of dimensions of semiconductor devices, and can not improve again
The arrangement closeness of unit components in semiconductor devices.
For memory (for example, dynamic RAM DRAM), storage unit include memory transistor and with
Connection memory element.Source region, channel region and the drain region of the memory transistor are along the direction water for being parallel to substrate surface
Divide cloth equally, in the case where the memory transistor normally of the storage unit, channel current is generally along level side
It circulates between source region and drain region.So, when the memory transistor is reduced to predetermined size, it is brilliant that storage will easily be generated
The short-channel effect of body pipe.As it can be seen that the size of existing memory is not only limited by the resolution of lithography apparatus, simultaneously also
Need to consider size reduction brought short-channel effect later.
Utility model content
The purpose of this utility model is to provide a kind of integrated circuit memories, to reduce the size of integrated circuit memory
And it can be improved the arrangement concentration of storage unit in integrated circuit memory.
In order to solve the above technical problems, the utility model provides a kind of integrated circuit memory, including：
One substrate；
Multiple bit lines, formation extend over the substrate and along a first direction；
Multiple active cylinders, are formed on the bit line, so that the bottom end of the active cylinder is connected to the bit line；
A plurality of wordline forms over the substrate and extends along second direction, and the wordline connects in their extension direction
It is connected to grid tube, around the lateral wall of corresponding active cylinder, the top of the active cylinder exposes to described the grid tube
Grid tube is collectively formed the vertical memory transistor of the integrated circuit memory by the active cylinder and the grid tube.
Optionally, the unit of the vertical memory transistor of the integrated circuit memory over the substrate configures ruler
It is very little more than or equal to minimum feature size square 4 times.
Optionally, the integrated circuit memory further includes a memory element, and the integrated circuit memory further includes：It is more
A memory element is formed in the top of the vertical memory transistor, and electrically connects with the top end part of the active cylinder
It connects.
Optionally, it is formed with the first doped region in the bottom end of the active cylinder, be connected on the bit line, institute
It states in the top end part of active cylinder and is formed with the second doped region, to connect memory element, first doped region and institute
State drain region and source region that the second doped region respectively constitutes the vertical memory transistor.
Optionally, the integrated circuit memory further includes：One insulating medium layer is formed over the substrate, described exhausted
Edge dielectric layer fills the gap between the adjacent bit line and covers the bit line, and the wordline is formed in the dielectric
On layer.
Optionally, the insulating medium layer is also around the member base end portion of the active cylinder；Also, the dielectric
The top surface of layer is higher than the top surface of the bit line, and the top boundary of first doped region lower than the active cylinder.
Optionally, the top surface of the grid tube is lower than the top surface of the active cylinder, and is higher than the active cylinder
Second doped region bottom boundary.
Optionally, the integrated circuit memory further includes：One spacer dielectric layer forms over the substrate and fills phase
Gap between the adjacent wordline.
Optionally, the wordline includes grid tube and connecting line portion, and the grid tube surround the side wall of the active cylinder,
The connecting line portion is used to connect the grid tube on the adjacent active cylinder, and the top surface in the connecting line portion
Lower than the top surface of the grid tube；Wherein, the spacer dielectric layer further covers the connecting line portion, and extends over institute
State the side wall of grid tube.
Optionally, the shape of the active cylinder includes cylindrical body.
Optionally, a plurality of wordline and a plurality of bit line space intersection and there are multiple overlapping regions, one overlapping
Region corresponds to an active cylinder, the medium six active cylinders away from adjacent same active cylinder of multiple active cylinders
The arrangement of six square arrays is presented.
Optionally, the integrated circuit memory further includes：One spacer dielectric layer forms over the substrate and fills phase
Gap between the adjacent grid tube.
Optionally, the wordline includes the connecting line portion of multiple connection grid tubes, connecting line portion regular linear
The grid tube on the adjacent active cylinder is connected, and the top surface in the connecting line portion is lower than the grid tube
Top surface；Wherein, the spacer dielectric layer further covers the connecting line portion, and extends over the side wall of the grid tube.
Optionally, the extending direction in the connecting line portion of wordline projection image over the substrate and institute's rheme
Line intersects and has an angle, and the angle of the angle is between 50 °~70 °.
Based on integrated circuit memory as described above, the utility model additionally provides a kind of semiconductor devices, including：
One substrate；
A plurality of first call wire, formation extend over the substrate and along a first direction；
Multiple active cylinders are formed on first call wire, so that the bottom end of the active cylinder is connected to institute
It states on the first call wire；And
A plurality of second call wire forms over the substrate and extends along second direction, and second call wire is at it
Around the side wall of corresponding active cylinder on extending direction, multiple corresponding active cylinders are connected to extend.
In integrated circuit memory provided by the utility model, constituted using the active cylinder being vertically arranged on substrate
The active area of vertical memory transistor, and the bottom end of active cylinder can be made using the bit line being located at below active cylinder
It can be drawn from the bottom of active cylinder, and combine the grid tube for being surrounded with source cylinder lateral wall, be capable of forming vertical structure
Vertical memory transistor (that is, source region, channel region and drain region are arranged vertically along short transverse).The vertical storage of vertical structure
Transistor, unit configuration sized on substrate are smaller (for example, unit configuration sized can reach 4F2), therefore can be corresponding
The size for making integrated circuit memory further decrease.Also, active area is constituted using active cylinder, additionally it is possible to further drop
The risk of short-channel effect occurs for low memory transistor, avoids the occurrence of reduction of the transistor due to its size of such as horizontal structure
And the problem of being easy to happen short-channel effect.Meanwhile the memory transistor of vertical structure is also equipped with preferably arrangement flexibility, from
And it is advantageously implemented the densely arranged of multiple vertical memory transistors.For example, multiple vertical memory transistors can be made close in six sides
Collection arrangement, making multiple storage units in integrated circuit memory accordingly is also in that six sides are densely arranged.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of integrated circuit memory；
Fig. 2 a is the top view of the integrated circuit memory in the utility model embodiment one；
Fig. 2 b is that the integrated circuit memory in the utility model embodiment one omits the structural representation after its memory element
Figure；
Fig. 3 a is section of the integrated circuit memory in the utility model embodiment one shown in Fig. 2 a along the direction aa '
Schematic diagram；
Fig. 3 b is the integrated circuit memory of the utility model embodiment one kind shown in Fig. 2 a along the section in the direction bb '
Schematic diagram；
Fig. 3 c is integrated circuit memory its two neighboring vertical memory transistor in the utility model embodiment one
Partial enlarged view；
Fig. 4 is the flow diagram of the forming method of the integrated circuit memory in the utility model embodiment two；
Fig. 5 a is the forming method of the integrated circuit memory in the utility model embodiment two in its execution step S100
When top view；
Fig. 5 b is the forming method of the integrated circuit memory in the utility model embodiment two in its execution step S100
When diagrammatic cross-section；
Fig. 6 a is the forming method of the integrated circuit memory in the utility model embodiment two in its execution step S200
When top view；
Fig. 6 b~Fig. 6 d is that the forming method of the integrated circuit memory in the utility model embodiment two executes step at it
Diagrammatic cross-section when rapid S200；
Fig. 7 a is the forming method of the integrated circuit memory in the utility model embodiment two in its execution step S201
When top view；
Fig. 7 b is the forming method of the integrated circuit memory in the utility model embodiment two in its execution step S201
When diagrammatic cross-section；
Fig. 8 a~Fig. 9 a is that the forming method of the integrated circuit memory in the utility model embodiment two executes step at it
Top view when rapid S300；
Fig. 8 b~Fig. 8 c and Fig. 9 b is the forming method of the integrated circuit memory in the utility model embodiment two at it
Execute diagrammatic cross-section when step S300.
Wherein, appended drawing reference is as follows：
10- active area；20- wordline；
30- bit line；
100- substrate；200- bit line；
The active cylinder of 300-；
The first doped region of 300D-；The second doped region of 300S-；
The bottom end 301-；The top end part 302-；
300M- sacrificial layer；
400- wordline；400a- conductive material layer；
410- gate work-function layer；410a- workfunction material；
420- grid conducting layer；420a- conductive material layer；
400G- grid tube；400L- connecting line portion；
400M- mask plate；400E- etching agent；
500- gate dielectric layer；600- insulating medium layer；
700- spacer dielectric layer；800- separation layer；
900- node contact layer；
H- through-hole；
θ-angle；
U- storage unit；
C- memory element；
The vertical memory transistor of T-；
D1- memory transistor is perpendicular to the width dimensions in bit line direction；
D2- memory transistor is perpendicular to the width dimensions on word-line direction.
Specific embodiment
As stated in the background art, in existing memory (for example, in dynamic RAM DRAM), memory transistor
For horizontal structure, to will limit the reduction of storage crystal pipe size, and the arrangement of memory transistor can not be further increased
Concentration.
Fig. 1 is a kind of structural schematic diagram of memory, and as described in Figure 1, the memory includes：
One substrate, definition has multiple active areas 10 in the substrate, and the active area 10 has one first doped region and position
Two the second doped regions in first doped region two sides；
A plurality of wordline 20 forms over the substrate and intersects with corresponding active area 10, in the wordline 20 with it is active
The part that area 10 intersects is used to constitute the grid tube of memory transistor；
Multiple bit lines 30 are formed over the substrate and are electrically connected with the first doped region of corresponding active area 10, with
Draw first doped region；And
As it can be seen that the active area 10 of memory transistor is formed in existing memory for horizontal proliferation, i.e. its first doping
Area and the second doped region are on the direction for be parallel to substrate surface in horizontal distribution, and then the storage for constituting horizontal structure is brilliant
Body pipe.
For memory transistor shown in FIG. 1, when reducing the size of memory transistor, i.e., make active area accordingly
10 size reduction, so will easily increase the risk of short-channel effect.In addition, even if not considering the short channel of memory transistor
Effect, however in the case where the resolution by lithography apparatus is limited, the size of the memory transistor still also can not be further
Reduction.
With specific reference to shown in Fig. 1, a memory transistor is being 3F perpendicular to the width dimensions D2 on 20 direction of wordline；With
And a memory transistor is being 2F perpendicular to the width dimensions D1 on 30 direction of bit line, therefore, memory transistor
It is 6F that the area for its configuration is needed on the substrate2(3F*2F), wherein F is minimum feature size.Namely based on existing
The unit configuration sized of the resolution of lithography apparatus, prepared memory transistor can only reach 6F2, and can not continue to contract
Subtract.
It should be noted that " minimum feature size F " described herein is：Based on the resolution of current lithography apparatus,
The least limit feature sizes and least limit pitch size that can be obtained.Wherein, least limit feature sizes and least limit
Pitch size is equal.
In addition, also needing additionally to prepare contact hole in the top of its active area in memory shown in FIG. 1, to utilize
The contact hole exposes second doped region of the active area 10.In this way, in subsequent technique, it can be in the lining
Memory element (for example, storage) is formed on bottom, the memory element can pass through the contact hole and the active area
Second doped region be electrically connected.As it can be seen that drawing second doped region so that it is formed by storage with subsequent
When element is electrically connected, need it is additional prepare contact hole, to keep preparation process more many and diverse.
For this purpose, the utility model provides a kind of integrated circuit memory, it is vertical to use in the integrated circuit memory
The active area that active cylinder on substrate replaces traditional horizontal proliferation is set, and bit line is arranged under active cylinder
Side, to realize that the bottom end of active cylinder is connected to bit line；And memory element can be with the top end part of the active cylinder
It is electrically connected, is further formed the storage unit of vertical structure.
That is, integrated circuit memory provided by the utility model, can not only further reduce the unit of memory transistor
Configuration sized, and also can effectively reduce the risk that short-channel effect occurs for the memory transistor after reduction；And vertical knot
The memory transistor of structure is also equipped with the more flexible characteristic of arrangement.
Below in conjunction with the drawings and specific embodiments to the utility model proposes integrated circuit memory and forming method thereof,
Semiconductor devices is described in further detail.According to following explanation, will be become apparent from feature the advantages of the utility model.It needs to illustrate
, attached drawing is all made of very simplified form and using non-accurate ratio, only conveniently, lucidly to aid in illustrating originally
The purpose of utility model embodiment.
Fig. 2 a is the top view of the integrated circuit memory in the utility model embodiment one, and Fig. 2 b is that the utility model is real
It applies the integrated circuit memory in example one and omits the structural schematic diagram after its memory element, Fig. 3 a is that this is practical new shown in Fig. 2 a
For integrated circuit memory in type embodiment one along the diagrammatic cross-section in the direction aa ', Fig. 3 b is that this is practical new shown in Fig. 2 a
For the integrated circuit memory of type embodiment one kind along the diagrammatic cross-section in the direction bb ', Fig. 3 c is the utility model embodiment one
In integrated circuit memory its two neighboring vertical memory transistor partial enlarged view.
In conjunction with shown in Fig. 2 a~Fig. 2 b and Fig. 3 a~Fig. 3 b, the integrated circuit memory includes a substrate 100, a plurality of position
Line 200, multiple active cylinders 300 and a plurality of wordline 400, wherein the wordline 400 is connected with grid in their extension direction
Pipe 400G.Also, the vertical storage of integrated circuit memory is collectively formed by the active cylinder 300 and the grid tube 400G
Transistor T.
Wherein, the substrate 100 such as can for silicon substrate or silicon-on-insulator (Silicon-On-Insulator,
SOI)。
The a plurality of bit line 200 is formed on the substrate 100, and is extended along a first direction.Wherein, the bit line
200 can be laminated construction, such as the bit line 200 includes the bit line separation layer that is sequentially stacked on the substrate 100 (in figure
Be not shown), bit line conductive layer (not shown), bit line work-function layer (not shown) and bit line contact layer (in figure not
It shows).Specifically, the material of the bit line separation layer is for example including silicon nitride (SiN), the material of institute's bit line conductive layer is for example
Including tungsten (W), material of the material of the bit line work-function layer for example including titanium nitride (TiN) and institute's bitline contact layer
For example including DOPOS doped polycrystalline silicon (Poly).
It should be noted that the doped polysilicon layer of institute's bitline contact layer, the conduction type of Doped ions can be according to vertical
The conduction type of formula memory transistor T adjusts accordingly, such as the conduction type of vertical memory transistor T is N-type, then institute's rheme
Doped polysilicon layer can also be n-type doping accordingly in line contact layer.
With continued reference to shown in Fig. 3 a and Fig. 3 b, multiple active cylinders 300 are formed on the bit line 200, so that described have
The bottom end 301 of source cylinder 300 is connected to the bit line 200.Wherein, the shape of the active cylinder 300 is, for example, cylindrical body.
In the present embodiment, the bottom end 301 of the active cylinder 300 is connect with the bit line contact layer of the bit line 200, since bit line connects
Contact layer can be the film layer doped with conductive ion, to can effectively reduce the electricity of the contact with the active cylinder 300 of bit line 200
Resistance, and then be conducive to reduce the leakage phenomenon of device.
With specific reference to shown in Fig. 3 c, the active cylinder 300 can be used for constituting the conducting channel of vertical memory transistor T,
Therefore the active cylinder 300 can be formed using channel material accordingly, for example, the material of active cylinder 300 includes indium arsenic
Change one of gallium (InGaAs) and GaAs (GaAs) or combinations thereof.In addition, two ends of the active cylinder 300 are also used
In the source region and drain region that form vertical memory transistor T, therefore may be used also in the bottom end 301 of the active cylinder 300
It is formed with the first doped region 300D, may also be formed with the second doped region in the top end part 302 of the active cylinder 300
300S, the first doped region 300D and the second doped region 300S can respectively constitute vertical memory transistor T drain region and
Source region.Wherein, the first doped region of corresponding conduction type can be set according to the conduction type of the vertical memory transistor T
300D and the second doped region 300S.
In the present embodiment, the vertical memory transistor T is N-type transistor, then the first doped region 300D and described
Second doped region 300D can be the doped region for being injected with arsenic (As) ion or phosphorus (P) ion accordingly.
A plurality of wordline 400 is formed on the substrate 100 and extends along second direction.In the present embodiment, the wordline
400 tilt extension relative to the bit line 200, thus the projection image of the extending direction of the wordline 400 over the substrate
It is formed by angle theta when with the bit line 200 intersection, angle for example can be between 50 °~70 °.In this way, to realize integrated circuit
Storage unit is densely arranged in memory.
Continuing with shown in Fig. 3 a, Fig. 3 b and Fig. 3 c, the wordline 400 is connected with grid tube in their extension direction
400G, the grid tube 400G surround the lateral wall of corresponding active cylinder 300, so that the extension connection of the wordline 400 is multiple
Corresponding active cylinder 300.Wherein, for the wordline 400 and the grid tube 400G, one kind is interpreted as：The word
Line 400 connects multiple grid tube 400G on same extension line；Another kind is it is also understood that be：400 middle ring of wordline
The grid tube 400G is constituted around the part of the active cylinder 300.
Further, the wordline 400 includes the connecting line portion 400L of multiple connection grid tube 400G, the connection
Line portion 400L regular linear connects the grid tube 400G on the adjacent active cylinder 300.In the alternative, institute
State connecting line portion 400L top surface can further below the top surface of the grid tube 400G, at this time the grid tube 400G and
The connecting line portion 400L can define a gap between the adjacent active cylinder 300.Therefore, in the present embodiment,
200 phase of projection image and the bit line of the extending direction of the connecting line portion 400L of the wordline 400 over the substrate
Angle theta is formed by when friendship, angle is for example between 50 °~70 °.
Wherein, the wordline 400 is also laminated construction comprising the gate work-function layer 410 and grid stacked gradually is led
Electric layer 420.The material of the gate work-function layer 410 for example including one of titanium (Ti) or titanium nitride (TiN) or combinations thereof,
The material of the grid conducting layer 420 is for example including one of polysilicon (Poly) and tungsten (W) or combinations thereof.
In addition, the integrated circuit memory further includes a gate dielectric layer 500, the gate dielectric layer 500 is formed in
On the substrate 100 and cover the side wall of the active cylinder 300 and the wordline 400 is formed in the gate dielectric layer
On 500, thus gate dielectric layer 500 described in the interval the grid tube 400G and cover the side wall of the active cylinder 300.It is described
The material of gate dielectric layer 410 is for example including silica (SiO).
With continued reference to shown in Fig. 3 a, Fig. 3 b and Fig. 3 c, the top end part 302 of the active cylinder 300 exposes to the grid
Pipe 400G.Specifically, the bottom end 301 and top end part 302 of the active cylinder 300 can be respectively used to composition drain region, (first mixes
Miscellaneous area 300D) and source region (the second doped region 300S), wherein the drain region of the active pillar body 300 is connected to bit line 200, the source
Area is exposed from the grid tube 400G, for being connected to memory element C (for example, storage etc.).
Since the memory transistor T forms its source region, channel region and drain region, and its using the active layer of column structure
Source region and drain region are the memory transistor T for being distributed vertically along short transverse, and then forming vertical structure.Compared to traditional
(its source region of traditional memory transistor and drain region are along the water perpendicular to short transverse for the memory transistor of horizontal structure
Divide cloth equally), the memory transistor of vertical structure occupied area on substrate 100 is smaller, is advantageously implemented storage crystal
The reduction of pipe T size.Also, the memory transistor of vertical structure can efficiently use the area of space of 100 top of substrate, such as
Crystalline substance can be stored to reduce to adjust the channel length of the memory transistor T by changing the height of the active cylinder 300
The risk of body pipe T generation short-channel effect.
Specifically, a vertical memory transistor T is on the substrate 100 in the integrated circuit memory of the present embodiment
Unit configuration sized can reach minimum feature size square 4 times of (2F*2F=4F2, wherein F is minimal characteristic ruler
It is very little).It should be noted that " unit configuration sized " described herein refers to：It needs for a storage unit in substrate
On for its configuration unit configuration sized, specifically include：The size of occupancy is actually needed in one storage unit on substrate, and
The required reserved size of space between the storage unit and adjacent storage unit.E.g., N number of memory transistor is described
It is occupied having a size of M on substrate, then unit configuration sized of the memory transistor on the substrate 100 is N/M.
Emphasis is with reference to shown in Fig. 2 b, for the vertical memory transistor T based on vertical structure, a plurality of 400 He of wordline
A plurality of 200 space intersection of the bit line simultaneously has multiple overlapping regions, wherein the i.e. corresponding vertical storage of an overlapping region
Transistor T (correspondingly, corresponding active cylinder 300).It is capable of forming according to existing preparation process with minimum feature size F
Bit line 200 and wordline 400, and make to be formed by line spacing between adjacent bit lines and adjacent word line also greater than being equal to minimum
Characteristic size F, then a vertical memory transistor T is being 2F perpendicular to the width dimensions D1 in bit line direction, vertical
In the width dimensions D2 on word-line direction be also 2F, therefore can make accordingly the vertical memory transistor T unit configure ruler
It is very little to reach 4F2(2F*2F).That is, the unit configuration sized of the vertical memory transistor T is more than or equal to the flat of minimum feature size
4 times of side.
Also, since vertical memory transistor T uses vertical structure, to make the arrangement of multiple vertical memory transistor T
Mode is more flexible, is advantageously implemented the more dense arrangement of vertical memory transistor array.For example, the vertical storage can be made brilliant
Body pipe array is in six square array arrangement modes (correspondingly, multiple active cylinders 300 are also six square array arrangement modes).Tool
Body, six side's arrangement modes of memory transistor array are, for example,：It is equidistant adjacent same in multiple vertical memory transistors
The arrangement of six square arrays is presented in the vertical memory transistor of six of vertical memory transistor.Correspondingly, multiple active pillars can be made
The arrangement of six square arrays is presented in six of equidistant adjacent same active cylinder active cylinders in body.
With continued reference to shown in Fig. 3 a and Fig. 3 b, the integrated circuit memory further includes：Multiple memory element C, are formed in
The top of the vertical memory transistor T, and be electrically connected with the top end part 302 of the active cylinder 300.It is understood that
, a vertical memory transistor T and a memory element C constitute the integrated circuit memory one deposits
Storage unit U.As noted previously, as the second doped region 300S of the active cylinder 300 is sudden and violent directly from the grid tube 400G
Expose, to make the second doped region 300S that can not can be electrically connected with memory element C by contact hole.
Wherein, the memory element C is for example including storage.The storage can use manufacture of semiconductor
Preparation is formed.The storage further comprises lower electrode plate (not shown), capacitor dielectric layer (not shown)
With electric pole plate (not shown), the top end part 302 of the lower electrode plate and active cylinder 300 is electrically connected, capacitor dielectric
Layer and electric pole plate are sequentially formed on the lower electrode plate.Preferably, the storage is two-sided capacitor, i.e., the described electricity
Hold dielectric layer and electric pole plate is sequentially formed on two opposite surfaces of the lower electrode plate, to utilize a lower electrode
Plate can constitute two capacitors in its two sides, be conducive to the capacitance for improving storage.Optionally, the capacitor dielectric layer
High K dielectric material can be used to be formed, such as can be aluminium oxide (Al2O3) or zirconium oxide (ZrO) etc..
As it can be seen that the memory element C is also the area of space made full use of above memory transistor T, and it is formed in described
The top of memory transistor T, and the memory element C and the memory transistor T can be realized one-to-one relationship (example
Such as, the position of memory element C is corresponding with the position of the memory transistor T), to by the vertical memory transistor T and deposit
Storing up the storage unit U that element C is constituted also is vertical structure (or up-down structure).It is understood that a storage unit U is being served as a contrast
Unit configuration sized on bottom 100 depends on unit configuration sized of the vertical memory transistor T on substrate 100, accordingly
, when size of the vertical memory transistor T on the substrate 100 is reduced, that is, it is advantageously implemented the list of whole memory cell U
The reduction of first configuration sized.
Therefore, in the present embodiment, the unit configuration sized of the vertical memory transistor T on substrate can reach 4F2,
Then the unit configuration sized of the storage unit U on substrate can also reach 4F2；And multiple vertical memory transistor T are in
When six sides are densely arranged, then the storage unit U is also densely arranged in six sides accordingly.This up-down structure in the present embodiment
Storage unit being capable of memory collection with high density array, especially suitable for microminiaturization, dense arrangement and high-speed operation
At circuit memory.Especially, for dynamic randon access integrated circuit memory (Dynamic Random Access
Memory, DRAM) for, since the structure of DRAM integrated circuit memory is simple (that is, a storage unit is usually only necessary to one
A storage and a memory transistor), therefore storage unit using the above structure stores DRAM integrated circuit
For device, size reduction is become apparent, the increase for concentration of arranging is also especially prominent.
Referring next to shown in Fig. 3 a~Fig. 3 c, the integrated circuit memory further includes an insulating medium layer 600, is formed in
On the substrate 100, the insulating medium layer 600 fills the gap between the adjacent bit line 200 and covers the bit line
200.That is, adjacent bit line 200 is isolated using the insulating medium layer 600, and the bit line 200 and wordline 400 can be made mutual
Isolation, and then improve the parasitic capacitance between bit line 200 and wordline 400.
In the present embodiment, the top surface of the insulating medium layer 600 is higher than the top surface of the bit line 200, so that described
Insulating medium layer 600 can cover bit line 200.At this point, the insulating medium layer 600 can also be accordingly around the active pillar
The member base end portion 301 of body 300.It, can be to the bottom position for being formed by wordline 400 due to the presence of insulating medium layer 600
It sets and causes direct or indirect influence.Based on this, in the present embodiment, it is higher than institute in the top surface for making the insulating medium layer 600
On the basis of the top surface of rheme line 200, further make the top surface of insulating medium layer 600 lower than the active cylinder 300
The top boundary of the first doped region 300D.In this way, the bottom of the wordline 400 can be made lower than first doped region
The top boundary of 300D, so that it is guaranteed that grid tube 400G can at least partly cover the first doped region 300D, to ensure
State the performance of vertical memory transistor T.
Similar, the top surface of the grid tube 400G is higher than the second doped region 300S of the active cylinder 300
Bottom boundary, the grid tube 400G can correspondingly at least partly cover the second doped region 300S at this time, so as to
It realizes and utilizes the current lead-through between grid tube 400G control the first doped region 300D and the second doped region 300S.Further
, the top surface of the grid tube 400G can also be further below the top surface of the active cylinder 300, that is, the grid tube
The the second doped region 300S for extending to active column side wall is not completely covered in 400G, but part covers second doped region
300S can so be effectively improved the leakage phenomenon of vertical memory transistor.
With continued reference to shown in Fig. 3 a~3c, the integrated circuit memory further includes：One spacer dielectric layer 700.Described
It is formed on substrate 100 every dielectric layer 700 and fills the gap between adjacent gate pole pipe 400G.In addition, in the present embodiment, it is right
Grid tube 400G and connecting line the portion 400L in same wordline 400 is answered to define a gap in the adjacent active cylinder 300
Between, therefore further filling is defined the spacer dielectric layer 700 by the grid tube 400G and the connecting line portion 400L
The gap (that is, the spacer dielectric layer 700 covers the connecting line portion 400L, and extends over the grid tube 400G's
Side wall).It is to be understood that the gap between adjacent vertical memory transistor T is filled using the spacer dielectric layer 700, with
Make mutually separated between adjacent vertical memory transistor T.Wherein, the material of the spacer dielectric layer 700 is for example including oxidation
Silicon (SiO).
In optional scheme, the top surface of the spacer dielectric layer 700 is not higher than active 300 top surface of cylinder, this
In embodiment, the top surface of the spacer dielectric layer 700 is flushed with active 300 top surface of cylinder.
Further, it is additionally provided with a separation layer 800 between the vertical memory transistor T and the memory element C,
The portion for not needing connection to be isolated between the vertical memory transistor T and the memory element C using the separation layer 800
Point.In the present embodiment, the separation layer 800 covers on the spacer dielectric layer 700 and covers the grid tube 400G and described
The operative tip portion 302 of active cylinder 300.Wherein, the material of the separation layer 800 is for example including silicon nitride (SiN).
In addition, it is also formed with node contact layer 900 on the top end part 302 of the active cylinder 300 in the present embodiment,
The node contact layer 900 runs through the separation layer 800 to connect with the second doped region 300S of the active cylinder 300, and
For being connected to memory element C.That is, the second doped region 300S's of the active cylinder 300 passes through the node contact layer 900
It is connected to the memory element C, in this way, be conducive to reduce the contact resistance between memory element C and the active cylinder 300,
To further increase the performance of entire integrated circuit memory.Wherein, the material of the node contact layer 900 is for example including tungsten
(W)。
Embodiment two
It in the present embodiment, is illustrated by the forming method to memory, the utility model offer is explained further
Integrated circuit memory.Fig. 4 is that the process of the forming method of the integrated circuit memory in the utility model embodiment two is shown
It is intended to, refering to what is shown in Fig. 4, in the present embodiment, the forming method of the integrated circuit memory includes：
Step S100 provides a substrate, and forms multiple bit lines over the substrate, and the bit line prolongs along a first direction
It stretches；
Step S200 forms multiple active cylinders on the bit line, and the bottom end of the active cylinder is connected to described
Bit line；
Step S300 forms a plurality of wordline over the substrate, and the wordline extends along second direction, and the wordline exists
Grid tube is connected on its extending direction, the grid tube surround the lateral wall of corresponding active cylinder, and by the active pillar
Body and the grid tube collectively form the vertical memory transistor of the integrated circuit memory.
Based on the forming method of integrated circuit memory as described above, the vertical storage that can form vertical structure is brilliant
Body pipe.Using the vertical memory transistor of vertical structure, it is on the one hand advantageously implemented the contracting of single vertical storage crystal pipe size
Subtract, such as can make to be formed by the unit configuration sized of vertical memory transistor on substrate more than or equal to minimum feature size
Square 4 times of (4F2), and then can effectively reduce the size of entire integrated circuit memory；On the other hand, be conducive to improve multiple
The arrangement flexibility of vertical memory transistor, the intensive journey of arrangement so as to improve storage unit in integrated circuit memory
Degree, such as multiple vertical memory transistors may be implemented in six side's arrangement modes.
It is described in detail below in conjunction with each step of the attached drawing to the forming method in the present embodiment.
Fig. 5 a is the forming method of the integrated circuit memory in the utility model embodiment two in its execution step S100
When top view, Fig. 5 b be the utility model embodiment two in integrated circuit memory forming method its execute step
Diagrammatic cross-section when S100.
In the step s 100, with specific reference to shown in Fig. 5 a and Fig. 5 b, a substrate 100 is provided, and forms multiple bit lines 200 and exists
On the substrate 100, the bit line 200 extends along a first direction.
As described in embodiment one, the bit line 200 can be laminated construction comprising be sequentially formed at the substrate
Bit line separation layer, bit line conductive layer and bit line contact layer on 100.Institute's bitline contact layer is used for and the active pillar that is subsequently formed
The bottom end of body connects.
Fig. 6 a is the forming method of the integrated circuit memory in the utility model embodiment two in its execution step S200
When top view, Fig. 6 b~Fig. 6 d be the utility model embodiment two in integrated circuit memory forming method its execution
Diagrammatic cross-section when step S200.
In step s 200, with specific reference to shown in Fig. 6 a and Fig. 6 d, the multiple active cylinders 300 of formation are in the bit line 200
On, the bottom end 301 of the active cylinder 300 is connected to the bit line 200.
Wherein, the active cylinder 300 is used to constitute source region, channel region and the drain region of vertical memory transistor, and can
Make to be formed by source region, channel region and drain region and arrange vertically along short transverse, and then constitutes the memory transistor of vertical structure,
Therefore the arrangement mode of the active cylinder 300 will directly affect the subsequent arrangement mode for being formed by whole memory cell.
In the present embodiment, multiple active cylinders 300 are in six side's arrangement modes, i.e., equidistant in multiple active cylinders 300
The arrangement of six square arrays is presented in the active cylinder of six of adjacent same active cylinder.In this way, can make subsequent to be formed by vertical deposit
Storing up transistor (storage unit) also is in six side's arrangement modes, to improve the arrangement concentration of the storage unit.
With further reference to shown in Fig. 6 b~Fig. 6 d, the forming method of the active cylinder 300 includes：
Referring initially to a sacrificial layer 300M shown in Fig. 6 b, is formed on the substrate 100, opened up in the sacrificial layer 300M
There are multiple through-hole H, the through-hole H to expose the bit line 200；
Referring next to active material shown in Fig. 6 c and Fig. 6 d, is filled in the through-hole H, to form the active cylinder
300, and remove the sacrificial layer 300M.
Further, since the active cylinder 300 is for constituting vertical memory transistor source region, channel region and drain region,
Therefore when filling the through-hole H, the active material doped with conductive ion can be filled accordingly in the through-hole H.Specifically
, when filling the bottom of the through-hole H, such as doping process in situ can be used, to form the first doped region 300D described
In the bottom end 301 of active cylinder 300.
It further include step S201 after forming the active cylinder 300 in preferred scheme：Form a dielectric
Layer is on the substrate 100.
Fig. 7 a is the forming method of the integrated circuit memory in the utility model embodiment two in its execution step S201
When top view, Fig. 7 b be the utility model embodiment two in integrated circuit memory forming method its execute step
Diagrammatic cross-section when S201.
In step s 201, with specific reference to shown in Fig. 7 a and Fig. 7 b, one insulating medium layer 600 of formation is in the substrate 100
On, the insulating medium layer 600 fills the gap between the adjacent bit line 200 and covers the bit line 200.
By forming the insulating medium layer 600, so that bit line 200 is isolated with the wordline being subsequently formed.In addition, can also lead to
The thickness for adjusting the insulating medium layer 600 is crossed, further to improve the parasitism electricity between bit line 200 and the wordline being subsequently formed
Hold.As shown in Figure 7b, the top surface of the insulating medium layer 600 is higher than the top surface of the bit line 200, and lower than described active
The bottom boundary of first doped region 300S of cylinder 300.
Fig. 8 a~Fig. 9 a is that the forming method of the integrated circuit memory in the utility model embodiment two executes step at it
Top view when rapid S300, Fig. 8 b~Fig. 8 c and Fig. 9 b are the formation of the integrated circuit memory in the utility model embodiment two
Diagrammatic cross-section of the method when it executes step S300.
In step S300, with specific reference to shown in Fig. 8 a~Fig. 8 c and Fig. 9 a~Fig. 9 b, forming a plurality of wordline 400 described
On substrate 100, the wordline 400 extends along second direction, and the wordline 400 is connected with grid tube in their extension direction
The side wall of 400G, the grid tube 400G around corresponding active cylinder 300.And by the active cylinder 300 and the grid
Pipe 400G collectively forms the vertical memory transistor of the integrated circuit memory.Further, the top of the active cylinder 300
It is surface exposed in the grid tube 400G.
Wherein, the wordline 400 and the grid tube 400G can be formed in same processing step, can be recognized at this time
To be looped around the part of 300 side wall of active cylinder in the wordline 400 for constituting the grid tube 400G.Alternatively, institute
Stating grid tube 400G and the wordline 400 can also form in two processing steps respectively, real using the wordline 400 at this time
The interconnection of multiple grid tube 400G on existing same extension line.And in the present embodiment, vertical based on vertical structure is deposited
For storing up transistor, a plurality of wordline 400 and a plurality of 200 space intersection of the bit line and there are multiple overlapping regions, and
The i.e. corresponding active cylinder 300 of one overlapping region, corresponds to a vertical memory transistor accordingly.
Further, before forming the wordline 400, further include：A gate dielectric layer 500 is formed in the substrate
On 100, what the gate dielectric layer 500 can be conformal is formed on the active cylinder 300, and the covering dielectric
The part between the adjacent active cylinder 300 is corresponded in layer 600.
In optional scheme, the forming method of place wordline 400 and the grid tube 400G may include following steps.
First step, with specific reference to shown in Fig. 8 a and Fig. 8 b, one conductive material layer 400a is on the substrate 100 for formation,
The conductive material layer 400a covers the top surface and side wall of the active cylinder 300, and covers the adjacent active cylinder 300
Between film surface.In the present embodiment, the conductive material layer 400a is formed on the gate dielectric layer 500.Wherein, institute
Stating conductive material layer 400a successively includes a workfunction material 410a and a conductive material layer 420a.
Second step, with continued reference to shown in Fig. 8 a~8c, in conjunction with a mask plate 400M and execution is etched back to technique, described to cover
Definition has a plurality of lines extended along second direction in film version 400M, is etched back to the conduction material by the mask plate 400M
Bed of material 400a, to be used to form the call wire of a plurality of correspondence lines.
As shown in Figure 8 a, in the present embodiment, described in the extending direction of the lines in the mask plate 400M i.e. correspondence
The extending direction of wordline 400.Therefore, when being etched back to technique to conductive material layer 400a execution using the mask plate 400M,
Etching agent 400E can remove the part of lines described in non-corresponding in conductive material layer 400a (for example, in conductive material layer 400a
The corresponding part between the adjacent lines), and retain conductive material layer corresponding with the lines to form call wire, and
For constituting wordline 400 and grid tube 400G.At this point, around the part of active 300 lateral wall of cylinder in the call wire
The grid tube 400G is constituted, the part that the adjacent grid tube is connected in the call wire constitutes the company of the wordline 400
Wire connecting portion.
It should be noted that in the present embodiment, even if the lines of the mask plate 400M are not completely covered by and described have
Conductive material layer (including the conductive material layer on active column side wall) on source cylinder 300, however, due to used etching
Technique is to be etched back to technique, therefore after the etching process, can remove the conductive material being formed on gate dielectric layer 500
Layer, without completely removing the conductive material layer being formed on active 300 side wall of cylinder.
In addition, being still further comprised after being etched back to technique to conductive material layer execution：It is covered in removal call wire
Cover the part of 300 top surface of active cylinder；And it can also further expose the top end part of the active cylinder 300.
Wherein, the removal process of the part of 300 top surface of active cylinder is covered in the call wire in combination with subsequent isolation work
Skill is performed simultaneously.
With specific reference to shown in Fig. 9 a and Fig. 9 b, in subsequent technique, can also further comprise：Fill a spacer dielectric layer
700 gap between the adjacent active cylinder 300.In the present embodiment, the spacer dielectric layer 700 fills adjacent word line
Gap between 400.In addition, the grid tube 400G of corresponding same wordline 400 and connecting line portion define a gap adjacent
Between the active cylinder 300, therefore the spacer dielectric layer 700 is further filled by the grid tube 400G and the connection
Line portion defines the gap.
Wherein, the spacer dielectric layer 700 is formed using flatening process, specifically：
Firstly, forming a layer of dielectric material on the substrate 100, the layer of dielectric material fills the adjacent grid
Gap between pipe 400G, and cover the conductive material layer for being located at active 300 top surface of cylinder；
Then, flatening process is executed to the layer of dielectric material, had described in covering to remove in the layer of dielectric material
The part of 300 top surface of source cylinder, until exposing the conductive material layer for covering active 300 top surface of cylinder；
Then, flatening process is continued to execute to the layer of dielectric material and the conductive material layer, to remove the biography
Material layer is led, and removes the layer of dielectric material on corresponding height position, until exposing the top surface of the active cylinder 300.
In the present embodiment, after removing the conductive material layer being located on active 300 top surface of cylinder, the grid are further removed
It is located at the part of active 300 top surface of cylinder in pole dielectric layer 500, to expose the top table of the active cylinder 300
Face.
In this way, can be while forming spacer dielectric layer 700 using flatening process, additionally it is possible to further removal
The conductive material at active 300 top of cylinder, and active 300 top end part of cylinder can be made to expose.And the blank medium can be made
The top surface of layer 700 is flushed with the top surface of the active cylinder 300, to be conducive to the formation of subsequent memory element.
Further, after the top surface for exposing the active cylinder 300, further include：Ion implantation technology is executed,
To form the second doped region 300S in the top end part of the active cylinder 300.
In preferred scheme, (that is, the present embodiment after removing the conductive material layer for being located at active 300 top surface of cylinder
In expose the active cylinder 300 after), also further the grid tube 400G can be performed etching, pass through etching exposure
The grid tube out is to reduce the height of the grid tube, so that the second doped region 300S be made to diffuse to active pillar side
The part of wall will not be completely covered by the grid tube, be conducive to reduce be formed by vertical memory transistor leakage current it is existing
As.Meanwhile the height of the grid tube can be also controlled accordingly, so that the top surface of grid tube is higher than the second doped region 300S
Bottom boundary, to ensure between the grid tube and the second doped region 300S to ensure vertical there are space overlapping region
The function of memory transistor.In addition, by continuing to etch to the grid tube, additionally it is possible to avoid in grinding conductive material layer
During conductive material extend into the top surface of active cylinder 300 and cause the top end part 302 of grid tube Yu active cylinder 300
The problem of short circuit.
It is believed that being so far basically completed the preparation process of vertical memory transistor.In subsequent technique, Ji Ke
The top of the vertical memory transistor forms memory element.
In preferred scheme, (that is, the present embodiment after removing the conductive material layer for being located at active 300 top surface of cylinder
In expose the active cylinder 300 after), can also further comprise：A separation layer is formed on the substrate 100, it is described
Separation layer covers the spacer dielectric layer 700, and covers the operative tip of the grid tube 400G and the active cylinder 300
Portion.That is, avoid the grid tube from exposing by the separation layer, the memory element for thus preventing grid tube and being subsequently formed
It is electrically connected.
Further, a node contact layer can also be formed on the top end part 302 of the active cylinder 300, the node
Contact layer is embedded in the separation layer to connect with the second doped region 300S of the active cylinder 300, and is used for and subsequent institute's shape
At memory element be electrically connected.
In this way, i.e. executable step S400, a memory element is formed in the top of the vertical memory transistor, it is described to deposit
The top end part 302 for storing up element and the active cylinder 300 is electrically connected.Wherein, the memory element is, for example, to store electricity
Container, and the storage is prepared using manufacture of semiconductor.
In addition, existing in semiconductor field, there are many semiconductor devices, and there is also have in a variety of semiconductor devices
It needs to draw active area.Wherein, the active area for needing to draw can also be replaced using active cylinder provided by the utility model, with
So that the active area in semiconductor devices is arranged in a vertical manner, and draws.
Specifically, the utility model additionally provides a kind of semiconductor devices, including：
One substrate；
A plurality of first call wire, formation extend over the substrate and along a first direction；
Multiple active cylinders are formed on first call wire, so that the bottom end of the active cylinder is connected to institute
It states on the first call wire；And
A plurality of second call wire forms over the substrate and extends along second direction, and second call wire is at it
Around the side wall of corresponding active cylinder on extending direction, multiple corresponding active cylinders are connected to extend.
That is, the bottom end of active cylinder can use the first call wire being disposed below from below in semiconductor devices
It draws；The top end part of active cylinder can be used for connecting with other elements；And the second call wire of part is around the active cylinder
Side wall therefore in a kind of embodiment, can use second call wire and draw the active cylinder close to intermediate portion
Point；Alternatively, in another embodiment control signal can be conveyed, by second call wire to control the two of active cylinder
Current lead-through between a end.
In conclusion in integrated circuit memory provided by the utility model, using being vertically arranged on substrate active
Cylinder not only contributes to the unit configuration for realizing memory transistor so as to constitute the vertical memory transistor of vertical structure
The reduction of size (is greater than equal to 4F2), and the arrangement closeness (example of vertical memory transistor can also be further increased
Such as, six sides are densely arranged).In this way, the size of integrated circuit memory can be reduced accordingly.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Fixed, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content belong to right and want
Seek the protection scope of book.
Claims (12)
1. a kind of integrated circuit memory, which is characterized in that including：
One substrate；
Multiple bit lines, formation extend over the substrate and along a first direction；
Multiple active cylinders, are formed on the bit line, so that the bottom end of the active cylinder is connected to the bit line；With
And
A plurality of wordline forms over the substrate and extends along second direction, and the wordline is connected in their extension direction
Grid tube, for the grid tube around the lateral wall of corresponding active cylinder, the top of the active cylinder exposes to the grid
Pipe, the vertical memory transistor of the integrated circuit memory is collectively formed by the active cylinder and the grid tube.
2. integrated circuit memory as described in claim 1, which is characterized in that the integrated circuit memory it is described vertical
The unit configuration sized of memory transistor over the substrate be more than or equal to minimum feature size square 4 times.
3. integrated circuit memory as described in claim 1, which is characterized in that the integrated circuit memory further includes：It is more
A memory element is formed in the top of the vertical memory transistor, and electrically connects with the top end part of the active cylinder
It connects.
4. integrated circuit memory as described in claim 1, which is characterized in that shape in the bottom end of the active cylinder
It at there is the first doped region, is connected on the bit line, the second doped region is formed in the top end part of the active cylinder, use
To connect memory element, first doped region and second doped region respectively constitute the drain region of the vertical memory transistor
And source region.
5. integrated circuit memory as claimed in claim 4, which is characterized in that further include：
One insulating medium layer is formed over the substrate, and the insulating medium layer fills the gap between the adjacent bit line
And the bit line is covered, the wordline is formed on the insulating medium layer.
6. integrated circuit memory as claimed in claim 5, which is characterized in that the insulating medium layer is also around described active
The member base end portion of cylinder；Also, the top surface of the insulating medium layer is higher than the top surface of the bit line, and has lower than described
The top boundary of first doped region of source cylinder.
7. integrated circuit memory as described in claim 1, which is characterized in that the shape of the active cylinder includes cylinder
Body.
8. integrated circuit memory as described in claim 1, which is characterized in that a plurality of wordline and a plurality of bit line are empty
Between intersect and have multiple overlapping regions, the corresponding active cylinder of overlapping region, in multiple active cylinders
The arrangement of six square arrays is presented in six active cylinders of equidistant adjacent same active cylinder.
9. integrated circuit memory as described in any one of claims 1 to 8, which is characterized in that further include：
One spacer dielectric layer forms over the substrate and fills the gap between the adjacent grid tube.
10. integrated circuit memory as claimed in claim 9, which is characterized in that the wordline includes multiple connection grid
The connecting line portion of pole pipe, connecting line portion regular linear connect the grid tube on the adjacent active cylinder, and
The top surface in the connecting line portion is lower than the top surface of the grid tube；Wherein, described in the spacer dielectric layer further covers
Connecting line portion, and extend over the side wall of the grid tube.
11. integrated circuit memory as claimed in claim 10, which is characterized in that the connecting line portion of the wordline prolongs
It stretches direction projection image over the substrate and the bit line intersects and have an angle, the angle of the angle is between 50 °
~70 °.
12. a kind of semiconductor device, which is characterized in that including：
One substrate；
A plurality of first call wire, formation extend over the substrate and along a first direction；
Multiple active cylinders are formed on first call wire, so that the bottom end of the active cylinder is connected to described
On one call wire；And
A plurality of second call wire forms over the substrate and extends along second direction, and second call wire is in its extension
Side connects multiple corresponding active cylinders up around the side wall of corresponding active cylinder to extend.
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