CN208061205U - A kind of anti-jamming circuit and chip of dram controller - Google Patents

Abstract

The utility model is related to a kind of anti-jamming circuit of dram controller and chips.The anti-jamming circuit and chip, other than it can filter out the burr of DQS signal, the number of pulses of DQS signal corresponding in the time window section can also be compared with amount of bursts, if the quantity of the two is identical, then show that the DQS signal is useful signal, the DQS processing modules send out control signal to data acquisition module is read, it is made to carry out reading data acquisition operations.If the quantity of the two differs, show DQS signal exception, be invalid signals, the DQS processing modules send out control signal to order transmitting module, so that it is re-emitted after read command receives the order to DRAM, DRAM and return to data.

Description

A kind of anti-jamming circuit and chip of dram controller

Technical field

The utility model is related to digital circuit fields, and in particular to a kind of anti-jamming circuit and chip of dram controller.

Background technology

Existing processor or SOC（System on Chip, abbreviation system on chip）, more or less can all be limited to visit The performance deposited, storage wall problem performance are more and more obvious.In a SOC system, DRAM（Dynamic Random Access Memory）, i.e. dynamic random access memory is the fastest external memory, most fast DRAM speed is up to 1GHz or more. Under so fast speed, the influence of noise and interference for DRAM is very big, it is easy to lead to DRAM read-write errors.And DQS （Data decimation pulse）In communication between DRAM and Memory Controller Hub, it is mainly used to accurate area within a clock cycle Each transmission cycle is separated, and data are accurately received convenient for recipient.If DQS itself there is the interference such as many burrs, It is easier to lead to DRAM read-write errors.

Utility model content

It, can be with to solve the above problems, the utility model provides a kind of anti-jamming circuit and chip of dram controller The burr interference for reducing DQS signal, improves the accuracy of DQS signal.The specific technical solution of the utility model is as follows：

A kind of anti-jamming circuit of dram controller, including：DQS time windows for generating DQS time window signals Module, input terminal are connect with DRAM, and for inputting the DQS signal that DRAM is sent out, and output end is then used to export DQS time windows Message number；DQS processing modules, one input terminal are connect with DRAM, and for inputting DQS signal, another input terminal and institute The DQS time window signals stated the connection of DQS time window modules, and generated for inputting the DQS time windows module；Its In, the DQS processing modules are used to the DQS signal and the DQS time windows signal carrying out sequential to when analyzing, and Order transmitting module is output control signals to according to analysis result and reads data acquisition module, to control the order transmitting module Read command or the control reading data acquisition module progress data acquisition are retransmitted to DRAM and are transmitted to CPU.

Further, the DQS time windows module includes：DQS Edge check submodules for detecting DQS edge signals Block, input terminal is for receiving DQS signal, and output end is for exporting testing result；Counter, input terminal and the sides DQS Output end along detection sub-module connects, and count value handling submodule is inputted for being counted to testing result, and by count value Block；Count value handling submodule, input terminal connect the output end of the counter, and output end is then connected to data selector Selection signal input terminal, the count value for being inputted to the counter are handled, and export selection signal to the data Selector；The data selector, selection signal input terminal are connect with the count value handling submodule, data input pin with Shift register connects, and the output end then output end as DQS time window modules is used for according to the count value handling submodule The selection signal of block output, the deposit signal of shift register output described in corresponding selection is as DQS time window signals It is exported；The shift register, input terminal are connect with read states generator, for generating the read states generator Status signals shifted and deposited, and export to the data selector data input pin；The read states generate Device for generating status signals, and is exported to the shift register.

Further, the DQS Edge checks submodule is a DQS Edge check register comprising for receiving The clock end of DQS signal adjusts the reset terminal of signal, the data terminal for receiving high level, for exporting for receiving window The output end of testing result.

Further, the count value handling submodule is an intermediate value processing circuit, including multiple counting value registers With multiple comparators, the count value in multiple counting value registers is compared two-by-two by comparing device, output is intermediate Value.

Further, the DQS processing modules include：With door, one input terminal is connect with DRAM, for receiving DRAM The DQS signal sent out, another input terminal is connect with the output end of the DQS time windows module, when for receiving the DQS Between window signal, output end is then connected to pulse counter, for exporting the DQS signal and the DQS time windows signal Mutually with after and signal；Pulse counter, the input terminal connection output end with door, output end are then connected to pulse and compare One input terminal of device, what the pulse counter was used to input carries out step-by-step counting with signal, and count results are exported To pulse comparator；Pulse comparator, one input terminal are connect with the output end of the pulse counter, another input terminal Signal for receiving amount of bursts, then the output end as DQS processing modules, the pulse comparator are used to compare output end Step-by-step counting result and bursty data, and order transmitting module is output control signals to according to comparison result and reads data acquisition module Block.

A kind of chip, including integrated circuit, the integrated circuit are the anti-of the dram controller described in any of the above one Interfere circuit.

The anti-jamming circuit and chip of dram controller provided by the utility model are produced by DQS time window modules Raw DQS time window signals, then by DQS processing modules will be located in DQS signal the burr other than the time window section or Other clutters filter out.In addition, the DQS processing modules can also be by DQS signal corresponding in the time window section Number of pulses is compared with amount of bursts, if the quantity of the two is identical, shows that the DQS signal is useful signal, described DQS processing modules send out control signal to data acquisition module is read, it is made to carry out reading data acquisition operations.If the quantity of the two It differs, then shows DQS signal exception, be invalid signals, the DQS processing modules send out control signal to order transmitting mould Block makes it re-emit after read command receives the order to DRAM, DRAM and returns to data.When the circuit passes through DQS Between window module and DQS processing modules DQS signal is handled, it can be deduced that accurate DQS signal improves DRAM controls The jamproof performance of device.

Description of the drawings

Fig. 1 is the structure diagram that the dram controller is connect with CPU and DRAM.

Fig. 2 is the flow chart of an embodiment of the anti-interference method of the dram controller.

Fig. 3 is that DQS signal and DQS time window signals carry out sequential to the schematic diagram one when analyzed.

Fig. 4 is that DQS signal and DQS time window signals carry out sequential to the schematic diagram two when analyzed.

Fig. 5 is a kind of structure diagram of embodiment of the anti-jamming circuit of dram controller described in the utility model.

Fig. 6 is a kind of structure diagram of embodiment of DQS time windows module described in the utility model.

Fig. 7 is the pin configuration schematic diagram of Edge check register.

Fig. 8 is the electrical block diagram of the count value handling submodule.

Fig. 9 is the electrical block diagram of the DQS processing modules.

Specific implementation mode

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Detailed description.It should be appreciated that specific embodiment disclosed below is only used for explaining the utility model, it is not used to limit this reality With novel.

DRAM (Dynamic Random Access Memory), i.e. dynamic random access memory, are most commonly seen Installed System Memory.Data can only be kept for the very short time by DRAM.In order to keep data, DRAM to be stored using capacitance, so necessary Refresh once every a period of time, if storage unit is not refreshed, the information of storage will lose (for example, shutdown will lose Lose data).DRAM is multiplexed according to row and column address pin by many basic units of storage to form, and its main function is former Reason is to represent one using the number of interior storage（bit）It is 1 or 0.Dram controller is set to system core chip system (SoC) in, it is inside computer system control memory and makes the important component of memory and the swapping data of CPU. Dram controller determines maximum memory capacity, memory BANK numbers, type of memory and the speed that computer system can use, interior Deposit particle data depth and data width etc. important parameter, that is to say, that determine the internal memory performance of computer system, to Also the overall performance of computer system is produced bigger effect.As shown in Figure 1, dram controller is connect with DRAM, for controlling The access of internal storage data in DRAM.The dram controller and CPU can be encapsulated in a chip.

The anti-interference method of dram controller as shown in Figure 2, includes the following steps：First, the dram controller inspection It measures DRAM and sends out DQS signal, just as clock signal, DQS signal is also the critical function in DRAM, is mainly used to Each transmission cycle is accurately distinguished in one clock cycle, and accurately receives data convenient for recipient.Each group of 8bit number According to position（DQ）A corresponding DQS signal line, it is two-way, and in write-in, it is used for transmitting the DQS sent by dram controller Signal when reading, then generates DQS from dram chip and is sent to dram controller, it is believed that it is exactly the synchronous letter of data Number.When receiving DQS signal, the dram controller generates DQS time window signals, and determines the DQS time windows Time window section in signal.Finally, the dram controller carries out the DQS signal and the DQS time windows signal Sequential determines in the DQS signal with the signal corresponding to the time window section to be normal signal to when analyzing.Such as Fig. 3 Shown, the 1st row is DQS signal, which includes the normal signal of DQS and the extraneous burr signal introduced；When 2nd row is DQS Between window signal（That is DQS_win signals）, wherein one section of high level is the time window section；3rd row is to pass through DQS_win Signal will be located at the signal filtered DQS signal other than the time window section in DQS signal, target signal filter burr Interference, accuracy higher.Method described in the present embodiment will be located at institute by using DQS time window signals in DQS signal It states the burr other than time window section or other clutters filters out, to obtain more accurate DQS signal, improve DRAM controls The jamproof performance of device.

As one of which embodiment, the step of dram controller generates DQS time window signals, specifically include Following steps：First, the dram controller determines continuous multiple according to the Edge check time for detecting DQS signal edge The average value or median of the Edge check time alternatively signal.Then, when the dram controller determines different The status signals that tagmeme is set, such as status signals after one clock cycle, the read states after two clock cycle Signal, the status signals after three clock cycle and the status signals, etc. after four clock cycle.Finally, it selects Take status signals corresponding with the selection signal as DQS time window signals, it so can be than reasonably obtaining The DQS time window signals being aligned with the edge of the DQS signal, i.e. DQS signal and DQS time window signals be while, Sequential so could be carried out to when analyzing, can just filter out other clutters.For example, dram controller detects DQS signal edge The Edge check time be respectively 2,3 and 4（Clock cycle）, then being averaged for these three numbers is taken to be worth to 3, or take these three numbers Centre be worth to 3, then may be selected by the status signals after three clock cycle as DQS time window signals, institute Determining DQS time windows signal is synchronous with DQS signal.Method described in the present embodiment, by taking multiple detection times Average value or median, the DQS time window signal synchronous with DQS signal can be relatively accurately obtained, after being conducive to Continuous sequential is to when analyzing.

As one of which embodiment, the time window section in the determination DQS time windows signal is specific to wrap Include following steps：First, it is based on system configuration, determines amount of bursts, wherein burst is also known as Burst, indicates that a read command is returned Return the data in how many a periods.Amount of bursts refers to just the number of burst, is obtained by being configured in system.By pulse Number is the continuous high level of the DQS signal of the amount of bursts as the time window section in the DQS time windows signal.Such as Shown in Fig. 3, amount of bursts 4, then the continuous high level corresponding to 4 DQS signals（The portion of DQS_win signals protrusions in figure Point）Time window section in the as described DQS time windows signal.Method described in the present embodiment is reference with amount of bursts To determine the time window section in the DQS time windows signal, it can more accurately determine and need to filter burr in DQS signal The range of equal clutters.

As one of which embodiment, in the determination DQS signal with corresponding to the time window section Further include following steps after the step of signal is normal signal：Judge the normal signal number of pulses whether with currently Amount of bursts is identical, if it is, determining that the normal signal is useful signal, otherwise, it determines the normal signal is invalid Signal.In practical applications, outside burr or the other clutters filtered out other than the time window section, it is also possible to occur with Lower problem：Due to signal interference or exception etc., the DQS signal in the time window section can also malfunction.Such as Fig. 4 institutes Show, by taking 4 read operations of DDR burst as an example, in the time window section of DQS_win signals shown in the 1st row, shown in the 2nd row DQS signal is normal condition（Including 4 pulses）, DQS signal shown in the 3rd row is abnormal conditions（A pulse is lacked）, the 4th DQS signal shown in row is abnormal conditions（More pulses）, both abnormal conditions can all lead to read operation error in data. To cope with this problem, the present embodiment will filter out the number of pulses of the normal signal of the DQS of the clutters such as burr with it is current Amount of bursts is compared, if the quantity of the two is identical, is shown that the DQS signal is useful signal, can be carried out subsequent Processing.If the quantity of the two differs, shows DQS signal exception, be invalid signals, need to re-read.So may be used To further prevent external disturbance and corrupt data.

A kind of anti-jamming circuit of dram controller as shown in Figure 5, the circuit include DQS time windows module, at DQS It manages module, order transmitting module, read data acquisition module and data return module, the DQS time windows module, DQS processing Module and the input terminal for reading data acquisition module are connect with the output end of DRAM respectively, the output end for reading data acquisition module Module is returned by data and is connected to CPU, and the output end of the DQS processing modules is respectively connected to the reading data acquisition module It is connected to the input terminal of DRAM with the output end of order transmitting module, the order transmitting module.These modules collect together with CPU At in SOC chip.Wherein, the DQS time windows module is for generating DQS time window signals, input terminal and DRAM Connection, and for inputting the DQS signal that DRAM is sent out, output end is then used to export DQS time window signals, i.e. DQS_win letters Number.One input terminal of DQS processing modules is connect with DRAM, and for inputting DQS signal, another input terminal and the DQS Time window module connects, and the DQS time window signals generated for inputting the DQS time windows module.At the DQS Module is managed to be used to the DQS signal and the DQS time windows signal carrying out sequential to when analyzing, and according to analysis result It outputs control signals to order transmitting module and reads data acquisition module, reading is retransmitted to DRAM to control the order transmitting module The reading data acquisition module is ordered or controls to carry out data acquisition and be transmitted to CPU.Circuit described in the present embodiment, passes through DQS time window modules generate DQS time window signals, then will be located at the time window in DQS signal by DQS processing modules Burr or other clutters other than mouth section filter out.In addition, the DQS processing modules can also be by institute in the time window section The number of pulses of corresponding DQS signal is compared with amount of bursts, if the quantity of the two is identical, shows the DQS signal For useful signal, the DQS processing modules send out control signal to data acquisition module is read, it is made to carry out reading data acquisition behaviour Make.If the quantity of the two differs, shows DQS signal exception, be invalid signals, the DQS processing modules send out control Signal processed makes it re-emit after read command receives the order to DRAM, DRAM and returns to data to order transmitting module （Including DQS signal and DQ signals）.As shown in the table, pulse_ok is a 2bit signal, and bit0 characterizations are currently got Whether DQS meets the requirements.Bit1 indicates whether DQS windows terminate.For example, in the case of DDRbusrt4 read commands, detection To 4 DQS pulses, after DQS_win time windows, pulse_ok states are 2 ' b11, then read operation is completed, and DQS is detected Pass through, pulse_ok signal transmissions are to reading data acquisition module.Circuit described in the present embodiment by DQS time windows module and DQS processing modules handle DQS signal, it can be deduced that accurate DQS signal improves the jamproof of dram controller Performance.

pulse_ok=2’b00	Read operation does not complete, and DQS detects fail
		pulse_ok=2’b01	N/A, the state that do not deposit
pulse_ok=2’b10	Read operation is completed, and DQS detects fail
		pulse_ok=2’b11	Read operation is completed, and DQS detects pass

As one of which embodiment, as shown in fig. 6, the DQS time windows module includes DQS Edge check submodules Block, counter, count value handling submodule, data selector, shift register and read states generator.Wherein, the sides DQS Along detection sub-module for detecting DQS edge signals, input terminal of the input terminal as DQS time window modules, for receiving The DQS signal that DRAM is sent out, output end are then used to export testing result to counter.The input terminal of the counter with it is described The output end of DQS Edge check submodules connects, and for being counted to testing result, and count value is inputted count value handling Submodule.The input terminal of the count value handling submodule connects the output end of the counter, and output end is then connected to data The selection signal input terminal of selector.At the count value that the count value handling submodule is used to input the counter Reason, and selection signal is exported to the data selector.The selection signal input terminal of the data selector and the count value Submodule connection is handled, data input pin is connect with shift register, the output end then output as DQS time window modules It holds, the selection signal for being exported according to the count value handling submodule, shift register output described in corresponding selection Deposit signal exported as DQS time window signals.The shift register, input terminal connect with read states generator It connects, the status signals for generating the read states generator are shifted and deposited, and are exported to the data and selected The data input pin of device.The read states generator for generating status signals, and is exported to the shift register.It lifts A data instance carries out the operation principle explanation of the module：It is assumed that DQS Edge check submodules detect DQS signal edge The Edge check time is respectively 2,1 and 3（Clock cycle）, show that testing result is 3 data by the counting of counter, then lead to It crosses that count value handling submodule is averaged this 3 numbers or centre is worth to 2, handling result 2 is then converted into selection Signal is sent to data selector.The average value can be obtained by divider, the median can by comparing device into Row size relatively obtains.At the same time, read states generator generates the status signals in different timing positions, in a clock Status signals after period, the status signals after two clock cycle, the status signals after three clock cycle With the status signals after four clock cycle, these status signals are deposited in a shift register respectively.Finally, data Selector is based on selection signal, determines the status signals after two clock cycle in shift register as DQS_win Signal is exported.DQS time window modules described in the present embodiment, by the average value or the centre that take multiple detection times Value, can relatively accurately obtain the DQS time window signal synchronous with DQS signal, be conducive to follow-up sequential to when analyzing.

As one of which embodiment, as shown in fig. 7, the DQS Edge checks submodule is a DQS Edge check Register comprising the clock end for receiving DQS signal adjusts signal for receiving window（Win_mode）Reset terminal, For receiving high level signal（1'b1）Data terminal, the output end for exporting testing result DQS_edge.It is terminated in clock When receiving the DQS signal of a cycle, the high level signal of data terminal is transferred to output end, and exports to counter and count one It is secondary.When reset terminal receives window adjustment signal, output end then exports low level.

As one of which embodiment, the count value handling submodule is an intermediate value processing circuit, including multiple Value register and multiple comparators are counted, the count value in multiple counting value registers is compared two-by-two by comparing device Compared with output median.As shown in figure 8, the count value handling submodule includes 3 counting value registers（A, B and C）With 3 Comparator is compared by comparing the count value in device P1 logarithm value register A and numerical register B, selects numerical value smaller Output be compared to comparator P3, then by comparing the count value in device P2 logarithm value register C and numerical register B, The output for selecting numerical value smaller is to comparator P3, finally by the bigger numerical value of comparator P3 output numerical values as median. Intermediate value processing circuit described in the present embodiment need not be calculated, and directly can be obtained output data by data comparison, be carried High data-handling efficiency.

As one of which embodiment, as shown in figure 9, the DQS processing modules include and door, pulse counter and arteries and veins Rush comparator.Wherein, described to be connect with DRAM with an input terminal of door, the DQS signal sent out for receiving DRAM（DQS）, Another input terminal is connect with the output end of the DQS time windows module, for receiving the DQS time windows signal （DQS_win）, output end is then connected to pulse counter, for exporting the DQS signal and the DQS time windows signal phase With after and signal.The input terminal connection output end with door of the pulse counter, output end are then connected to pulse ratio Compared with an input terminal of device, what the pulse counter was used to input carries out step-by-step counting with signal, and count results are defeated Go out to pulse comparator.One input terminal of the pulse comparator is connect with the output end of the pulse counter, another Input terminal is used to receive the Burst signals of amount of bursts, the output end then output end as DQS processing modules, the pulse ratio Compared with device for comparing step-by-step counting result and bursty data, and according to comparison result output control signals to order transmitting module and Read data acquisition module.DQS processing modules described in the present embodiment, by being located at the time in described and goalkeeper's DQS signal Burr or other clutters other than hatch section filter out.Then it is right institute to be calculated in the time window section by pulse counter again The number of pulses is compared by the number of pulses for the DQS signal answered finally by pulse comparator with amount of bursts, if The quantity of the two is identical, then shows that the DQS signal is useful signal, the DQS processing modules send out control signal to reading data Acquisition module makes it carry out reading data acquisition operations.If the quantity of the two differs, show DQS signal exception, is nothing Signal is imitated, the DQS processing modules send out control signal to order transmitting module, it is made to re-emit read command to DRAM, DRAM returns to data after receiving the order.In this way, can show that accurate DQS believes by simple circuit structure Number, the jamproof performance of dram controller is improved with lower cost.

A kind of chip, including integrated circuit, the integrated circuit are the dram controller described in any of the above-described embodiment Anti-jamming circuit.As shown in Figure 1, the chip described in the present embodiment can be effective using internal integration CPU and dram controller Control dram controller is operated in frequency same as core cpu, and since the data exchange between DRAM and CPU is not necessarily to By north bridge, transmission delay can be effectively reduced.

Obviously, the above embodiments are only the utility model a part of the embodiment, instead of all the embodiments, each Technical solution between embodiment can be combined with each other.In addition, if occur in embodiment "center", "upper", "lower", " left side ", The orientation or positional relationship of the terms such as " right side ", "vertical", "horizontal", "inner", "outside", instruction is orientation based on ... shown in the drawings Or position relationship, be merely for convenience of describing the present invention and simplifying the description, do not indicate or imply the indicated device or Element must have a particular orientation or with specific azimuth configuration and operation, therefore should not be understood as the limit to the utility model System.It is the differentiation for the ease of correlated characteristic, Bu Nengli if occurring the terms such as " first ", " second ", " third " in embodiment Solution is instruction or implies its relative importance, the quantity of the priority of order or technical characteristic.

One of ordinary skill in the art will appreciate that：Realize that all or part of step of above-mentioned each method embodiment can lead to The relevant hardware of program instruction is crossed to complete.These programs can be stored in computer read/write memory medium（Such as ROM, The various media that can store program code such as RAM, magnetic disc or CD）In.When being executed, execution includes above-mentioned each to the program The step of embodiment of the method.

Finally it should be noted that：The above various embodiments is only to illustrate the technical solution of the utility model, rather than limits it System；Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should Understand：It still can be with technical scheme described in the above embodiments is modified, either to which part or whole Technical characteristic carries out equivalent replacement；And these modifications or replacements, this practicality that it does not separate the essence of the corresponding technical solution are new The range of each embodiment technical solution of type.

Claims (6)

1. a kind of anti-jamming circuit of dram controller, which is characterized in that including：

DQS time window modules for generating DQS time window signals, input terminal are connect with DRAM, and for inputting The DQS signal that DRAM is sent out, output end are then used to export DQS time window signals；

DQS processing modules, one input terminal are connect with DRAM, and for inputting DQS signal, another input terminal with it is described DQS time window modules connect, and the DQS time window signals generated for inputting the DQS time windows module；

Wherein, the DQS processing modules are used to the DQS signal and the DQS time windows signal carrying out sequential to when Analysis, and order transmitting module is output control signals to according to analysis result and reads data acquisition module, to control the order Transmitting module retransmits read command or the control reading data acquisition module progress data acquisition to DRAM and is transmitted to CPU.

2. circuit according to claim 1, which is characterized in that the DQS time windows module includes：

DQS Edge check submodules for detecting DQS edge signals, for receiving DQS signal, output end is used for input terminal Export testing result；

Counter, input terminal are connect with the output end of the DQS Edge checks submodule, based on being carried out to testing result Number, and count value is inputted into count value handling submodule；

Count value handling submodule, input terminal connect the output end of the counter, and output end is then connected to data selector Selection signal input terminal, the count value for being inputted to the counter is handled, and exports selection signal to the number According to selector；

The data selector, selection signal input terminal are connect with the count value handling submodule, data input pin and shifting Bit register connects, and the output end then output end as DQS time window modules is used for according to the count value handling submodule The selection signal of output, the deposit signal of shift register output described in corresponding selection as DQS time windows signal into Row output；

The shift register, input terminal are connect with read states generator, the reading for generating the read states generator Status signal is shifted and is deposited, and is exported to the data input pin of the data selector；

The read states generator for generating status signals, and is exported to the shift register.

3. circuit according to claim 2, which is characterized in that the DQS Edge checks submodule is that an edge DQS is examined Survey register comprising the clock end for receiving DQS signal adjusts the reset terminal of signal for receiving window, for receiving The data terminal of high level, the output end for exporting testing result.

4. circuit according to claim 2, which is characterized in that the count value handling submodule is an intermediate value processing electricity Road, including multiple counting value registers and multiple comparators, by comparing device to multiple countings counted in value register Value is compared two-by-two, exports median.

5. circuit according to claim 1, which is characterized in that the DQS processing modules include：

With door, one input terminal is connect with DRAM, the DQS signal sent out for receiving DRAM, another input terminal with it is described The output end of DQS time window modules connects, and for receiving the DQS time windows signal, output end is then connected to pulsimeter Number devices, for export the DQS signal and the DQS time windows signal phase with after and signal；

Pulse counter, the input terminal connection output end with door, output end be then connected to pulse comparator one are defeated Enter end, what the pulse counter was used to input carries out step-by-step counting with signal, and count results are exported to pulse and are compared Device；

Pulse comparator, one input terminal are connect with the output end of the pulse counter, another input terminal is for receiving The signal of amount of bursts, then the output end as DQS processing modules, the pulse comparator are used to compare step-by-step counting output end As a result it and bursty data, and according to comparison result outputs control signals to order transmitting module and reads data acquisition module.

6. a kind of chip, including integrated circuit, which is characterized in that the integrated circuit is any one of claim 1 to 5 institute The anti-jamming circuit for the dram controller stated.