CN207992862U - A kind of push-pull type quick response LDO circuit - Google Patents
A kind of push-pull type quick response LDO circuit Download PDFInfo
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Abstract
The utility model discloses a kind of push-pull type quick response LDO circuits, including：First control circuit, second control circuit, third control circuit, feedback circuit, load circuit, error amplifier EA, power tube MP；The circuit structure that the utility model is created is relative to existing LDO circuit, good performance is all had in the parameters index such as low-power consumption, large load current, high PSRR, transient response, it especially has outstanding performance in terms of transient response, meets the development need of the following LDO circuit.The circuit structure can be widely applied to SoC chip.
Description
Technical field
The utility model is related to a kind of adjusting electric variable or the system of magnetic variable, more particularly to a kind of LDO (Low
Dropout Regulator, LDO, low pressure difference linear voltage regulator) circuit.
Background technology
Almost all of electronic circuit is required for a stable voltage source, it is maintained within the scope of certain tolerance, with true
Protect correct operation (typical cpu circuit only allows the maximum deviation of voltage source and rated voltage to be no more than ± 3%).Fixation electricity
Pressure is provided by some kinds of voltage-stablizer.LDO circuit is exactly one such voltage-stablizer.
As shown in Figure 1, typical LDO circuit includes：Reference voltage Vref, error amplifier EA, power tube a1, resistance point
Depressor a2, current source a3.The LDO circuit detects output voltage V automatically by resitstance voltage divider a2out, error amplifier EA is continuous
Current source a3 is adjusted to maintain output voltage VoutStablize in rated voltage.There are load transient sound for the LDO circuit of the structure
It should be able to the not high problem of power.However as the continuous development of integrated circuit, traditional LDO structures cannot meet low-power consumption,
The requirements such as large load current, high PSRR, good transient response, therefore there is an urgent need for design new-type circuit.
Utility model content
The purpose of this utility model is to provide a kind of can quickly cope with and loads variation, the LDO electricity with good transient response
Road.
The solution that the utility model solves its technical problem is：A kind of push-pull type quick response LDO circuit, including：
First control circuit, second control circuit, third control circuit, feedback circuit, load circuit, error amplifier EA, power tube
MP；The first control circuit by：PMOS tube M1, M3, NMOS tube M2, capacitance C1, resistance R1 compositions, the drain electrode difference of the M1
With the draining of the M2, one end of the grid of the M3, capacitance C1 are connect, the other end of the capacitance C1 is with the resistance R1's
One end connects, and the grid of the M1 connect with the output end of the error amplifier EA, the source electrode of the M1, the M3 source electrode
It is connect respectively with power vd D, the source electrode of the M2 is connect with ground GND, and the drain electrode of the M3 is another with the resistance R1 respectively
End, the power tube MPGrid connection, the substrate of described M1, M3 connect with the power vd D respectively, the substrate of the M2 and
Described ground GND connections；The second control circuit by：PMOS tube M4, NMOS tube M5, M6 composition, the drain electrode of the M4 respectively with
Drain electrode, the grid connection of the M5, the grid of the M4 are connect with the output end of the error amplifier EA, the source electrode of the M4
It is connect with the power vd D, the grid of the M5 is connect with the grid of the M6, the drain electrode of the M6 and the MPGrid connect
It connects, the source electrode of described M5, M6 are connect with ground GND respectively, and the substrate of the M4 is connect with power vd D, the substrate point of described M5, M6
It is not connect with ground GND；The third control circuit by：PMOS tube M7, NMOS tube M8, M9, operational amplifier A MP compositions, it is described
The inverting input of AMP is connect with the output end of the grid of the M4, the error amplifier EA respectively, the output of the AMP
End is connect with the grid of the M7, and the source electrode of the M7 is connect with power vd D, grid, the M8 of the drain electrode and the M9 of the M7
Drain electrode connection, the drain electrode of the M9 and the MPDrain electrode connection, the source electrode of described M8, M9 with GND connect, the M7's
Substrate is connect with the power vd D, and the substrate of described M8, M9 are connect with ground GND；The feedback circuit by：NMOS tube M10, M11
Composition, the drain electrode of the M10, grid, the M11 grid connect the output voltage of the push-pull type quick response LDO circuit
End, the output voltage terminal and the MPDrain electrode connection, the source electrode of the M10 respectively with the draining of the M11, the error
The in-phase input end of amplifier EA connects, and the substrate of source electrode connection the ground GND, the M11 of the M11 are connect with ground GND；It is described
Load circuit by：Load resistance RL, load capacitance CLComposition, the load resistance RLWith the load capacitance CLAnd connect, it is described negative
Carry resistance RL, load capacitance CLOne end connect output voltage terminal connection, other end GND connections over the ground；The error amplification
The inverting input connection reference voltage V of device EAref。
Further, the power tube MPFor PMOS tube.
Further, the reference voltage VrefFor the output voltage of band-gap reference circuit.
The utility model has the beneficial effects that：The circuit structure of the invention is relative to existing LDO circuit, in low work(
Good performance is all had in the parameters index such as consumption, large load current, high PSRR, transient response, especially in wink
It has outstanding performance in terms of state response, meets the development need of the following LDO circuit.The circuit structure can be widely applied to SoC chip.
Description of the drawings
It is required in being described below to embodiment in order to illustrate more clearly of the technical scheme in the embodiment of the utility model
Attached drawing to be used is briefly described.Obviously, described attached drawing is a part of the embodiment of the utility model, rather than complete
Portion's embodiment, those skilled in the art without creative efforts, can also be obtained according to these attached drawings it
His design scheme and attached drawing.
Fig. 1 is the structural schematic diagram of the LDO circuit in background technology；
Fig. 2 is the structural schematic diagram of the LDO circuit of the invention；
Fig. 3 is to work as load voltage VoutThe situation of change of control loop when raising；
Fig. 4 is to work as load voltage VoutThe situation of change of control loop when reduction.
Specific implementation mode
The technique effect of the design of the utility model, concrete structure and generation is carried out below with reference to embodiment and attached drawing
It clearly and completely describes, to be completely understood by the purpose of this utility model, feature and effect.Obviously, described embodiment
It is a part of the embodiment of the utility model, rather than whole embodiments, it is based on the embodiments of the present invention, the skill of this field
The other embodiment that art personnel are obtained without creative efforts belongs to the model of the utility model protection
It encloses.In addition, all connection/connection relations being previously mentioned in text, not singly refer to component and directly connect, and referring to can be according to specific reality
Situation is applied, by adding or reducing couple auxiliary, to form more preferably coupling structure.Each technology in the invention is special
Sign, can be with combination of interactions under the premise of not conflicting conflict.
Embodiment 1, with reference to figure 2, a kind of push-pull type quick response LDO circuit, including：First control circuit 1, second controls
Circuit 2, third control circuit 3, feedback circuit 4, load circuit 5, error amplifier EA, power tube MP；The power tube MPFor
PMOS tube, the first control circuit 1 by：PMOS tube M1, M3, NMOS tube M2, capacitance C1, resistance R1 compositions, the leakage of the M1
Pole respectively with the draining of the M2, one end of the grid of the M3, capacitance C1 are connect, the other end and the electricity of the capacitance C1
One end connection of R1 is hindered, the grid of the M1 is connect with the output end of the error amplifier EA, the source electrode of the M1, the M3
Source electrode connect respectively with power vd D, the source electrode of the M2 connect with ground GND, and the grid of the M2 connects reference voltage Vb1, institute
State M3 drain electrode respectively with the other end of the resistance R1, the power tube MPGrid connection, described M1, M3 substrate difference
It is connect with the power vd D, the substrate of the M2 is connect with described ground GND；The second control circuit 2 by：PMOS tube M4,
NMOS tube M5, M6 forms, and the drain electrode of the M4 is connect with the drain electrode of the M5, grid respectively, the grid of the M4 and the mistake
The output end of poor amplifier EA connects, and the source electrode of the M4 is connect with the power vd D, the grid of the grid of the M5 and the M6
Pole connects, the drain electrode of the M6 and the MPGrid connection, the source electrode of described M5, M6 connect with ground GND respectively, the M4's
Substrate is connect with power vd D, and the substrate of described M5, M6 are connect with ground GND respectively；The third control circuit 3 by：PMOS tube
M7, NMOS tube M8, M9, operational amplifier A MP composition, the inverting input of the AMP respectively with the grid of the M4, the mistake
The output end of poor amplifier EA connects, noninverting input and the reference voltage V of the AMPb2Connection, the output end of the AMP with
The grid of the M7 connects, and the source electrode of the M7 is connect with power vd D, the leakage of the drain electrode and the grid, M8 of the M9 of the M7
Pole connects, the drain electrode of the M9 and the MPDrain electrode connection, the grid connection reference voltage V of the M8b3, described M8, M9's
Source electrode is connect with ground GND, and the substrate of the M7 is connect with the power vd D, and the substrate of described M8, M9 are connect with ground GND；It is described
Feedback circuit 4 by：NMOS tube M10, M11 forms, the drain electrode of the M10, the grid connection push-pull type of grid, the M11
The output voltage terminal of quick response LDO circuit, the output voltage terminal and the MPDrain electrode connection, the source electrode of the M10 point
Not with the draining of the M11, the in-phase input end of the error amplifier EA is connect, the source electrode connection ground GND of the M11, institute
The substrate for stating M11 is connect with ground GND；The load circuit 5 by：Load resistance RL, load capacitance CLComposition, the load resistance
RLWith the load capacitance CLAnd it connects, the load resistance RL, load capacitance CLOne end connect output voltage terminal connection,
Other end GND connections over the ground；The inverting input connection reference voltage V of the error amplifier EAref.The reference voltage Vref
For the output voltage of band-gap reference circuit, band-gap reference circuit can establish one it is unrelated with power supply and technique, there is temperature
The DC voltage of characteristic improves the performance of LDO circuit to provide a stable voltage Vref for operational amplifier A MP.
For the convenience of description, the draining of the source electrode of the M10, the M11, the in-phase input end of the error amplifier EA
Intersection be point A, the output end of the error amplifier EA, the M1 grids, M4 grids, operational amplifier A MP reverse phase
The intersection of input terminal is point B, the power tube MPGrid, the draining of the M3, the intersection of the drain electrode of the M6 be point
C.The operation principle of the invention is as follows：
Such as Fig. 3, when load changes, i.e., as output voltage VoutWhen raising, the voltage at point A increases, point A and error
The in-phase input end of amplifier EA connects, therefore the voltage at point B increases, and the grid voltage of M1 increases, and the electric current for flowing through M1 subtracts
Small, then the grid voltage of M3 reduces.M3 grid voltages reduce, then the electric current for flowing through M3 increases；When point B voltage increase, M4's
Grid voltage increases, then the electric current for flowing through M5 reduces, and M6 and M5 forms current mirror, therefore the electric current for flowing through M6 also subtracts；The electricity of M3
Stream increases, and the electric current of M6 reduces, therefore the voltage at point C increases.Voltage at point C increases, then flows through MPElectric current reduce；When
Voltage at point B increases, and because it is connected with the inverting input of operational amplifier A MP, therefore the output end voltage of AMP reduces,
The grid voltage of M7 reduces, and M7 is become being connected from original closed state, then the grid voltage of M9 increases, and the electric current for flowing through M9 increases
Greatly；MPCircuit reduce, the electric current of M9 increases, by output voltage VoutIt drags down, steady load voltage.
As Fig. 4 works as output voltage VoutWhen reduction, the voltage at point A reduces, then the voltage of the exit point B of EA reduces, then
The grid voltage of M1 reduces, and the electric current for flowing through M1 increases, then the grid voltage of M3 increases.The grid voltage of M3 increases, and flows through M3
Electric current reduce；When voltage at point B reduces, M4 grid voltages reduce, and the electric current for flowing through M4 increases, then flows through the electric current of M6
Increase；The electric current for flowing through M3 reduces, and the electric current for flowing through M6 increases, then the voltage at point C reduces, and the electric current for flowing through MP increases, will
Output voltage VoutIt draws high, steady load voltage.When voltage at point B reduces, the output end voltage of AMP is high level, because
M7 is PMOS, so M7 is in closed state, is not worked.I.e. third control circuit 3 does not work, to be not drawn into third control in Fig. 4
Circuit 3 processed is as prompt.
Quantitative analysis is carried out to circuit below：Term is explained：I1To flow through the electric current of M1, I2To flow through the electric current of M2, I3For
Flow through the electric current of M3, I4To flow through the electric current of M4, I5To flow through the electric current of M5, I6To flow through the electric current of M6, IPTo flow through MPElectricity
Stream, I8To flow through the electric current of M8, I9To flow through the electric current of M9, I10To flow through the electric current of M10, I11To flow through the electric current of M11；
1. feedback circuit 4
Voltage at point A is with output voltage VoutSynchronous variation.The connection type of M10 connects for diode as shown in Figure 2
It connects, therefore is in saturation region, M11 is likely to be at saturation region, it is also possible to be in linear zone.
1.1 assuming that M11 is in saturation region
VGS11=Vout (3)
VGS10=Vout-VA (4)
I11=I10 (5)
Wherein Ki=μn,Cox(W/L)iI=1,2 ...
It is obtained by formula (1) (2) (3) (4) (5)
Formula (6) derivation is obtained
1.2 when M11 is operated in triode region, and current formula is
VDS11=VA (9)
It can be obtained by formula (1) (5)
It can be obtained by formula (3) (4) (8) (9) (10)
Formula (11) derivation can be obtained
VAIt is A point voltages, VGSIt is the gate source voltage of metal-oxide-semiconductor, VDSIt is the drain-source voltage of CMOS transistor.VTHIt is CMOS tube
Threshold voltage.μnIt is the mobility of electronics, μpIt is the mobility in hole.CoxIt is unit area gate capacitance.W is that conducting channel is wide
Degree, L is conducting channel length, and (W/L) is the breadth length ratio of CMOS transistor.
We can make its value be more than zero by adjusting M10 and M11 breadth length ratios in formula (7), and formula (12) its value is big
In zero.Therefore, the derivative between the voltage and output voltage at point A it can be seen from formula (7) and (12) be just, therefore they
Between proportional relationship.Voltage at point A changes with the variation of output.
2. control circuit part,
2.1 first control circuits 1
As shown in Fig. 2, M1 and M2 is the common-source circuits using current source load.It is leaked if PMOS electric currents are flowed to by source electrode
Pole, the then electric current for flowing through PMOS tube M1 are
VGS1=VDD-VB (14)
Set up an office B voltage variety be Δ VB, then can be obtained by formula (13) (14)
The Δ V when the voltage of point B increasesBFor just, Δ V when reductionBIt is negative.Known to formula (15) when point B voltages increase,
Electric current I1Reduce, when point B voltages reduce, electric current I1Increase.Again because of M2 connection bias voltages, it is equivalent to a current source, electricity
It flows constant, therefore works as I1M3 grid voltages reduce when reduction, I1M3 grid voltages increase when increase.
The electric current for flowing through M3 is
VGS1=VDD-VG3 (17)
If the variable quantity of the grid voltage of M3 is Δ VG3, then can be obtained by formula (16) (17)
By formula (18) it is found that when M3 grid voltages increase I3Reduce, the I when M3 grid voltages reduce3It increases.
2.2 second control circuits 2
PMOS tube M4 in second control circuit 2 and the common-source stage that the connection type of M5 is the load connected using diode
Circuit.It is that load is different, therefore the curent change situation of M1 and M4 is identical from the circuit that M1 and M2 is formed.
The load M5 of M4 is diode connection type, so M5 can be equivalent to a small signal resistance.M5 and M6 and structure
At current mirror, therefore M5 is synchronous variation with the electric current in M6.
Therefore by the analysis to M1 it is found that flowing through the electric current I of M4 when point B voltages increase4Reduce, when point B voltages reduce
Flow through the electric current I of M44Increase.As M6 with M5 curent changes, therefore I4I when reduction6Also reduce I4I when increase6Also increase.
2.3 power tube MP
Flow through MPElectric current be
VGSP=VDD-VC (20)
Output voltage V againoutFor
Vout=Iout·Zout (21)
Iout=α IP (22)
ZoutFor output impedance.
Set up an office C voltage change be Δ VC, then can be obtained by formula (19) (20) (21) (22)
The I when C voltage increases is understood by formula (23)outReduce, Δ VCFor just, output voltage VoutIt reduces, restores normal
State；I when point C voltage reducesoutIncrease, Δ VCFor just, output voltage VoutIt increases, restores normal condition, steady load voltage.
2.4 third control circuits 3
As shown in Fig. 2, M7 connects operational amplifier A MP output ends, M8 meets bias voltage Vb3.M7 and M8 compositions use current source
The common-source stage circuit of load.I8Current formula is
Work as V known to formula (24)GS8When smaller, I8Also smaller.
Under normal circumstances, the voltage of AMP outputs is vdd voltage, thus M7 be in by area because M7 is PMOS tube,
Only when gate source voltage VGS7 is less than threshold voltage, M7 can just be connected.
When point B voltages increase, by operational amplifier inverting input, AMP output voltages are zero at this time, therefore M7 is led
Logical, third control circuit 3 is started to work.M9 grid voltages increase at this time.
The current formula of M9 is
If the variation of M7 grid voltages is Δ VGS9, then can be obtained by formula (25)
By formula (26) it is found that when M9 grid voltages increase, the electric current in M9 increases, by output voltage VoutIt drags down.
By analyzing feedback circuit 4, first control circuit 1, second control circuit 2 it is found that working as output voltage VoutIt increases
When, the voltage at point B increases, the electric current I in M33Increase, the electric current I in M66Reduce, therefore the voltage at point C is raised.Point C
The voltage at place increases, then flows through MPCurrent reduction.By the analysis to third control circuit 3 it is found that the voltage of point B increases,
The output end voltage of operational amplifier A MP reduces, and the grid voltage of M7 reduces, and M7 turn-on control circuits are started to work, therefore M9
Grid voltage be raised, flow through M9 electric current increase.To sum up, as output voltage VoutWhen raising, MPIn electric current reduce, M9
In electric current increase, by output voltage VoutIt drags down, is restored to normal condition, steady load voltage.
As output voltage VoutWhen reduction, the voltage at point B reduces, and the electric current in M3 reduces, and the electric current in M6 increases, because
Voltage at this point C is pulled low, and the electric current for flowing through MP increases, output voltage VoutIt is raised, restores normal condition, steady load
Voltage.
By emulation, the LDO circuit of the invention can within 8ns just the load voltage of LDO circuit can restore
Normal condition has a clear superiority relative to traditional LDO circuit.
The better embodiment of the utility model is illustrated above, but the invention be not limited to it is described
Embodiment, those skilled in the art can also make various equivalent changes without departing from the spirit of the present invention
Type or replacement, these equivalent modifications or replacement are all contained in the application claim limited range.
Claims (3)
1. a kind of push-pull type quick response LDO circuit, which is characterized in that including：First control circuit, second control circuit,
Three control circuits, feedback circuit, load circuit, error amplifier EA, power tube MP；
The first control circuit by：PMOS tube M1, M3, NMOS tube M2, capacitance C1, resistance R1 compositions, the drain electrode point of the M1
Not with the draining of the M2, one end of the grid of the M3, capacitance C1 are connect, the other end of the capacitance C1 and the resistance R1
One end connection, the grid of the M1 connect with the output end of the error amplifier EA, the source electrode of the M1, the M3 source
Pole is connect with power vd D respectively, and the source electrode of the M2 is connect with ground GND, and the drain electrode of the M3 is another with the resistance R1 respectively
One end, the power tube MPGrid connection, the substrate of described M1, M3 connect with the power vd D respectively, the substrate of the M2
It is connect with described ground GND；
The second control circuit by：PMOS tube M4, NMOS tube M5, M6 composition, the drain electrode leakage with the M5 respectively of the M4
Pole, grid connection, the grid of the M4 are connect with the output end of the error amplifier EA, the source electrode of the M4 and the power supply
VDD connections, the grid of the M5 are connect with the grid of the M6, the drain electrode of the M6 and the MPGrid connection, the M5,
The source electrode of M6 is connect with ground GND respectively, and the substrate of the M4 is connect with power vd D, the substrate of described M5, M6 respectively with ground GND
Connection；
The third control circuit by：PMOS tube M7, NMOS tube M8, M9, operational amplifier A MP compositions, the reverse phase of the AMP are defeated
Enter end to connect with the output end of the grid of the M4, the error amplifier EA respectively, the output end of the AMP is with the M7's
Grid connects, and the source electrode of the M7 is connect with power vd D, and the drain electrode of the M7 is connect with the drain electrode of the grid of the M9, M8, institute
State the drain electrode of M9 and the MPDrain electrode connection, the source electrode of described M8, M9 connect with ground GND, the substrate of the M7 and the electricity
The substrate of source VDD connections, described M8, M9 is connect with ground GND；
The feedback circuit by：NMOS tube M10, M11 forms, the drain electrode of the M10, grid, the M11 grid connection described in
The output voltage terminal of push-pull type quick response LDO circuit, the output voltage terminal and the MPDrain electrode connection, the M10's
Source electrode respectively with the draining of the M11, the in-phase input end of the error amplifier EA is connect, the source electrode connection ground of the M11
The substrate of GND, described M10, M11 are connect with ground GND；
The load circuit by：Load resistance RL, load capacitance CLComposition, the load resistance RLWith the load capacitance CLAnd
It connects, the load resistance RL, load capacitance CLOne end connect output voltage terminal connection, other end GND connections over the ground；
The inverting input connection reference voltage V of the error amplifier EAref。
2. a kind of push-pull type quick response LDO circuit according to claim 1, it is characterised in that：The power tube MPFor
PMOS tube.
3. a kind of push-pull type quick response LDO circuit according to claim 1 or 2, it is characterised in that：The reference voltage
VrefFor the output voltage of band-gap reference circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721501412.9U CN207992862U (en) | 2017-11-10 | 2017-11-10 | A kind of push-pull type quick response LDO circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721501412.9U CN207992862U (en) | 2017-11-10 | 2017-11-10 | A kind of push-pull type quick response LDO circuit |
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| Publication Number | Publication Date |
|---|---|
| CN207992862U true CN207992862U (en) | 2018-10-19 |
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|---|---|---|---|
| CN201721501412.9U Withdrawn - After Issue CN207992862U (en) | 2017-11-10 | 2017-11-10 | A kind of push-pull type quick response LDO circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107783588A (en) * | 2017-11-10 | 2018-03-09 | 佛山科学技术学院 | A kind of push-pull type quick response LDO circuit |
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2017
- 2017-11-10 CN CN201721501412.9U patent/CN207992862U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107783588A (en) * | 2017-11-10 | 2018-03-09 | 佛山科学技术学院 | A kind of push-pull type quick response LDO circuit |
| CN107783588B (en) * | 2017-11-10 | 2023-11-28 | 佛山科学技术学院 | Push-pull type quick response LDO circuit |
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