CN207924661U - Instrument bus host circuit device - Google Patents
Instrument bus host circuit device Download PDFInfo
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- CN207924661U CN207924661U CN201820176631.2U CN201820176631U CN207924661U CN 207924661 U CN207924661 U CN 207924661U CN 201820176631 U CN201820176631 U CN 201820176631U CN 207924661 U CN207924661 U CN 207924661U
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- triode
- circuit
- power supply
- data
- bus
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Abstract
The utility model is related to a kind of instrument bus host circuit devices, including data transmission circuit, electric current loop power supply circuit, receiving test circuit and waveform shaping circuit, data transmission circuit to issue data for realizing with direct current carrier data mode；Electric current loop power supply circuit is for loading low pressure to bus；Receiving test circuit is used to be loaded into the data that the judgement of the voltage in bus receives by detecting electric current loop power supply circuit；Waveform shaping circuit adjusts the waveform in bus by the extra electricity of pliotron Absorption Capacitance coupling effect.The utility model can improve the speed and reliability of communication, improve data transmission stability.
Description
Technical field
The utility model is related to field of circuit technology, more particularly to a kind of instrument bus host circuit device.
Background technology
Two lines bus is one kind relative to four-wire system（Liang Gen supply lines, two communication lines）, by supply lines and signal
Line is combined into one, and realizes signal and power supply shares the technology of a bus.Two lines bus saves construction and cable cost, to existing
Field construction and later maintenance bring great convenience.In fire-fighting, instrument, sensor, the fields such as Industry Control are widely applied.
Typical double bus technology has M-BUS, fire-fighting bus etc..Current bus host circuit is poor in the prevalence of data transmission stability
Defect.
Utility model content
The purpose of this utility model is that improving the above-mentioned deficiency in the presence of the prior art, a kind of meter bus master is provided
Machine circuit device, to improve the stability of data transmission.
In order to realize that above-mentioned purpose of utility model, the utility model embodiment provide following technical scheme：
A kind of instrument bus host circuit device, including data transmission circuit, electric current loop power supply circuit, receiving test circuit
And waveform shaping circuit, wherein
The input terminal of data transmission circuit connects DC power supply, and data transmission circuit is for realizing with direct current carrier data side
Formula issues data；
The output end of the input terminal connection data transmission circuit of electric current loop power supply circuit, electric current loop power supply circuit is for loading
In low pressure to bus；
The output end of the input terminal connection electric current loop power supply circuit of receiving test circuit, receiving test circuit is for passing through inspection
It surveys electric current loop power supply circuit and is loaded into the data that the judgement of the voltage in bus receives；
The output end of the input terminal connection receiving test circuit of waveform shaping circuit, waveform shaping circuit pass through three pole of power
The extra electricity of pipe Absorption Capacitance coupling effect adjusts the waveform in bus.
Further, in above-mentioned instrument bus host circuit device, the data transmission circuit includes metal-oxide-semiconductor, the one or three
Pole pipe, the anode of the drain electrode connection DC power supply of metal-oxide-semiconductor, the drain electrode of metal-oxide-semiconductor connect the collection of the first triode by a resistance
The base stage of electrode, the first triode connects data emission port, the emitter ground connection of the first triode by a resistance.Pass through
Such mode realizes that direct current carrier data mode issues data, is not necessarily to electrical isolation, not only may be implemented to communicate but also may be implemented to supply
Electricity.
Further, in above-mentioned instrument bus host circuit device, the electric current loop power supply circuit includes the integrated electricity of power supply
Road chip, the second triode, the first divider resistance and the second divider resistance, the power input connection of power IC chip
The anode of DC power supply, the ground terminal of power IC chip connect the collector of the second triode, the base of the second triode
Pole connects the ports CONM, the emitter ground connection of the second triode, and the collector of the second triode is also attached to concatenated first point
Between piezoresistance and the second divider resistance, the other end of the first divider resistance is connected to the power supply output of power IC chip
End, the other end ground connection of the second divider resistance.
Further, in above-mentioned instrument bus host circuit device, the receiving test circuit includes third transistor, number
It is connected to the power output end of power IC chip according to reception resistance and switching diode, one end of data receiver resistance,
The emitter of one end of other end connecting valve diode, third transistor is connected to the power supply output of power IC chip
End, base stage is connected to the other end of switching diode, while base stage also connects the ports SHORT, collector connection by a resistance
Receiving port.It can realize and receive data using electric current loop and detect bus short circuit situation, improve the reliability of system.
Further, in above-mentioned instrument bus host circuit device, the waveform shaping circuit includes the 4th triode, the
The base stage of five triodes, the 6th triode and the 7th triode, the 4th triode connects data emission port, collector connection
The base stage of 5th triode, and 5V voltages are connected, the collector of collector the 6th triode of connection of the 5th triode, the six or three
The source electrode of the emitter connection metal-oxide-semiconductor of pole pipe, the base stage of the 6th triode connect the 7th transistor emitter, the 7th triode
Base stage connects the ground terminal of power IC chip, the grounded collector of the 7th triode by another switching diode.
In this way power tube design, can the energy in parasitic capacitance by control the 7th opening for triode by consume,
Make waveform response faster, to improve the speed and reliability of communication.
Compared with prior art, the beneficial effects of the utility model：
Data are issued by direct current carrier data mode, are not necessarily to electrical isolation, not only may be implemented to communicate but also may be implemented to supply
Electricity.
Data are received using electric current loop, and bus short circuit situation can be detected, improve the reliability of system.
Power tube design can fall the energy expenditure in parasitic capacitance, make waveform response faster, to improve communication
Speed and reliability.
Description of the drawings
It, below will be to required use in embodiment in order to illustrate more clearly of the technical solution of the utility model embodiment
Attached drawing be briefly described, it should be understood that the following drawings illustrates only some embodiments of the utility model, therefore does not answer
It is counted as the restriction to range, for those of ordinary skill in the art, without creative efforts, also
Other relevant attached drawings can be obtained according to these attached drawings.
Fig. 1 is the electrical schematic diagram for the instrument bus host circuit device that the utility model embodiment provides.
Fig. 2 is to issue data waveform figure.
Fig. 3 is the level waveforms figure on A points and bus in Fig. 1.
Specific implementation mode
Below in conjunction with attached drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out clear
Chu is fully described by, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole realities
Apply example.The component of the utility model embodiment being usually described and illustrated herein in the accompanying drawings can be come with a variety of different configurations
Arrangement and design.Therefore, the detailed description of the embodiments of the present invention to providing in the accompanying drawings is not intended to limit below
Claimed the scope of the utility model, but it is merely representative of the selected embodiment of the utility model.Based on the utility model
Embodiment, the every other embodiment that those skilled in the art are obtained without making creative work, all
Belong to the range of the utility model protection.
It should be noted that：Similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined, then it further need not be defined and explained in subsequent attached drawing in a attached drawing.Meanwhile it is new in this practicality
In the description of type, term " first ", " second " etc. are only used for distinguishing description, are not understood to indicate or imply relatively important
Property.
Referring to Fig. 1, a kind of instrument bus host circuit device is provided in the present embodiment, the instrument bus host circuit
Device includes data transmission circuit 10, electric current loop power supply circuit 20, receiving test circuit 30 and waveform shaping circuit 40, wherein
The input terminal of data transmission circuit 10 connects DC power supply, and data transmission circuit 10 is for realizing with direct current carrier number
Data are issued according to mode；
The output end of the input terminal connection data transmission circuit 10 of electric current loop power supply circuit 20, electric current loop power supply circuit 20 are used
In loading in low pressure to bus；
The output end of the input terminal connection electric current loop power supply circuit 20 of receiving test circuit 30, receiving test circuit 30 are used for
It is loaded into the data that the judgement of the voltage in bus receives by detecting electric current loop power supply circuit 20；
The output end of the input terminal connection receiving test circuit 30 of waveform shaping circuit 40, waveform shaping circuit 40 pass through work(
The extra electricity of rate triode Absorption Capacitance coupling effect adjusts the waveform in bus.
Referring to Fig. 1, specifically, in the present embodiment, the data transmission circuit 10 includes metal-oxide-semiconductor Q8, the first triode
The positive VIN+ of the drain electrode connection DC power supply of Q2, metal-oxide-semiconductor Q8, the drain electrode of metal-oxide-semiconductor Q8 pass through a resistance R5 connection the one or three
The collector of pole pipe Q2, the base stage of the first triode Q2 is by a resistance R9 connection data emission ports T_DATA, and the one or three
The emitter of pole pipe Q2 is grounded.
By the control to the ports T_DATA, turning on and off for Q2 triodes is realized, to realize to Q8 metal-oxide-semiconductors
The data of T_DATA are loaded into the power supply of power supply up, to make the power supply electricity in bus by control by the switch of metal-oxide-semiconductor
The plain existing level with data waveform, and high level part therein is realized and provides work capacity to slave.Again in order to give from
Machine provides enough electric energy, so having carried out specific definition to the data waveform issued, as shown in Figure 2.Bus is with 1ms for 1
A period will send out the high level of the low level+0.8ms of 0.2ms if no data issues in a cycle；If one
Period has data distributing will be in 1ms specifically to encode transmission data.And data are in unit period（0.1ms）It is all
The level of high level is defined as " 1 " in binary system, to there is rising edge to be defined as " 0 " in binary system in unit period, this
Sample can send downwards communication data.Thus it can also be seen that when it is " 1 " to issue data, systems stay to externally fed,
When data are " 0 ", system also has half the time that can continue output power supply, thus can realize that energy is defeated to greatest extent
Go out.It can be seen that the bus can provide enough electric energy, can also realize communication, and the two is combined into one, without electrically every
From.
Referring to Fig. 1, in the present embodiment, the electric current loop power supply circuit 20 includes that power IC chip U1 (is used
LM317 chips), the second triode Q3, the first divider resistance R2 and the second divider resistance R6, the electricity of power IC chip U1
The anode of source input terminal connection DC power supply, the ground terminal of power IC chip U1 connect the current collection of the second triode Q3
Pole, the ports base stage connection CONM of the second triode Q3, the emitter ground connection of the second triode Q3, the current collection of the second triode Q3
Pole is also attached between concatenated first divider resistance R2 and the second divider resistance R6, the other end connection of the first divider resistance R2
It is grounded in the other end of the power output end of power IC chip U1, the second divider resistance R6.
By two electric resistance partial pressures of R2, R6 to LM317（U1）Reference voltage, then the control by the ports CONM to Q3 are provided
It realizes the control to reference voltage, the voltage change of A points may be implemented, when the ports CONM are high level, the voltage of A points is
1.25V, when the ports CONM are low level, A points are 8V or so.When T_DATA transmission datas, the waveform and T_DATA of CONM
On the contrary, when T_DATA no datas issue, CONM is low level.Level such as Fig. 3 institutes on the level and bus of corresponding A points
Show, by oscillogram it is found that the effect of electric current loop power supply circuit 20 is mainly the low of that 0.2ms when not having to send out data in bus
Level draws high 8V or so, and transmission data part, without influence, this is done to can be realized in periodical 0.2ms low levels
Electric current loop data transmission, that is, prepare for the part of bus reception data.
Referring to Fig. 1, in the present embodiment, the receiving test circuit 30 includes third transistor Q1, data receiver resistance
One end of R1 and switching diode D1, data receiver resistance R1 are connected to the power output end of power IC chip U1, separately
One end of one end connecting valve diode D1, the emitter of third transistor Q1 are connected to the power supply of power IC chip U1
Output end, base stage is connected to the other end of switching diode D1, while base stage also connects the ports SHORT, current collection by a resistance
Pole connects receiving port.
By R1, D1, Q1, these three components realize that the data receiver of electric current loop section is handled, when slave is periodically being
When generating the electric current with data on the 8V level of 0.2ms, this electric current can generate voltage difference between 1 and 3 feet of R1 and D1,
Be exactly the voltage ratio A points of B points in Fig. 1 voltage it is low, this makes it possible to make Q1 be connected, to there is corresponding level on C points
Waveform can thus obtain the data information of C points, and to obtain the data sent out on slave, here it is the data receivers of electric current loop
Principle.And between bus level is the high period of 24V, the voltage of A points is always 8V, if during this period of time bus occurs
Short circuit, then the voltage of B points will appear bust, thus level change can occur in the ports SHORT, can detect bus short circuit
The case where.
Referring to Fig. 1, in the present embodiment, the waveform shaping circuit 40 include the 4th triode Q7, the 5th triode Q6,
The base stage of 6th triode Q9 and the 7th triode Q10, the 4th triode Q7 connect data emission port T_DATA, collector
The base stage of the 5th triode Q6 is connected, and connects 5V voltages, the collector of the 5th triode Q6 connects the collection of the 6th triode Q9
Electrode, the source electrode of the emitter connection metal-oxide-semiconductor of the 6th triode Q9, the base stage of the 6th triode Q9 connect the 7th triode Q10
Emitter, the ground connection that the base stage of the 7th triode Q10 passes through another switching diode D2 connection power IC chips U1
End, the grounded collector of the 7th triode Q10.
It is influenced by circuit parasitic capacitance in bus level change procedure, after Q8 shutdowns, bus voltage will not be fast
Speed reduces, and thus affects the reliability of communication, the energy in parasitic capacitance can be passed through control by waveform shaping circuit 40
Opening for Q10 and consume, make waveform response faster, to improve the speed and reliability of communication.
Above description is only a specific implementation of the present invention, but the scope of protection of the utility model is not limited to
In this, any one skilled in the art within the technical scope disclosed by the utility model, can readily occur in variation
Or replace, it should be covered within the scope of the utility model.
Claims (5)
1. instrument bus host circuit device, which is characterized in that including data transmission circuit, electric current loop power supply circuit, receive inspection
Slowdown monitoring circuit and waveform shaping circuit, wherein
The input terminal of data transmission circuit connects DC power supply, and data transmission circuit is for realizing under direct current carrier data mode
Send out data；
The output end of the input terminal connection data transmission circuit of electric current loop power supply circuit, electric current loop power supply circuit is for loading low pressure
Onto bus；
The output end of the input terminal connection electric current loop power supply circuit of receiving test circuit, receiving test circuit are used for by detecting electricity
Stream ring power supply circuit is loaded into the voltage in bus and judges the data received；
The output end of the input terminal connection receiving test circuit of waveform shaping circuit, waveform shaping circuit are inhaled by pliotron
The extra electricity of capacitance coupling effect is received, the waveform in bus is adjusted.
2. instrument bus host circuit device according to claim 1, which is characterized in that the data transmission circuit includes
Metal-oxide-semiconductor, the first triode, the anode of the drain electrode connection DC power supply of metal-oxide-semiconductor, the drain electrode of metal-oxide-semiconductor pass through a resistance connection the
The base stage of the collector of one triode, the first triode connects data emission port, the hair of the first triode by a resistance
Emitter grounding.
3. instrument bus host circuit device according to claim 2, which is characterized in that the electric current loop power supply circuit packet
Include power IC chip, the second triode, the first divider resistance and the second divider resistance, the electricity of power IC chip
The anode of source input terminal connection DC power supply, the ground terminal of power IC chip connect the collector of the second triode, the
The ports base stage connection CONM of two triodes, the emitter ground connection of the second triode, the collector of the second triode are also attached to
Between concatenated first divider resistance and the second divider resistance, the other end of the first divider resistance is connected to power IC core
The power output end of piece, the other end ground connection of the second divider resistance.
4. instrument bus host circuit device according to claim 3, which is characterized in that the receiving test circuit includes
One end of third transistor, data receiver resistance and switching diode, data receiver resistance is connected to power IC chip
Power output end, one end of other end connecting valve diode, the emitter of third transistor is connected to power IC
The power output end of chip, base stage is connected to the other end of switching diode, while base stage also connects the ends SHORT by a resistance
Mouthful, collector connects receiving port.
5. instrument bus host circuit device according to claim 4, which is characterized in that the waveform shaping circuit includes
The base stage of 4th triode, the 5th triode, the 6th triode and the 7th triode, the 4th triode connects data transmitting terminal
Mouthful, collector connects the base stage of the 5th triode, and connects 5V voltages, and the collector of the 5th triode connects the 6th triode
Collector, the source electrode of the emitter connection metal-oxide-semiconductor of the 6th triode, the base stage of the 6th triode connects the 7th triode emission
Pole, the base stage of the 7th triode connect the ground terminal of power IC chip, the seven or three pole by another switching diode
The grounded collector of pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820176631.2U CN207924661U (en) | 2018-02-01 | 2018-02-01 | Instrument bus host circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820176631.2U CN207924661U (en) | 2018-02-01 | 2018-02-01 | Instrument bus host circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207924661U true CN207924661U (en) | 2018-09-28 |
Family
ID=63602479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820176631.2U Expired - Fee Related CN207924661U (en) | 2018-02-01 | 2018-02-01 | Instrument bus host circuit device |
Country Status (1)
| Country | Link |
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| CN (1) | CN207924661U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109714236A (en) * | 2019-02-26 | 2019-05-03 | 北京强联通讯技术有限公司 | The bus-powered and means of communication, device and storage medium |
-
2018
- 2018-02-01 CN CN201820176631.2U patent/CN207924661U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109714236A (en) * | 2019-02-26 | 2019-05-03 | 北京强联通讯技术有限公司 | The bus-powered and means of communication, device and storage medium |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180928 Termination date: 20210201 |
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| CF01 | Termination of patent right due to non-payment of annual fee |