CN207869089U - Phaselocked loop start-up circuit - Google Patents
Phaselocked loop start-up circuit Download PDFInfo
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- CN207869089U CN207869089U CN201820823916.0U CN201820823916U CN207869089U CN 207869089 U CN207869089 U CN 207869089U CN 201820823916 U CN201820823916 U CN 201820823916U CN 207869089 U CN207869089 U CN 207869089U
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- transistor
- phase inverter
- input terminal
- phaselocked loop
- loop start
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Abstract
The phaselocked loop start-up circuit of the utility model, including nor gate, the first NAND gate, the second NAND gate, from counter, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter, transmission gate, the first transistor, second transistor, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor and the 8th transistor.The utility model can make phaselocked loop within the controllable time, it is particular level by internal important node fast preset, shorten PLL to start and locking time, and the unlatching order of entire loop can be controlled, make its will not because by technique, voltage, temperature influence due to change.
Description
Technical field
The utility model is related to IC design fields, and in particular to a kind of phaselocked loop start-up circuit.
Background technology
With the fast development of IC design and CMOS technology, integrated circuit comes into system level chip
（System on Chip, SoC）Design phase.With constantly carrying for complexity of electronic systems, integrated level and working frequency of chip
Height, the requirement to the distributed mass and stability of on piece clock are also higher and higher.Phaselocked loop（Phase Locked Loop,PLL）
As the clock source of system on chip, it is the critical function module in modern integrated circuits design, is widely used in all kinds of SoC cores
In piece.
Phaselocked loop is the degeneration factor that output phase is compared with input phase, utilizes externally input reference signal
The frequency and phase of control loop internal oscillation signal.Conventional phase locked loops start-up circuit is as shown in Figure 1, in input signal START
Before coming, switch S1 and S2 are opened, and S3 is closed, and VCTL points are pulled to vdd voltage；After START signal comes, S2 is closed, S1
It is opened with S3, due to the presence of loop filtering capacitance, VCTL signals are slowly dragged down by VREF1 signals until comparator overturning, production
The control signal of modules in raw PLL, and S1 is closed, start-up course terminates.Conventional phase locked loops start-up circuit is by two moulds
Quasi- voltage VREF1, VREF2 are compared with comparator, the enable signal of the signal of generation as entire loop, due to comparator
Offset voltage（offset）And the time of VCTRL drop-downs can all be influenced by technique, voltage, temperature, therefore comparison result is simultaneously
Inaccuracy, and the time of comparator overturning and be not fixed, it is abnormal to may result in phaselocked loop starting state.
Invention content
Goal of the invention：In order to overcome the deficiencies in the prior art, the utility model to provide a kind of phaselocked loop startup control
Circuit processed enhances the stability and reliability of phaselocked loop to accelerate the startup of phaselocked loop, shorten locking time.
Technical solution：In order to solve the above technical problems, phaselocked loop start-up circuit provided by the utility model, including or it is non-
Door, the first NAND gate, the second NAND gate, from counter, the first phase inverter, the second phase inverter, third phase inverter, the 4th reverse phase
Device, the 5th phase inverter, transmission gate, the first transistor, second transistor, third transistor, the 4th transistor, the 5th transistor,
6th transistor, the 7th transistor and the 8th transistor, wherein：One input terminal of the nor gate is connected to the Q of counter
Output end, the input terminal CLKN of another input termination phaselocked loop start-up circuit, output end are connected to the CK input terminals of counter；
One input terminal of first NAND gate is connected to the QN output ends of counter, another input termination phaselocked loop start-up circuit
Input terminal CLKP, output end is connected to the CN input terminals of counter；The Q output from counter also connects the first reverse phase
The output end LOOP_ST of the input terminal and phaselocked loop start-up circuit of device and third phase inverter, RESET input connect phaselocked loop startup
The input terminal RESET of circuit；The grid of the input terminal and second transistor of output the second phase inverter of termination of first phase inverter
End；The grid end of output the 5th transistor and the 7th transistor of termination of second phase inverter；The output of the third phase inverter
One input terminal of termination and the second NAND gate；Another input of second NAND gate terminates the defeated of phaselocked loop start-up circuit
Enter and holds RESET, the input terminal of output the 4th phase inverter of termination；The grid of output the 8th transistor of termination of 4th phase inverter
End；The input terminal RESET of input termination phaselocked loop start-up circuit, the grid end of the first transistor and the transmission of 5th phase inverter
One control terminal of door, another control terminal, the grid end of the 6th transistor and the 4th transistor of output termination transmission gate；It is described
Second transistor, the 7th transistor source are connected, and connect the 8th transistor, the drain terminal of the 5th transistor and the 6th transistor, first
The source of transistor, the second transistor, the 7th transistor drain terminal are connected, and meet the output end V1 of phaselocked loop start-up circuit；Institute
State the source ground connection of the 5th transistor；The 8th source transistor termination power Vdd；6th transistor, the first transistor
Drain terminal is connected, and connects the drain terminal of third transistor and the input terminal of transmission gate；The drain terminal connects the output end and third of transmission gate
The source of transistor；4th transistor and third transistor source ground connection.
It is described as a preferred implementation manner, to include at least three d type flip flops from counter, wherein first D is touched
Input terminal CK, CN of device are sent out respectively as input terminal CK, CN from counter, output end Q, QN of the last one d type flip flop
Respectively as output end Q, QN from counter, it is located at intermediate d type flip flop, input terminal CK, CN connect previous d type flip flop
Output end Q, QN.
As a preferred implementation manner, the first transistor, second transistor, third transistor, the 4th transistor,
5th transistor is N-type transistor.
The 6th transistor, the 7th transistor and the 8th transistor are P-type crystal as a preferred implementation manner,
Pipe.
As a preferred implementation manner, first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter,
5th phase inverter is TTL not circuits.
Advantageous effect：The utility model compared with prior art, has following substantive features and progress：
1）The present invention can make phaselocked loop within the controllable time, be particular level by internal important node fast preset,
Shorten PLL startups and locking time；
2）The present invention can control the unlatching order of entire loop, make by exporting clock count to VCO from counter
It will not change due to being influenced by technique, voltage, temperature.
Description of the drawings
Fig. 1 is conventional phase locked loops start-up circuit figure.
Fig. 2 is the utility model phaselocked loop start-up circuit figure.
Fig. 3 is the structure diagram of the utility model locking phase loop section.
Fig. 4 is from counter circuit diagram.
Specific implementation mode
In the following with reference to the drawings and specific embodiments, the technical solution of the utility model is further illustrated.
As shown in Fig. 2, phaselocked loop start-up circuit 201 include nor gate 101, the first NAND gate 102, the second NAND gate 107,
It is anti-from counter 103, the first phase inverter 104, the second phase inverter 105, third phase inverter 106, the 4th phase inverter the 108, the 5th
Phase device 109, transmission gate 110, the first transistor MN1, second transistor MN2, third transistor MN3, the 4th transistor MN4,
Five transistor MN5, the 6th transistor MP1, the 7th transistor MP2 and the 8th transistor MP3, the connection relation tool between each component
Body is as follows：
The input terminal RESET of phaselocked loop start-up circuit 201 connects the input terminal of phase inverter 109, and phase inverter 109 provides for circuit
The signal opposite with input signal RESET.
MN3, MN4 source are grounded, and MN4 drain terminals connect the output end of the grid and transmission gate 110 of MN3, and MN3 drain terminals connect transmission gate
One control terminal of 110 input terminal, MN4 grids and transmission gate 110 connects the output end of phase inverter 109, transmission gate 110 it is another
The input terminal RESET of control termination phaselocked loop start-up circuit 201.
One transmission gate is formed by a P pipes MP1 and a N pipes MN1, N, P pipe source are connected, and are connected on the drain terminal of MP3；Leakage
End is connected, and is connected on the input terminal of the drain terminal and transmission gate 110 of MN3.The grid of MP1 connects the output end of phase inverter 109 and the grid of MN4
Pole；The grid of MN1 meets the input terminal RESET of phaselocked loop start-up circuit 201.MP3 provides high potential for VC, source termination power Vdd,
Grid connects the output end of phase inverter 108.
One input terminal of nor gate 101 is connected to the Q output of counter 103, another input termination phaselocked loop opens
The input terminal CLKN of dynamic circuit 201, output end are connected to the CK input terminals of counter 103；One input termination of NAND gate 102
From the QN output ends of counter 103, the input terminal CLKP of another input termination phaselocked loop start-up circuit 201, output termination
From the CN input terminals of counter 103.The output of nor gate 101 and NAND gate 102 is a pair of of reverse signal.As a kind of specific
Embodiment, from counter 103 by n（n≥3）A d type flip flop composition, as shown in figure 4, the input terminal CK of d type flip flop 301,
CN connects the output end of the output end and NAND gate 102 of nor gate 101 respectively, and output end Q, QN connect the input of d type flip flop 302 respectively
Hold CN, CK.N d type flip flop can be connect between d type flip flop 302 and 303 according to demand, connection is same as described above.If counted from adding
The number for the d type flip flop for including in device 103 is even number, then output end Q, QN of d type flip flop 301 connect d type flip flop 302 respectively
Input terminal CK, CN, output end Q, QN of n-th/2D triggers connect respectively（n+1）Output end CN, CK of/2 d type flip flops.D is touched
Output end Q, QN feedback for sending out device 303 is connected to input terminal, plays the role of two divided-frequency, so will be in meter full 2 from counter 103（n-1）The output signal LOOP_ST of phaselocked loop start-up circuit 201 is just exported after a period.
The input terminal of phase inverter 104,106 is connected to from the output end Q of counter 103.Phase inverter 106 output termination with
One input terminal of NOT gate 107, the input terminal RESET of another input termination phaselocked loop start-up circuit 201 of NAND gate 107,
The output end signal of control NAND gate 107 is set to 1 or becomes with the output end LOOP_ST signals of phaselocked loop start-up circuit 201
Change.107 output end of NAND gate connects the input terminal of phase inverter 108, and the grid of the output termination MP3 of phase inverter 108 controls MP3's
Switch, to control charging of the high level to VC points.
The output end of phase inverter 104 connects the input terminal of phase inverter 105 and the grid of MN2, the output termination of phase inverter 105
The grid of MP2, MN5, MN2, MP2 form charge and discharge of the transmission gate control VC to V1, and source is connected, connect MP3, MN5 drain terminal and
The source of MP1, MN1；Drain terminal is connected, and meets the output end V1 of phaselocked loop start-up circuit 201.The source of MN5 is grounded, and is VC in circuit
Point provides discharge path.
Above-mentioned phaselocked loop start-up circuit 201 and voltage controlled oscillator（VCO）, frequency divider（DIVIDER）203, phase frequency detector
（PFD）204 connection relation is as shown in Figure 3.When RESET=0, entire phaselocked loop is in reset state.RESET signal is inverted
Device 109, net01 signals are 1, MN1, MP1 cut-off.RESET signal passes through NAND gate 107, net02 signals is set to 1, by anti-
Phase device 108 makes MP3 input signals cause pipe to be opened for 0, and VC points are started to charge up to high level Vdd.At this time because of RESET=0, certainly
Counter 103 does not enable, and LOOP_ST signals are 0, by phase inverter 104, net03 signals is made to be 1, MN2 input signals by low
Pipe is caused to be opened to height, then inverted device 105, it is 0 to make net04 signals be 0, MP2 input signals, and pipe is opened, and MN5 is cut
Only, high level is transmitted to V1 points by VC points.RESET is 0, inverted device 109, make net01 signals be 1, MN4 input signals by low
Cause pipe to be opened to height, the high level of MN3 grids is pulled low to 0, avoids generating unknown state Z.
As RESET=1, entire phaselocked loop starts to start, RESET signal pass through NAND gate 107, make net02 signals with
LOOP_ST changes, and it is 1 that LOOP_ST signals, which are 0, MP3 input signals, at this time, pipe cut-off；MP2, MN2 are kept it turning on, and MN5 is protected
Cut-off is held, VC, V1 keep high level；Meanwhile the inverted device 109 of RESET signal, it is 0 to make net01 signals, and MN1, MP1 are opened,
MN4 ends, and V1 starts to discharge with VC points, the drain terminal charging of MN3；Transmission gate 110 is opened, and high level is passed by MN3 drain terminals through net05
To MN3 grids, its input signal is made to cause pipe to be opened from low to high, MN3 drain terminal signals are pulled low.
RESET signal remains 1, voltage controlled oscillator（VCO）202, it is enabled from counter 103, when V1 discharges with VC
To certain particular level（It is related with VCO design parameters）, voltage controlled oscillator（VCO）202 start to shake, and export CLKN, CLKP signal,
V1 continues to decline at this time；After CLK signal from counter by counting N number of period（It can be arranged by counter）, output refers to
Showing that signal LOOP_ST signals are 1, inverted device 104, it is 0 to make net03 signals, inverted device 105, and it is 1 to make net04 signals,
MN2, MP2 end, and V1 points are hanging, and particular level is kept no longer to decline.MN5 is connected, and VC point voltages are pulled down to 0.Frequency divider
（DIVIDER）203, phase frequency detector（PFD）204 are controlled the start-up operation that is enabled by LOOP_ST signals, and entire loop is beaten
It opens, phaselocked loop start-up course terminates.
Claims (5)
1. a kind of phaselocked loop start-up circuit, including nor gate（101）, the first NAND gate（102）, the second NAND gate 107, from plus meter
Number device（103）, the first phase inverter（104）, the second phase inverter（105）, third phase inverter（106）, the 4th phase inverter（108）,
Five phase inverters（109）, transmission gate（110）, the first transistor（MN1）, second transistor（MN2）, third transistor MN3, the 4th
Transistor（MN4）, the 5th transistor（MN5）, the 6th transistor（MP1）, the 7th transistor（MP2）With the 8th transistor（MP3）,
It is characterized in that：The nor gate（101）An input terminal be connected to counter（103）Q output, another input terminal
Connect phaselocked loop start-up circuit（201）Input terminal CLKN, output end is connected to counter（103）CK input terminals；Described first
NAND gate（102）An input terminal be connected to counter（103）QN output ends, another input termination phaselocked loop start electricity
Road（201）Input terminal CLKP, output end is connected to counter（103）CN input terminals；It is described from counter（103）Q
Output end also connects the first phase inverter（104）With third phase inverter（106）Input terminal and phaselocked loop start-up circuit（201）Output
LOOP-ST, RESET input is held to connect phaselocked loop start-up circuit（201）Input terminal RESET；First phase inverter（104）'s
Output the second phase inverter of termination（105）Input terminal and second transistor（MN2）Grid end；Second phase inverter（105）'s
Output the 5th transistor of termination（MN5）With the 7th transistor（MP2）Grid end；The third phase inverter（106）Output termination
With the second NAND gate（107）An input terminal；Second NAND gate（107）Another input termination phaselocked loop start electricity
Road（201）Input terminal RESET, output termination the 4th phase inverter（108）Input terminal；4th phase inverter（108）It is defeated
Go out the 8th transistor of termination（MP3）Grid end；5th phase inverter（109）Input terminate phaselocked loop start-up circuit（201）
Input terminal RESET, the first transistor（MN1）Grid end and transmission gate（110）A control terminal, output termination transmission gate
（110）Another control terminal, the 6th transistor（MP1）With the 4th transistor（MN4）Grid end；The second transistor
（MN2）, the 7th transistor（MP2）Source is connected, and connects the 8th transistor（MP3）, the 5th transistor（MN5）Drain terminal and the 6th brilliant
Body pipe（MP1）, the first transistor（MN1）Source, the second transistor（MN2）, the 7th transistor（MP2）Drain terminal is connected,
Connect phaselocked loop start-up circuit（201）Output end V1；5th transistor（MN5）Source ground connection；8th transistor
（MP3）Source termination power Vdd；6th transistor（MP1）, the first transistor（MN1）Drain terminal is connected, and connects third transistor
（MN3）Drain terminal and transmission gate（110）Input terminal；4th transistor（MN4）Drain terminal connect transmission gate（110）Output
End and third transistor（MN3）Source；4th transistor（MN4）And third transistor（MN3）Source is grounded.
2. phaselocked loop start-up circuit according to claim 1, it is characterised in that：It is described from counter（103）Including extremely
Few three d type flip flops, wherein input terminal CK, CN of first d type flip flop are respectively as from counter（103）Input terminal
CK, CN, output end Q, QN of the last one d type flip flop are respectively as from counter（103）Output end Q, QN, be located at centre
D type flip flop, input terminal CK, CN meet output end Q, QN of previous d type flip flop.
3. phaselocked loop start-up circuit according to claim 1, it is characterised in that：The first transistor（MN1）, it is second brilliant
Body pipe（MN2）, third transistor（MN3）, the 4th transistor（MN4）, the 5th transistor（MN5）It is N-type transistor.
4. phaselocked loop start-up circuit according to claim 1, it is characterised in that：6th transistor（MP1）, it is the 7th brilliant
Body pipe（MP2）With the 8th transistor（MP3）It is P-type transistor.
5. phaselocked loop start-up circuit according to claim 1, it is characterised in that：First phase inverter（104）, it is second anti-
Phase device（105）, third phase inverter（106）, the 4th phase inverter（108）, the 5th phase inverter（109）For TTL not circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820823916.0U CN207869089U (en) | 2018-05-30 | 2018-05-30 | Phaselocked loop start-up circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820823916.0U CN207869089U (en) | 2018-05-30 | 2018-05-30 | Phaselocked loop start-up circuit |
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| Publication Number | Publication Date |
|---|---|
| CN207869089U true CN207869089U (en) | 2018-09-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820823916.0U Withdrawn - After Issue CN207869089U (en) | 2018-05-30 | 2018-05-30 | Phaselocked loop start-up circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108462489A (en) * | 2018-05-30 | 2018-08-28 | 南京胜跃新材料科技有限公司 | A kind of phaselocked loop start-up circuit |
-
2018
- 2018-05-30 CN CN201820823916.0U patent/CN207869089U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108462489A (en) * | 2018-05-30 | 2018-08-28 | 南京胜跃新材料科技有限公司 | A kind of phaselocked loop start-up circuit |
| CN108462489B (en) * | 2018-05-30 | 2023-09-29 | 山东泉景胜跃信息技术有限公司 | Phase-locked loop starting circuit |
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Granted publication date: 20180914 Effective date of abandoning: 20230929 |
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| AV01 | Patent right actively abandoned |