CN207852638U - The encapsulating structure of semiconductor chip - Google Patents
The encapsulating structure of semiconductor chip Download PDFInfo
- Publication number
- CN207852638U CN207852638U CN201721904125.2U CN201721904125U CN207852638U CN 207852638 U CN207852638 U CN 207852638U CN 201721904125 U CN201721904125 U CN 201721904125U CN 207852638 U CN207852638 U CN 207852638U
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- encapsulating material
- material layer
- encapsulating
- plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The utility model provides a kind of encapsulating structure of semiconductor chip, and the encapsulating structure includes：There is the first opposite plane and the second plane, the electric deriving structure of the semiconductor chip to be revealed in first plane of the encapsulating material layer for semiconductor chip and the encapsulating material layer for being coated on the semiconductor chip, the encapsulating material layer.The utility model is bent by using by the surface design of support substrate in cambered surface, the warpage of the encapsulating material caused by the mismatch of the coefficient of thermal expansion as the support substrate Yu the encapsulating material can be effectively reduced, encapsulating material layer surfacing after separation is without warpage, it can be conducive to the progress of subsequent technique, the making of such as re-wiring layer and the making of metal coupling improve the stability and yield of packaging technology.The utility model is compatible with existing packaging technology, does not need additional adjusting process step or increases process apparatus, can effectively reduce process costs.
Description
Technical field
The utility model belongs to field of semiconductor package, the encapsulating structure more particularly to a kind of semiconductor chip and encapsulation
Method.
Background technology
As the function of integrated circuit is increasingly stronger, performance and integrated level is higher and higher and novel integrated circuit goes out
Existing, encapsulation technology plays an increasingly important role in IC products, shared in the value of entire electronic system
Ratio it is increasing.Meanwhile as integrated circuit feature size reaches nanoscale, transistor to more high density, it is higher when
Clock frequency develops, and encapsulation also develops to more highdensity direction.
Since fan-out wafer grade encapsulation (fowlp) technology is due to having many advantages, such as miniaturization, low cost and high integration, with
And there is better performance and higher energy efficiency, fan-out wafer grade encapsulation (fowlp) technology have become the movement of high request/
The important packaging method of the electronic equipments such as wireless network is current one of encapsulation technology most with prospects.
In existing fan-out wafer grade encapsulation process, not due to the coefficient of thermal expansion between encapsulating material and carrier material
Match, frequently can lead to the generation of the warping phenomenon of encapsulation chip, it is existing when the warpage for encapsulating chip is excessive (warpage ＞ 3.5mm)
Some process equipments are just difficult to the encapsulation chip to the warpage and are effectively repaired, and are substantially reduced so as to cause production yield.
Existing several solution compound chip warpage issues methods include；1) the carrier material of suitable coefficient of thermal expansion is selected
Material and encapsulating material, however, it is necessary to select the carrier material and encapsulating material of matched coefficients of thermal expansion, and can meet encapsulation
The material that can be required is very difficult；2) encapsulation chip is subjected to adhesion process with carrier material in technical process, and all
After production process is completed, then chip will be encapsulated and carry out unsticking processing with carrier material, still, this technique needs to change work
Skill flow can greatly increase the cost of process equipment.
Based on the above, a kind of encapsulation chip warpage and lower-cost semiconductor chip of can effectivelying prevent is provided
Encapsulating structure and packaging method are necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of envelopes of semiconductor chip
Assembling structure and packaging method, for solving the problems, such as that encapsulation chip is easy warpage in the prior art or cost is higher.
In order to achieve the above objects and other related objects, the utility model provides a kind of packaging method of semiconductor chip,
Including step：1) support substrate is provided, the support substrate has the first face and second face opposite with first face, in
First face of the support substrate substrate forms separating layer；2) semiconductor chip is provided, the semiconductor chip is adhered to
In in the separating layer, wherein the semiconductor chip has the one of electric deriving structure facing towards the separating layer；3) using envelope
Package material is packaged the semiconductor chip；And 4) it is based on encapsulating material and the support described in the separation layer separation
Substrate so that there is the semiconductor chip one side of electric deriving structure to be in same flat with the lower surface of the encapsulating material
Face；Wherein, the first face of the support substrate is bent in cambered surface, to reduce the heat by the support substrate and the encapsulating material
The warpage of the encapsulating material caused by the mismatch of the coefficient of expansion.
Preferably, the coefficient of thermal expansion of the support substrate is more than the coefficient of thermal expansion of the encapsulating material, the support
The cambered surface that first face of substrate is bent in relative level recess.
Preferably, the coefficient of thermal expansion of the support substrate is less than the coefficient of thermal expansion of the encapsulating material, the support
First face of substrate is in the cambered surface of relative level convex curved.
Preferably, the support substrate includes glass substrate, metal substrate, semiconductor substrate, polymer substrate and ceramics
One kind in substrate.
Preferably, the separating layer includes one kind in adhesive tape and polymeric layer, and the polymeric layer uses spin coating first
Technique is coated on the support substrate surface, then ultra-violet curing or heat curing process is used to make its curing molding.
Preferably, using the method that encapsulating material encapsulates the semiconductor chip include compression forming, Transfer molding,
One kind in fluid-tight molding, vacuum lamination and spin coating.
Preferably, the encapsulating material includes one kind in polyimides, silica gel and epoxy resin.
The utility model also provides a kind of encapsulating structure of semiconductor chip, and the encapsulating structure includes：Semiconductor chip
And it is coated on the encapsulating material layer of the semiconductor chip, the encapsulating material layer is flat with the first opposite plane and second
The electric deriving structure in face, the semiconductor chip is revealed in first plane of the encapsulating material layer.
Preferably, first plane with second plane of the encapsulating material layer are in generally parallel.
Preferably, the encapsulating material layer includes one kind in polyimide layer, layer of silica gel and epoxy resin layer.
As described above, the encapsulating structure and packaging method of the semiconductor chip of the utility model, have the advantages that：
The utility model is bent by using by the surface design of support substrate in cambered surface, can be effectively reduced by the branch
The warpage of the encapsulating material caused by the mismatch of the coefficient of thermal expansion of support group bottom and the encapsulating material, can be with after separation
Obtain encapsulating material layer of the surfacing without warpage, in favor of the progress of subsequent technique, the making such as re-wiring layer and metal
The making etc. of convex block improves the stability and yield of packaging technology.
The utility model is compatible with existing packaging technology, does not need additional adjusting process step or increases process apparatus,
Process costs can be effectively reduced, are with a wide range of applications in field of semiconductor package.
Description of the drawings
Fig. 1 a~Fig. 5 is shown as the structural representation that each step of packaging method of the semiconductor chip of the utility model is presented
Figure, wherein Fig. 5 is shown as the structural schematic diagram of the encapsulating structure of the semiconductor chip of the utility model.
Component label instructions
101 support substrates
Second face of 102 support substrates
The cambered surface of 103 recess bendings
The cambered surface of 104 convex curveds
105 separating layers
106 semiconductor chips
107 encapsulating material layers
108 first planes
109 second planes
Specific implementation mode
Illustrate that the embodiment of the utility model, those skilled in the art can be by this theorys below by way of specific specific example
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific implementation modes are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1 a~Fig. 5.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, when only display is with related component in the utility model rather than according to actual implementation in illustrating then
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change
Become, and its assembly layout kenel may also be increasingly complex.
As shown in Fig. 1 a~Fig. 5, the present embodiment provides a kind of packaging methods of semiconductor chip 106, including step：
As shown in Fig. 1 a, Fig. 1 b and Fig. 2, step 1) is carried out first, a support substrate 101, the support substrate 101 are provided
With the first face and second face 102 opposite with first face, formed in first face of 101 substrate of the support substrate
Separating layer 105.
First face of the support substrate 101 is bent in cambered surface.
Specifically, when the coefficient of thermal expansion of the support substrate 101 is more than the thermal expansion system of subsequent encapsulating material layer 107
When number, the first face of the support substrate 101 is in the cambered surface 103 of relative level recess bending, as shown in Figure 1a.
When the support substrate 101 coefficient of thermal expansion be less than subsequent encapsulating material layer 107 coefficient of thermal expansion, it is described
First face of support substrate 101 is in the cambered surface 104 of relative level convex curved, as shown in Figure 1 b.
As an example, the crooked radian of the support substrate 101 and the support substrate 101 and encapsulating material layer 107
The difference of coefficient of thermal expansion is positively correlated relationship.For example, the coefficient of thermal expansion of the support substrate 101 and encapsulating material layer 107 it
Difference is bigger, and the crooked radian of the support substrate 101 is bigger.
The support substrate includes in glass substrate, metal substrate, semiconductor substrate, polymer substrate and ceramic substrate
It is a kind of.In the present embodiment, it is glass substrate that the support substrate, which is selected, and the glass substrate cost is relatively low, is easy in its table
Face forms separating layer 105, and can reduce the difficulty of subsequent stripping technology.
As an example, the separating layer 105 includes one kind in adhesive tape and polymeric layer, the polymeric layer uses first
Spin coating proceeding is coated on the support substrate surface, then ultra-violet curing or heat curing process is used to make its curing molding.
In the present embodiment, it is heat-curable glue that the separating layer 105, which is selected, and being formed in the support by spin coating proceeding serves as a contrast
After on bottom, its curing molding is made by heat curing process.Heat-curable glue performance is stablized, and surface is more smooth, is conducive to subsequent heavy
The making of new route layer, also, in subsequent stripping technology, the difficulty of stripping is relatively low, and complete and property can be obtained after stripping
It can good re-wiring layer.
As shown in figure 3, then carrying out step 2), semiconductor chip 106 is provided, the semiconductor chip 106 is adhered to
In the separating layer 105, wherein the semiconductor chip 106 has the one of electric deriving structure facing towards the separating layer 105.
As an example, the semiconductor chip 106 can be one or more, and the function that can be realized according to needs
And it is arbitrarily combined.
As shown in figure 4, then carrying out step 3), the semiconductor chip 106 is sealed using encapsulating material layer 107
Dress.
As an example, including compression forming using the method that encapsulating material layer 107 encapsulates the semiconductor chip 106, passing
Pass one kind in molded, fluid-tight molding, vacuum lamination and spin coating.
As an example, the encapsulating material layer 107 includes one kind in polyimides, silica gel and epoxy resin.It is described
Encapsulating material layer 107 is selected according to the cambered surface design of above-mentioned support substrate 101.
As shown in figure 5, finally carry out step, 4) based on the separating layer 105 detach the encapsulating material layer 107 with it is described
Support substrate so that the semiconductor chip 106 has the lower surface of the one side and the encapsulating material layer 107 of electric deriving structure
In same plane；Wherein, the first face of the support substrate 101 in cambered surface be bent, with reduce by the support substrate 101 with
The warpage of the encapsulating material layer 107 caused by the mismatch of the coefficient of thermal expansion of the encapsulating material layer 107.
As an example, the selection of the cambered surface design and encapsulating material layer 107 by the support substrate 101, can make
First plane 108 of the encapsulating material layer 107 and second plane 109 are in generally parallel, in favor of follow-up cloth again
The making of the making of line layer and metal coupling etc..
As shown in figure 5, the present embodiment also provides a kind of encapsulating structure of semiconductor chip 106, the encapsulating structure includes：
Semiconductor chip 106 and the encapsulating material layer 107 for being coated on the semiconductor chip 106, the encapsulating material layer 107 have
Opposite the first plane 108 and the second plane 109, the electric deriving structure of the semiconductor chip 106 are revealed in the package material
First plane 108 of the bed of material 107.
As an example, the encapsulating material layer 107 is substantially without warpage, for example, described can be expressed as sticking up without warpage substantially
Song is not more than 0.5mm, alternatively, further, it is described to be expressed as warpage no more than 0.2mm without warpage substantially.Described
One plane 108 and second plane 109 are in generally parallel, and described is in generally parallel comprising essence is parallel or first plane
There are the angles that one is not more than 3 ° between 108 and second plane 109, for example, first plane 108 and described second
There are 1 ° of angles for plane 109, or there are 2 ° angles etc., also belong to described be in generally parallel range.
As an example, the encapsulating material layer 107 includes one in polyimide layer, layer of silica gel and epoxy resin layer
Kind.
As an example, first plane 108 of the encapsulating material layer 107, which also makes, re-wiring layer, described half
Conductor chip 106 realizes electrically interconnection by the re-wiring layer.
As an example, being also formed with metal coupling and the bottom between the metal coupling on the re-wiring layer
Filled layer, the Underfill layer is to protect the metal coupling, and the metal coupling is realizing the re-wiring layer
Extraction.
As described above, the encapsulating structure and packaging method of the semiconductor chip 106 of the utility model, have below beneficial to effect
Fruit：
The utility model is bent by using by the surface design of support substrate 101 in cambered surface, can be effectively reduced by institute
State support substrate 101 and the encapsulating material layer 107 caused by the mismatch of the coefficient of thermal expansion of the encapsulating material layer 107
Warpage, encapsulating material layer 107 of the surfacing without warpage can be obtained after separation, in favor of the progress of subsequent technique, such as weight
The making of new route layer and the making of metal coupling etc. improve the stability and yield of packaging technology.
The utility model is compatible with existing packaging technology, does not need additional adjusting process step or increases process apparatus,
Process costs can be effectively reduced, are with a wide range of applications in field of semiconductor package.
So the utility model effectively overcomes various shortcoming in the prior art and has high industrial utilization.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications completed under refreshing and technological thought or change, should be covered by the claim of the utility model.
Claims (5)
1. a kind of encapsulating structure of semiconductor chip, which is characterized in that the encapsulating structure includes semiconductor chip and cladding
In the encapsulating material layer of the semiconductor chip, the encapsulating material layer has the first opposite plane and the second plane, described
The electric deriving structure of semiconductor chip is revealed in first plane of the encapsulating material layer.
2. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The encapsulating material layer it is described
First plane is in generally parallel with second plane.
3. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The encapsulating material layer includes poly-
Imide layer.
4. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The encapsulating material layer includes silicon
Glue-line.
5. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The encapsulating material layer includes ring
Oxygen resin layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721904125.2U CN207852638U (en) | 2017-12-29 | 2017-12-29 | The encapsulating structure of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721904125.2U CN207852638U (en) | 2017-12-29 | 2017-12-29 | The encapsulating structure of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207852638U true CN207852638U (en) | 2018-09-11 |
Family
ID=63420103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721904125.2U Active CN207852638U (en) | 2017-12-29 | 2017-12-29 | The encapsulating structure of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207852638U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010877A (en) * | 2017-12-29 | 2018-05-08 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and method for packing of semiconductor chip |
-
2017
- 2017-12-29 CN CN201721904125.2U patent/CN207852638U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010877A (en) * | 2017-12-29 | 2018-05-08 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and method for packing of semiconductor chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105514087A (en) | Double-faced fan-out type wafer-level packaging method and packaging structure | |
| WO2017124671A1 (en) | Packaging method packaging structure for fan-out chip | |
| CN108305856A (en) | The encapsulating structure and packaging method of antenna | |
| CN108417982A (en) | The encapsulating structure and packaging method of antenna | |
| CN107301983A (en) | Fan-out package structure and preparation method thereof | |
| CN107248509A (en) | The chip-packaging structure and method for packing of EMI protection | |
| CN107634076A (en) | Cmos image sensor fan-out package structure and preparation method thereof | |
| CN108336494A (en) | The encapsulating structure and packaging method of antenna | |
| CN107910311A (en) | A kind of fan-out-type antenna packages structure and preparation method thereof | |
| CN107195551A (en) | Fan-out-type laminated packaging structure and preparation method thereof | |
| CN103681458A (en) | Method for manufacturing three-dimensional flexible stacked encapsulating structure of embedded ultrathin chip | |
| CN207852638U (en) | The encapsulating structure of semiconductor chip | |
| CN208738235U (en) | Fan-out-type antenna packages structure | |
| CN107146778A (en) | The encapsulating structure and method for packing of fingerprint recognition chip | |
| CN108010877A (en) | The encapsulating structure and method for packing of semiconductor chip | |
| CN107123604A (en) | A kind of method for packing of double-faced forming | |
| CN207938809U (en) | The encapsulating structure of antenna | |
| CN207503965U (en) | A kind of fan-out-type antenna packages structure | |
| CN107481992A (en) | The encapsulating structure and method for packing of fingerprint recognition chip | |
| CN207503967U (en) | The encapsulating structure of fingerprint recognition chip | |
| CN208806245U (en) | Fan-out-type antenna packages structure | |
| CN207165562U (en) | The chip-packaging structure of EMI protection | |
| CN206931602U (en) | The two-sided system-level laminated packaging structure of plastic packaging fan-out-type | |
| CN107644845A (en) | The encapsulating structure and method for packing of fingerprint recognition chip | |
| US11756942B2 (en) | Fan-out packaging structure and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |