CN207801904U - A kind of PLL phase-locked loop systems - Google Patents
A kind of PLL phase-locked loop systems Download PDFInfo
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- CN207801904U CN207801904U CN201720695754.2U CN201720695754U CN207801904U CN 207801904 U CN207801904 U CN 207801904U CN 201720695754 U CN201720695754 U CN 201720695754U CN 207801904 U CN207801904 U CN 207801904U
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Abstract
The utility model is related to a kind of PLL phase-locked loop systems, including PLL loop modules and the voltage-controlled local oscillator module for being associated with the PLL loop modules, further include prime amplification module, signal feedback module, final stage amplification module, central processing unit, calibration module, will with it is more stable, more accurately output signal to user terminal.
Description
Technical field
The utility model is related to PHASE-LOCKED LOOP PLL TECHNIQUE fields, and in particular to a kind of PLL phase-locked loop systems.
Background technology
Phaselocked loop (phase locked loop) is exactly as its name suggests the loop of locking phase.It learned and automatically controls original
The people of reason both knows about, this is a kind of typical feedback control circuit, using shaking inside externally input reference signal control loop
The frequency and phase of signal are swung, realizes that output signal frequency, from motion tracking, is generally used for Closed loop track to frequency input signal
Circuit.It is a kind of method for keeping frequency relatively stable in radio transmitting, mainly there is VCXO（Voltage controlled oscillator）With PLL IC
（Phase-locked loop intergrated circuit）, voltage controlled oscillator provides a signal, a part of that output, another part is used as to pass through frequency dividing and PLL
Local oscillation signal caused by IC makees phase bit comparison, in order to which keep frequency is constant, it is desirable to which phase difference does not change, if there is phase
The variation of potential difference, then the voltage of the voltage output end of PLL IC change, go control VCXO, until phase difference restore, reach
The purpose of locking phase.It can make the close loop electronic circuit of the frequency and phase of controlled oscillator with the determining relationship of input signal holding.
In actual PLL circuit environment, we can also ignore the parameter of other key, that is, in entire PLL circuit
The amplitude of signal influences and the accuracy of final pole voltage controlled oscillator VCXO output frequencies.Domestic relevant reported literature at present
In there is no detailed research is unfolded with regard to this technology, cause the phenomenon of most of PLL phase-locked loop operations stability differences.
The above problem has to be solved.
Utility model content
The technical problems to be solved in the utility model is：It proposes a kind of to reduce PLL frequency displacements simultaneously using signal feedback control loop
By with PLL phase-locked loop systems that are more stable, more accurately outputing signal to user terminal,
The technical solution that the utility model proposes to solve above-mentioned technical problem is：A kind of PLL phase-locked loop systems, including
PLL loop modules and the voltage-controlled local oscillator module for being associated with the PLL loop modules further include prime amplification module, signal feedback
Module, final stage amplification module, central processing unit, calibration module；
The frequency signal output end of the PLL loop modules is connected respectively to the signal after the prime amplification module
The signal input part of the signal input part and final stage amplification module of feedback module；
The information of the central processing unit reads the information providing end that end is connected to the signal feedback module, the center
The control terminal of processor is connected to the controlled end of the final stage amplification module；
The voltage-controlled voltage output end of the final stage amplification module is connected to the signal input part of the voltage-controlled local oscillator；
The voltage-controlled local oscillation frequency signal output end is also connected to the calibration module, and the controlled end of the calibration module connects
It is connected to the control terminal of the central processing unit；
The signal output end of the calibration module is for being connected to user terminal.
Further, further include temperature control module, the voltage-controlled local oscillator module is set in the temperature control module, the temperature control mould
Block is suitable for the voltage-controlled local oscillator and provides isoperibol.
Further, the temperature control module be constant temperature wall by surrounding on four sides and close off at the top of the constant temperature wall and
The hexahedron structure that the constant temperature lid of bottom, constant temperature bottom are constituted, the voltage-controlled local oscillator are fixed on inside the temperature control module, the perseverance
It is all provided on the medial surface at warm bottom, constant temperature lid and constant temperature wall and is laid with shielding metal leve,
The constant temperature bottom is equipped with voltage-controlled local oscillator module fixing screws, and the constant temperature bottom is internally provided with warming resistance, institute
The both sides for stating constant temperature bottom are respectively provided with a photoinduction sensor for being served only for detection constant temperature bottom light leakage respectively,
The middle part of the constant temperature lid is equipped with an outlet hole only for threading, and enamel-cover electric induced line is introduced in outlet hole, described
Enamel-cover electric induced line is connected to the voltage-controlled local oscillator module, and the constant temperature is covered equipped with a heating resistance, and the two of the constant temperature lid
Side is also respectively provided with a photoinduction sensor for being served only for detection light intensity respectively；
The heating resistance is heated under the control of external temperature control circuit, the signal of the warming resistance export to
The temperature control circuit.
Further, the calibration module be by isolated amplifier, the first DDS module, the second DDS module, walk when count
Device, latch and filter module are constituted,
The signal output end of the isolated amplifier is separately connected the first DDS module and the second DDS module, and described second
The signal output end of DDS module be connected to it is described walk hour counter, it is described walk hour counter be coupled to the latch, the lock
Storage is also coupled to the central processing unit,
The signal output end of first DDS module is connected to the filter module, the signal output of the filter module
End is adapted to user terminal；
The central processing unit is further adapted for the control that the first DDS module is arranged with predeterminated frequency signal respectively and to second
DDS module is with the control of 1/100 frequency dividing setting.
Further, the final stage amplification module is suitable under the control of the central processing unit to amplifying through the prime
The frequency signal of module prime amplification carries out parameter reparation, and the synchronization phase demodulation carried out.
The beneficial effects of the utility model are embodied in：
It is applied to the voltage-controlled voltage such as following formula expression of VCXO,
VY+VX=VY+（V12-V11）* (Ry/Rx)=VY+KVPP（1）
Here VY is that the synchronization phase demodulation that traditional PLL phaselocked loops obtain is voltage-controlled；K is that preset signal feedback circuit feedback increases
Benefit；VPP is the peak-to-peak value of prime amplified signal.According to time-domain radio-frequency signal frequency and magnitude relation, same time domain frequency signal
In output system, become larger with the frequency of output signal, the peak-to-peak value of signal will become smaller.So when traditional PLL phase-locked loop circuits
The signal frequency of generation becomes hour, and the prime signal peak value of acquisition will become larger, by system in the utility model, the pressure of acquisition
Control voltage VY+KVPP will become larger（It is that VPP becomes larger in practice）, the signal frequency for making VCXO export is become larger after acting on VCXO
（Because that select in practice is the VCXO of just voltage-controlled slope）, thus play the role of compensation.
Description of the drawings
The PLL phase-locked loop systems of the utility model are described further below in conjunction with the accompanying drawings.
Fig. 1 is the structure diagram of PLL phase-locked loop systems in the utility model；
Fig. 2 is the circuit structure schematic diagram of signal feedback module；
Fig. 3 is the structure diagram of calibration module；
Fig. 4 is the structural schematic diagram of temperature control module；
Fig. 5 is the structural schematic diagram at constant temperature bottom；
Fig. 6 is the structural schematic diagram of constant temperature lid.
Specific implementation mode
According to Fig. 1, include PLL loop modules and be associated with the pressures of the PLL loop modules in the utility model
Local oscillator module is controlled, further includes prime amplification module, signal feedback module, final stage amplification module, central processing unit, calibration module.
Wherein, the frequency signal output end of the PLL loop modules is connected respectively to institute after the prime amplification module
State the signal input part of the signal input part and final stage amplification module of signal feedback module.
Wherein, the information of the central processing unit reads the information providing end that end is connected to the signal feedback module, institute
The control terminal for stating central processing unit is connected to the controlled end of the final stage amplification module.
The circuit structure of signal feedback module is and preceding as shown in Fig. 2, prime amplified signal transports to amplifier A1 and A3 respectively
Grade amplified signal is sent after A3 to A2.A4 and A5 is voltage follower, output end V11 and V12 voltage magnitude and capacitance C1 and
Voltage on C2 is identical（It is to provide electric current with this follower to support to add the effect that level-one follows）.V11 and V12 send respectively to
The reverse side and in-phase end of A6 completes N（V12-V11）Operation.
Wherein A1 and A4 completes the detection of prime amplified signal peak-peak：When prime amplified signal voltage is more than capacitance C1
When voltage, pressure drop is generated on resistance Rf, electric current is from left to right.It is not turned on according to the disconnected rule D11 of the void of amplifier.At this moment charging electricity
Stream carries out C1 by D12.When the voltage of prime amplified signal is less than capacitance C1 voltages, pressure drop, electric current are generated on resistance R2
From right to left.It is not turned on according to the disconnected rule D12 of the void of amplifier, at this moment electric current only enters A1 by D11.Due to voltage follow
Device A4 output voltages are identical as the voltage on capacitance C1, and diode D11 cut-offs, capacitance cannot lead D11 electric discharges, and voltage is protected
Shield, i.e. capacitance C1 and A4 outputs V11 have recorded the peak-peak of prime amplified signal.There are one discharge resistance R1, RC by capacitance C1
Discharge time constant τ set according to the period of actual prime amplified signal, such as the frequency of prime amplified signal is
79Hz, then τ take 1S.V11 is delivered to the corresponding voltage value of 1 acquisition of A/D samplings and is transferred to central processing unit simultaneously.
A3 completes prime amplified signal reverse phase：Amplifier A3 first carries out reverse phase to the prime amplified signal of its input, then is superimposed
One negative amplitude DC level Vref, is finally completed the conversion of the high and low level of prime amplified signal, obtains signal and exports to amplifier
A2。
A2 and A5 completes the detection of prime amplified signal minimum peak：Prime amplified signal after A3 is handled, and send to
The in-phase end of amplifier A2.Wherein A2 and A5 principles as described in above-mentioned A1 and A3, only this moment due to prime amplified signal
Through passing through amplifier A3 processing, what A2 and A5 were completed is the detection of prime amplified signal minimum value.V12 is delivered to A/D samplings 2 simultaneously
It obtains corresponding voltage value and is transferred to central processing unit.
A6 completes the detection of peak-to-peak value：Distinguish through aforementioned treated prime amplified signal high level V11 and low level V12
It is sent into difference amplifier A6, by adjusting the ratio of Ry and Rx, output（V12-V11）*(Ry/Rx).It is delivered to A/D samplings simultaneously
3, which obtain corresponding voltage value, is transferred to central processing unit.
The frequency letter that the voltage value that 1,2,3 obtain may determine that the output of prime amplified signal module is sampled by above-mentioned A/D
Number amplitude Characteristics, these signals are fed back to by central processing unit in final stage amplified signal module, and synchronous phase demodulation is completed.
Here there are one critically important technologies：Substantially in accordance with main schematic diagram, we are only by above-mentioned acquisition（V12-V11）*(Ry/Rx)
Information handle becoming correcting is delivered to VCXO, Wo Menji with voltage-controlled voltage VX and the voltage-controlled voltage VY summations of conventional synchronization phase demodulation
（V12-V11）=VPP、(Ry/Rx)=K.Here K be a gain amplifier it typically rely on amplifier A6 in signal feedback module
Feedback oscillator Ry and Rx ratio, KVPP directly determines the voltage-controlled voltage swing of amendment for adding to VCXO, so VX is necessary
It is configured with voltage-controlled voltage VY magnitudes according to the voltage-controlled slope of specific VCXO and conventional synchronization phase demodulation, we generally take VX=VY/
20 to VX=VY/10 magnitudes.
Wherein, the voltage-controlled voltage output end of the final stage amplification module is connected to the signal input part of the voltage-controlled local oscillator.
It can be used as preferably：The final stage amplification module is suitable under the control of the central processing unit to amplifying through the prime
The frequency signal of module prime amplification carries out parameter reparation, and the synchronization phase demodulation carried out.
Wherein, the voltage-controlled local oscillation frequency signal output end is also connected to the calibration module, the calibration module by
Control end is connected to the control terminal of the central processing unit.
Wherein, the signal output end of the calibration module is for being connected to user terminal.
It can be used as preferably：As shown in figure 3, the calibration module can be by isolated amplifier, the first DDS module,
Two DDS modules walk hour counter, latch and filter module composition.The signal output end of the isolated amplifier is separately connected
First DDS module and the second DDS module, the signal output end of second DDS module be connected to it is described walk hour counter, it is described
It walks hour counter and is coupled to the latch, the latch is also coupled to the central processing unit.First DDS module
Signal output end is connected to the filter module, and the signal output end of the filter module is adapted to user terminal.The center
Processor is further adapted for the control that the first DDS module is arranged with predeterminated frequency signal respectively and to the second DDS module with 1/100 point
The control of frequency setting.
When VCXO frequencies are up to a hundred million or even hundreds of megahertzs, it is contemplated that limitation of the hour counter to VCXO ranges is walked,
Design in the present invention wherein all the way DDS2 modules to VCXO signals carry out 1/100 scaling down processing.VCXO is after isolated amplifier
It is sent directly into the external clock input terminal of DDS2, reference clock when working as DDS2.
The DDS chip interiors actually selected have 2 48 bit frequency control registers（F0、F1）, the present apparatus is not used
Inside DDS when PLL double frequency functions, when 48 frequency control register F0 full packings 1, DDS has VCXO, and to expire frequency signal defeated
Go out, therefore exported to user terminal for the frequency signal for obtaining standard, is needed corresponding to frequency control register F0 settings in DDS
Numerical value is divided, the method specifically calculated is：
（2）
Wherein, D is the specific frequency dividing numerical value of required calculating, and f0 is VCXO output signal frequencies.The external communication end of DDS
Mouth is connected to central processing unit, and central processing unit is according to formula（2）Obtained 248 × 10-2 frequency dividing numerical value passes through serial communication sequential
Be written DDS2 buffer areas, after the 1/100 crossover rate signal that DDS2 is obtained, send to walk hour counter 1 carry out coarse frequency measurement, in
After central processor reads numerical value of the latch 1 to walking the sampling of hour counter 1, frequency values at this time are recorded, after being multiplied by 100 just
The coarse frequency value F of VCXO can be obtained.
Another way is sent to the external clock input terminal of DDS1 by the VCXO of isolated amplifier, when working as DDS1
Reference clock.The external communication port of DDS1 is connected to central processing unit simultaneously, and central processing unit is according to formula（2）Be calculated with
The frequency dividing numerical value of DDS1 communications：, by walking, hour counter 1 counts wherein F, central processing unit operation obtains
The coarse frequency value of VCXO, f are the radio frequency signal frequency value of user terminal to be delivered to.And the tool as serial communication sequential by obtained by
Body divides numerical value and DDS1 buffer areas is written, and frequency signal is obtained after DDS1, the frequency signal of gained is sent again to low-pass filtering
Final frequency signal output is obtained after module.
It can be used as preferably：Further include temperature control module, the voltage-controlled local oscillator module is set in the temperature control module, institute
It states temperature control module and the voltage-controlled local oscillator offer isoperibol is provided.
It can be used as further preferably：As shown in Figure 4, Figure 5 and Figure 6, temperature control module is the constant temperature by surrounding on four sides
Wall 1 and the hexahedron structure constituted at the constant temperature lid 2 of the top of constant temperature wall 1 and bottom, constant temperature bottom 3 is closed off, voltage-controlled local oscillator is solid
It is scheduled on inside temperature control module, is all provided on the medial surface at constant temperature bottom 3, constant temperature lid 2 and constant temperature wall 1 and is laid with shielding metal leve.Constant temperature
Bottom 3 is equipped with voltage-controlled local oscillator fixing screws 4, and constant temperature bottom 3 is internally provided with warming resistance 5, and the both sides at constant temperature bottom 3 are respectively provided with respectively
One is served only for the photoinduction sensor 6 of light leakage at detection constant temperature bottom 3.The middle part of constant temperature lid 2 is equipped with an outlet hole only for threading,
Enamel-cover electric induced line 7 is introduced in outlet hole, enamel-cover electric induced line 7 is connected to voltage-controlled local oscillator, and constant temperature lid 2 is equipped with a heating resistance
8, the both sides of constant temperature lid 2 are also respectively provided with a photoinduction sensor 6 for being served only for detection light intensity respectively.Resistance 8 is heated in outside
It is heated under the control of temperature control circuit, the signal of warming resistance 5 is exported to temperature control circuit..
The utility model is not limited to the above embodiment, the technical solution of above-mentioned each embodiment of the utility model that
This can form new technical solution with combined crosswise, and in addition all technical solutions formed using equivalent replacement, all fall within this practicality
In the protection domain of novel requirement.
Claims (5)
1. a kind of PLL phase-locked loop systems, including PLL loop modules and the voltage-controlled local oscillator module for being associated with the PLL loop modules,
It is characterized in that：Further include prime amplification module, signal feedback module, final stage amplification module, central processing unit, calibration module；
The frequency signal output end of the PLL loop modules is connected respectively to the signal feedback after the prime amplification module
The signal input part of the signal input part and final stage amplification module of module；
The information of the central processing unit reads the information providing end that end is connected to the signal feedback module, the central processing
The control terminal of device is connected to the controlled end of the final stage amplification module；
The voltage-controlled voltage output end of the final stage amplification module is connected to the signal input part of the voltage-controlled local oscillator；
The voltage-controlled local oscillation frequency signal output end is also connected to the calibration module, and the controlled end of the calibration module is connected to
The control terminal of the central processing unit；
The signal output end of the calibration module is for being connected to user terminal.
2. PLL phase-locked loop systems according to claim 1, it is characterised in that：Further include temperature control module, the voltage-controlled local oscillator mould
Block is set in the temperature control module, and the temperature control module is suitable for the voltage-controlled local oscillator and provides isoperibol.
3. PLL phase-locked loop systems according to claim 2, it is characterised in that：The temperature control module is the perseverance by surrounding on four sides
It warm wall and closes off at the top of the constant temperature wall and hexahedron structure that the constant temperature lid of bottom, constant temperature bottom are constituted, it is described voltage-controlled
Local oscillator module is fixed on inside the temperature control module, is all provided with and is laid on the medial surface at the constant temperature bottom, constant temperature lid and constant temperature wall
Shielding metal leve,
The constant temperature bottom is equipped with voltage-controlled local oscillator module fixing screws, and the constant temperature bottom is internally provided with warming resistance, the perseverance
The both sides at warm bottom are respectively provided with a photoinduction sensor for being served only for detection constant temperature bottom light leakage respectively,
The middle part of the constant temperature lid is equipped with an outlet hole only for threading, and enamel-cover electric induced line, the enamel-cover are introduced in outlet hole
Electric induced line is connected to the voltage-controlled local oscillator module, and the constant temperature is covered equipped with a heating resistance, the both sides of the constant temperature lid
It is respectively provided with a photoinduction sensor for being served only for detection light intensity respectively；
The heating resistance is heated under the control of external temperature control circuit, and the signal of the warming resistance is exported to described
Temperature control circuit.
4. PLL phase-locked loop systems according to claim 3, it is characterised in that：The calibration module is by isolated amplifier,
One DDS module, the second DDS module walk hour counter, latch and filter module composition,
The signal output end of the isolated amplifier is separately connected the first DDS module and the second DDS module, the 2nd DDS moulds
The signal output end of block be connected to it is described walk hour counter, it is described walk hour counter be coupled to the latch, the latch
It is also coupled to the central processing unit,
The signal output end of first DDS module is connected to the filter module, and the signal output end of the filter module is suitable
In connection user terminal；
The central processing unit is further adapted for the control that the first DDS module is arranged with predeterminated frequency signal respectively and to the 2nd DDS
Module is with the control of 1/100 frequency dividing setting.
5. PLL phase-locked loop systems according to claim 4, it is characterised in that：The final stage amplification module is suitable in described
Parameter reparation is carried out to the frequency signal amplified through the prime amplification module prime under the control of central processor, and is carried out same
Walk phase demodulation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720695754.2U CN207801904U (en) | 2017-06-15 | 2017-06-15 | A kind of PLL phase-locked loop systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720695754.2U CN207801904U (en) | 2017-06-15 | 2017-06-15 | A kind of PLL phase-locked loop systems |
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| Publication Number | Publication Date |
|---|---|
| CN207801904U true CN207801904U (en) | 2018-08-31 |
Family
ID=63273482
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720695754.2U Expired - Fee Related CN207801904U (en) | 2017-06-15 | 2017-06-15 | A kind of PLL phase-locked loop systems |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207801904U (en) |
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2017
- 2017-06-15 CN CN201720695754.2U patent/CN207801904U/en not_active Expired - Fee Related
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