CN207717920U - A kind of wafer test system - Google Patents
A kind of wafer test system Download PDFInfo
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- CN207717920U CN207717920U CN201721898763.8U CN201721898763U CN207717920U CN 207717920 U CN207717920 U CN 207717920U CN 201721898763 U CN201721898763 U CN 201721898763U CN 207717920 U CN207717920 U CN 207717920U
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- test
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- group relay
- probe station
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Abstract
The utility model embodiment provides a kind of wafer test system, including：Master controller, test machine, probe station, TCH test channel control module；The main controller is connected with the test machine, the probe station respectively and the TCH test channel control module is connected, the main controller is microcontroller, the main controller is attached with the test machine by connecting interface respectively, it controls the test machine and receives the test result of the test machine, and test result is sent to the probe station；TCH test channel control module sends out relay drive signal by driver, and the closure that the drive signal by controlling relay carries out TCH test channel selects.Using the utility model, more devices can be tested simultaneously, improve the testing efficiency of device.
Description
Technical field
The utility model is related to device detection technical fields, and system is tested more particularly to a kind of wafer.
Background technology
Wafer (Wafer) refers to the silicon chip used in silicon semiconductor production of integrated circuits, since its shape is circle, therefore is claimed
For wafer.Wafer is to produce the carrier of used in integrated circuits, and general significance wafer refers to monocrystalline silicon wafer more.Monocrystalline silicon wafer is by general
Logical silica sand, which is drawn, to be refined, and silicon single crystal rod is made by dissolving, purification, distillation a series of measures, silicon single crystal rod is by polishing, slice
Later, just become wafer.
Discrete device class product is tested with JUNO discrete semiconductor testings system in P8 probe stations at present.Due to JUNO deviding devices
Part test system cannot support more while test that testing efficiency is low.
Therefore, it is necessary to provide a kind of new wafer test system solution above-mentioned technical problem.
Utility model content
The utility model embodiment is designed to provide a kind of wafer test system, and to solve in the prior art, device is not
Support more tests, the low problem of testing efficiency, it is intended to improve the testing efficiency of device.Specific technical solution is as follows：
In order to achieve the above objectives, the utility model embodiment provides a kind of wafer test system, master controller, test
Machine, probe station, TCH test channel control module；
The main controller is connected respectively with the test machine, the probe station and the TCH test channel control module phase
Even, the main controller is microcontroller, and the main controller is attached with the test machine by connecting interface respectively, described in control
Test machine and the test result for receiving the test machine, and test result is sent to the probe station；
TCH test channel control module sends out relay drive signal by driver, by the drive signal for controlling relay
Carry out the closure selection of TCH test channel.
In preferred embodiments of the present invention, the circuit of the TCH test channel control module includes：Switch W1, switch
W2, switch W3 and switch W4, connecting interface (P10), driver (U1), the first group relay, the second group relay, third group after
Electric appliance and the 4th group relay；
The microcontroller passes through the switch W1, switch W2, switch W3 and switch W4 and the connecting interface respectively
(P10) it is connected, the drive signal of relay is sent to by driver (U1) by the connecting interface (P10) and passes through described
The signal control of driver (U1) output first group relay, the second group relay, third group relay and the 4th group
The on and off of the corresponding TCH test channel of relay, wherein the driver (U1) is ULN2003.
In preferred embodiments of the present invention, first group relay, the second group relay, third group relay
Device and the 4th group relay respectively include four relays.
In preferred embodiments of the present invention, the main controller is by sending a signal to the probe station for controlling
The probe station is walked about, and test result is sent to the probe station after receiving the ready signal of probe station.
In preferred embodiments of the present invention, the model of the microcontroller：STC11F02C.
In preferred embodiments of the present invention, the crystal oscillation signal of the microcontroller is 12MHz.
Further include regulator circuit in preferred embodiments of the present invention, the regulator circuit passes through voltage stabilizing chip
(U2) 12V voltages are converted to 5V voltages, wherein the model of the voltage stabilizing chip (U2)：UZ1084.
Using the utility model embodiment provide a kind of wafer test system, main controller respectively with test machine, probe station
Be connected and TCH test channel control module be connected, main controller is microcontroller, main controller respectively with test machine by connecting interface into
Row connection controls test machine and receives the test result of test machine, and test result is sent to probe station；TCH test channel controls
Module sends out relay drive signal by driver, and the closure that the drive signal by controlling relay carries out TCH test channel is selected
It selects.Therefore, can be led to by the relay drive signal control test that driver in TCH test channel is sent out using the utility model
The closure in road is selected, and therefore, can be carried out at the same time closure with the multiple TCH test channels of simultaneous selection, thus may be implemented multiple logical
Road is carried out at the same time test, improves the testing efficiency of device.
Description of the drawings
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, other drawings may also be obtained based on these drawings.
Fig. 1 is the first circuit diagram of the wafer test platform of the utility model embodiment；
Fig. 2 is second of circuit diagram of the wafer test platform of the utility model embodiment；
Fig. 3 is the third circuit diagram of the wafer test platform of the utility model embodiment.
Specific implementation mode
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
The every other embodiment obtained, shall fall within the protection scope of the present invention.
Embodiment：
Shown in Fig. 1-2, main controller U3 is attached with test machine by connecting interface P8 respectively, specifically, master control
Device U3 is attached by TEST_SOT, TEST_EOT, BIN, VCC and connecting interface P8, main controller U3 by TEST_SOT,
TEST_EOT controls test machine, and receives test result.Main controller U3 controls probe station by prober_sot_stc2 and walks about,
Prober_eot_stc3 receives probe station and is ready to, bin1, bin2, and bin3, bin4 are that main controller U3 transmits test result (4
Parallel transmission) give probe station.
TCH test channel control module sends out relay drive signal by driver, by the drive signal for controlling relay
Carry out the closure selection of TCH test channel.In preferred embodiments of the present invention, the circuit of TCH test channel control module includes：
Switch W1, switch W2, switch W3 and switch W4 are connected with the 1-4 feet of connecting interface (P10) respectively, and test channel signal is sent out
It send to driver (U1), drive signal Drive1-Drive4 signals are respectively sent to the first group relay, by driver (U1)
Two group relays, third group relay and the 4th group relay.Illustratively, Drive1 signals connect 4 with 5V voltage signals
The connection type of relay, Drive2, Drive3, Drive4 is identical as Drive1.The signal control exported by driver (U1)
First group relay of system, the second group relay, third group relay and the corresponding TCH test channel of the 4th group relay logical and
It is disconnected, wherein driver (U1) is ULN2003.First group relay, the second group relay, third group relay and the 4th group after
Electric appliance respectively includes four relays.
In preferred embodiments of the present invention, the model of microcontroller：The crystal oscillation signal of STC11F02C, microcontroller
For 12MHz.
Further include regulator circuit in preferred embodiments of the present invention, regulator circuit will by voltage stabilizing chip (U2)
12V voltages are converted into 5V voltages, wherein the model of voltage stabilizing chip (U2)：UZ1084.As shown in figure 3, voltage stabilizing chip U2
Input terminal inputs 12V voltages, and is connected with the anode of electrolytic capacitor C1, the cathode ground connection of electrolytic capacitor C1；Voltage stabilizing chip U2's
Input terminal is connected with the anode of electrolytic capacitor C2 and is connected with one end of resistance R1, the other end and resistance of the resistance R1
The first end of R2 is connected, and the cathode of C2 is connected, the other end of the resistance R2 is grounded.The ports ADJ of voltage stabilizing chip U2 and resistance
R1 is connected with the connecting pin of resistance R2.
SITE1 is first test device, and SITE2 is second test device, and SITE3 is that third tests device,
SITE4 is that the 4th test device E1_S1-E1_S14, C1_S1-C1_S14, BI_S1-BI_S4, BV_S1-BV_S4 are respectively
The test results machine of corresponding pin is tested, and feeds back to microcontroller by corresponding test pin.
In the utility model, an interface circuit can be made of microcontroller, control sequential allows JUNO follow-on tests 4 times, then
P8 is allowed to walk about 1 time, to realize 4 serially tests.Test program is also not required to do special processing, with original program,
TCH test channel loop switch (RELAY switchings) has also been integrated in microcontroller control loop.
Detailed process can be：P8, JUNO are monitored after initialization surveys pattern in the ready string into 4,
In the case where testing completion, test result is transmitted by P8 to test machine, and sending signal makes test machine be moved to
Next 4 device under test, continue to change built-in testing after test, until test is completed.
In the utility model, notice JUNO starts to test after TCH test channel is switched to first, in microcontroller monitoring and test
Test result is received after the completion and is stored, and 4 ends of subroutine tested in the case where terminating for the 4th test, it is no
Then, it goes to TCH test channel and is switched to following four and carry out continuing to test.
The above is only the preferred embodiment of the utility model only, is not intended to limit the protection model of the utility model
It encloses.Any modification, equivalent substitution, improvement and etc. made within the spirit and principle of the present invention, are all contained in this reality
With in novel protection domain.
Claims (7)
1. a kind of wafer tests system, which is characterized in that main controller, test machine, probe station, TCH test channel control module；
The main controller is connected with the test machine, the probe station respectively and the TCH test channel control module is connected, institute
It is microcontroller to state main controller, and the main controller is attached with the test machine by connecting interface respectively, controls the test
Machine and the test result for receiving the test machine, and test result is sent to the probe station；
TCH test channel control module sends out relay drive signal by driver, and the drive signal by controlling relay carries out
The closure of TCH test channel selects.
2. wafer according to claim 1 tests system, which is characterized in that the circuit packet of the TCH test channel control module
It includes：Switch W1, switch W2, switch W3 and switch W4, connecting interface (P10), driver (U1), the first group relay, second group
Relay, third group relay and the 4th group relay；
The microcontroller passes through the switch W1, switch W2, switch W3 and switch W4 and the connecting interface (P10) phase respectively
Even, the drive signal of relay is sent to by driver (U1) by the connecting interface (P10) and by the driver
(U1) the first group relay, the second group relay, third group relay and the 4th group relay described in signal control exported
The on and off of corresponding TCH test channel, wherein the driver (U1) is ULN2003.
3. wafer according to claim 2 tests system, which is characterized in that first group relay, second group after
Electric appliance, third group relay and the 4th group relay respectively include four relays.
4. wafer according to claim 1 tests system, which is characterized in that the main controller is described by sending a signal to
Probe station is walked about for controlling the probe station, and test result is sent to the spy after receiving the ready signal of probe station
Needle platform.
5. testing system according to claim 1-4 any one of them wafers, which is characterized in that the model of the microcontroller：
STC11F02C。
6. wafer according to claim 5 tests system, which is characterized in that the crystal oscillation signal of the microcontroller is 12MHz.
7. wafer according to claim 1 tests system, which is characterized in that further include regulator circuit, the regulator circuit
It converts 12V voltages to 5V voltages by voltage stabilizing chip (U2), wherein the model of the voltage stabilizing chip (U2)：UZ1084.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721898763.8U CN207717920U (en) | 2017-12-29 | 2017-12-29 | A kind of wafer test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721898763.8U CN207717920U (en) | 2017-12-29 | 2017-12-29 | A kind of wafer test system |
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| Publication Number | Publication Date |
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| CN207717920U true CN207717920U (en) | 2018-08-10 |
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| CN201721898763.8U Active CN207717920U (en) | 2017-12-29 | 2017-12-29 | A kind of wafer test system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110286309A (en) * | 2019-07-19 | 2019-09-27 | 北京华峰测控技术股份有限公司 | Wafer parallel testing device, method and system |
-
2017
- 2017-12-29 CN CN201721898763.8U patent/CN207717920U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110286309A (en) * | 2019-07-19 | 2019-09-27 | 北京华峰测控技术股份有限公司 | Wafer parallel testing device, method and system |
| CN110286309B (en) * | 2019-07-19 | 2024-06-11 | 北京华峰测控技术股份有限公司 | Wafer parallel testing device, method and system |
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