CN207637790U - A kind of system integration intelligent power module - Google Patents
A kind of system integration intelligent power module Download PDFInfo
- Publication number
- CN207637790U CN207637790U CN201820419599.6U CN201820419599U CN207637790U CN 207637790 U CN207637790 U CN 207637790U CN 201820419599 U CN201820419599 U CN 201820419599U CN 207637790 U CN207637790 U CN 207637790U
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- Prior art keywords
- power module
- hvic
- lead frame
- chip
- hvic chips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The utility model is related to technical field of semiconductors, disclose a kind of system integration intelligent power module.In the utility model, intelligent power module includes MCU chip, HVIC chips and lead frame；HVIC chips include top layer metallic layer, and top layer metallic layer is equipped with chip bonding area, and MCU chip is arranged in chip bonding area；And MCU chip and HVIC chips are electrically connected to lead frame.In terms of existing technologies, chip bonding area is arranged, and MCU chip is set in chip bonding area in the utility model embodiment on the top layer metallic layer of HVIC chips.This mode for fitting together HVIC chips and MCU chip lamination, so that being directly integrated MCU in intelligent power module, has calculation processing power, to save the process of external processor, the application design for being conducive to simplified intelligent power module, promotes the usage experience of user.
Description
Technical field
The utility model is related to technical field of semiconductors, more particularly to a kind of system integration intelligent power module.
Background technology
As shown in Figure 1, existing IPM (Intelligent Power Module, intelligent power module) would generally integrate
HVIC (high pressure gate driving IC) chip 1, IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar
Transistor) 2, FRD (fast recovery diode) 3 etc..This IPM does not have computing module, can not independently carry out related operation.Make
Used time needs external processor, this mode that can increase the complexity using design, influence the experience of user.
Utility model content
The purpose of this utility model is to provide a kind of system integration intelligent power module, by MCU
(Microcontroller Unit, micro-control unit) is directly assembled on HVIC so that intelligent power module inherently has
Operational capability, to save the process of external processor, the application design of simplified intelligent power module.
In order to solve the above technical problems, the embodiment of the utility model provides a kind of system integration intelligent power mould
Block, including MCU chip, HVIC chips and lead frame；The HVIC chips include top layer metallic layer, on the top layer metallic layer
Equipped with chip bonding area, the MCU chip is arranged in the chip bonding area；And the MCU chip and the HVIC chips
It is electrically connected to the lead frame.
In terms of existing technologies, chip is arranged on the top layer metallic layer of HVIC chips in the utility model embodiment
Bonding region, and MCU chip is set in chip bonding area.It is this to fit together HVIC chips and MCU chip lamination
Mode so that be directly integrated MCU in intelligent power module, had calculation processing power, to save external processor
Process is conducive to the application design of simplified intelligent power module, promotes the usage experience of user.
In addition, the HVIC chips include several driving units and several groups power device, each driving unit
Power device described in being correspondingly connected with 2 groups；Power device described in every group includes a LIGBT and FRD, the LIGBT and the FRD phases
Connection.Existing IPM uses planar package technology, i.e., pastes the devices such as HVIC, IGBT and FRD for being integrated in IPM respectively
On lead frame or IMS substrates or DBC base plans, package dimension is larger.And by power device collection in the embodiment of the present application
It is assembled on HVIC chips to HVIC chip interiors, and MCU laminations, substantially reduces encapsulation volume.
In addition, the top layer metallic layer of the HVIC chips includes：The first metal layer, and the table to the first metal layer
Face carries out the second metal layer of turmeric processing formation；The chip bonding area is set in the second metal layer.To the first metal
The surface of layer carries out turmeric processing and forms second metal layer, on the one hand can enhance the solderability of HVIC chip top-layers, on the other hand
Also it can play the role of protection against oxidation.
In addition, the MCU chip includes several bonding welding pads, the part in several described bonding welding pads is by drawing
Line bonding is connected to the HVIC chips, and another part in several described bonding welding pads is connected to described by wire bonding
Lead frame；The HVIC chips are connected to the lead frame by wire bonding.MCU chip and HVIC chips are provided and drawn
A kind of specific implementation of wire frame electrical connection.
In addition, the MCU chip is connected to the lead frame by wire bonding, the HVIC chips pass through lead key
Conjunction is connected to the lead frame.Another specific implementation side that offer MCU chip and HVIC chips are electrically connected with lead frame
Formula.
In addition, the MCU chip is connected to the HVIC chips by wire bonding, the HVIC chips pass through lead key
Conjunction is connected to the lead frame.Another specific implementation side that offer MCU chip and HVIC chips are electrically connected with lead frame
Formula.
In addition, the MCU chip is pasted on the chip bonding area.MCU chip and chip bonding area fixed one are provided
Kind concrete mode.
In addition, the HVIC chips are pasted on the lead frame.HVIC chips and the fixed one kind of lead frame are provided
Concrete mode.
In addition, the HVIC chips are pasted on the lead frame by elargol or tin-lead solder.
In addition, the chip bonding area is located at the intermediate region of the top layer metallic layer.Chip bonding area is provided in top layer
The specific location of metal layer.
Description of the drawings
Fig. 1 is the electrical block diagram of intelligent power module according to prior art；
Fig. 2 is the structural schematic diagram according to the HVIC chips of the utility model first embodiment；
Fig. 3 is the vertical view being arranged according to the MCU chip of the utility model first embodiment on HVIC chips；
Fig. 4 is the sectional view being arranged according to the MCU chip of the utility model first embodiment on HVIC chips；
Fig. 5 is the mounting structure schematic diagram of HVIC chips, IGBT, FRD according to prior art；
Fig. 6 is the structural schematic diagram according to the intelligent power module of the utility model second embodiment.
Specific implementation mode
It is new to this practicality below in conjunction with attached drawing to keep the purpose of this utility model, technical solution and advantage clearer
Each embodiment of type is explained in detail.However, it will be understood by those skilled in the art that each in the utility model
In embodiment, in order to make the reader understand this application better, many technical details are proposed.But even if without these skills
Art details and various changes and modifications based on the following respective embodiments can also realize that each claim of the application is required and protect
The technical solution of shield.
The first embodiment of the utility model is related to a kind of system integration intelligent power module.The intelligent power module packet
Include HVIC chips 1, MCU chip 4 and lead frame 5；Wherein, 4 lamination of MCU chip is assembled on HVIC chips 1, and MCU chip 4
And HVIC chips 1 are electrically connected to lead frame 5.
Specifically, as shown in Fig. 2, HVIC chips 1 include the first substrate 11, the insulating layer 12 on the first substrate 11
(mainly being formed by silicon materials), the second substrate 13 on insulating layer 12, the device layer 14 on the second substrate 13.Device
Layer 14 includes top layer metallic layer 15, which is located at the top of device layer 14.The top layer metallic layer 15 includes the
One metal layer 151 and the second metal layer 152 that turmeric processing formation is carried out to the surface of the first metal layer, second metal layer
152 are located on the first metal layer 151.
As shown in Figure 3, Figure 4, chip bonding area 16 is arranged in present embodiment in second metal layer 152, and MCU chip 4 is set
It sets in chip bonding area 16.MCU chip 4 can be pasted onto in chip bonding area 16 by elargol, so without being limited thereto, actually answered
In, also it can select other manner that MCU chip 4 is fixed in chip bonding area 16 according to actual conditions.HVIC chips 1 can lead to
It crosses elargol or tin-lead solder is pasted on lead frame 5.In addition, HVIC chips 1 and MCU chip 4 are electrically connected to lead frame
5, to form integrated circuit structure.
It in practical applications, can be by way of wire bonding, by HVIC chips 1 and MCU chip 4 and 5 electricity of lead frame
Connection.Specifically, a part of bonding welding pad in MCU chip 4 can be connect with HVIC chips 1 by the leads such as gold, copper, aluminium 6,
Another part bonding welding pad in MCU chip 4 is connect with lead frame 5 by lead 6 again, and by lead 6 by HVIC cores
Bonding welding pad on piece 1 is directly connect with lead frame 5.It is so without being limited thereto, it also can directly will be in MCU chip 4 by lead 6
All bonding welding pads are connect with lead frame 5, and the bonding welding pad on HVIC chips 1 is directly connect with lead frame 5, i.e., directly
It connects and MCU chip 4, HVIC chips 1 is connected to lead frame 5.Alternatively, also can by lead 6 will be in MCU chip 4 it is all
Bonding welding pad is connect with HVIC chips 1, and the bonding welding pad on HVIC chips 1 is directly connect with lead frame 5, i.e., by MCU
Chip 4 is connected to lead frame 5 by HVIC chips 1.
In addition, in actual design, the intermediate region of top-level metallic, the i.e. intermediate region of second metal layer 152 can be set
Chip bonding area 16 is set, to be more reasonably laid out related device and cabling.
Present embodiment in terms of existing technologies, the design chips bonding region in the top layer metallic layer of HVIC chips,
And MCU chip is set to the chip bonding area.This design for fitting together HVIC chips and MCU chip lamination, makes
It obtains in intelligent power module and has been directly integrated MCU, have calculation processing power, to save the process of external processor, have
Conducive to the application design of simplified intelligent power module, the usage experience of user is promoted.In addition, present embodiment uses HVIC turmerics
Technique forms the metal layer of good weldability in the top layer of HVIC chips, and plays the role of protection against oxidation.Meanwhile this implementation
Mode is adhered to MCU on the top layer metallic layer of HVIC chips, and pass through lead on HVIC die bondings to lead frame
Bonding, is electrically connected MCU with HVIC with lead frame, forms integrated circuit structure.When packaged, epoxy-plastic packaging or gold can be passed through
Belong to encapsulation, ceramic package mode, system is packaged, forms internal protection.
The second embodiment of the utility model is related to a kind of system integration intelligent power module.Second embodiment is
It is further improved on the basis of one embodiment, mainly thes improvement is that：In present embodiment, using SOI (insulators
Upper silicon materials) technology, LIGBT (lateral type insulated gate bipolar transistor), FRD are integrated into HVIC chip interiors.
It is noted that as shown in figure 5, in the prior art, IPM is frequently with planar package technology, i.e., by HVIC cores
The devices such as piece, IGBT and FRD are all respectively adhered on lead frame or IMS substrates (insulating metal substrate) or DBC substrates (ceramics
Insulating substrate) in plane, HVIC chip surfaces do not paste any chip or device.This mode make whole package dimension compared with
Greatly, and bonding line is longer.
And present embodiment, it uses SOI and carries out HVIC flows, LIGBT, FRD integrated design in HVIC chip interiors.
Specifically, as shown in fig. 6, in present embodiment, IPM includes HVIC chips 1 and MCU chip 4.If the HVIC chips 1 include
Dry driving unit 7 and several groups power device 8.Each driving unit 7 is correspondingly connected with two groups of power devices 8, every group of power device
Part 8 includes a LIGBT and FRD.The LIGBT and FRD links together.
In present embodiment, using SOI technology, LIGBT, FRD are integrated into inside HVIC, MCU laminations are assembled into
HVIC chips top substantially reduces the overall package volume of IPM.The IPM collection provided compared to existing IPM, present embodiment
At degree higher, enormously simplify using design.
It will be understood by those skilled in the art that the respective embodiments described above are to realize the specific implementation of the utility model
Example, and in practical applications, can to it, various changes can be made in the form and details, without departing from the spirit of the utility model
And range.
Claims (10)
1. a kind of system integration intelligent power module, which is characterized in that including MCU chip, HVIC chips and lead frame；
The HVIC chips include top layer metallic layer, and the top layer metallic layer is equipped with chip bonding area, the MCU chip setting
In the chip bonding area；And the MCU chip and the HVIC chips are electrically connected to the lead frame.
2. system according to claim 1 Integrated Smart Power module, which is characterized in that the HVIC chips include several
A driving unit and several groups power device, each driving unit be correspondingly connected with 2 groups described in power device；Work(described in every group
Rate device includes a LIGBT and FRD, and the LIGBT is connected with the FRD.
3. system according to claim 1 Integrated Smart Power module, which is characterized in that the top layer gold of the HVIC chips
Belonging to layer includes：The first metal layer, and the second metal layer of turmeric processing formation is carried out to the surface of the first metal layer；Institute
Chip bonding area is stated in the second metal layer.
4. system according to claim 1 Integrated Smart Power module, which is characterized in that the MCU chip includes several
A bonding welding pad, the part in several described bonding welding pads is connected to the HVIC chips by wire bonding, if described
Another part in dry bonding welding pad is connected to the lead frame by wire bonding；
The HVIC chips are connected to the lead frame by wire bonding.
5. system according to claim 1 Integrated Smart Power module, which is characterized in that the MCU chip passes through lead
Bonding is connected to the lead frame, and the HVIC chips are connected to the lead frame by wire bonding.
6. system according to claim 1 Integrated Smart Power module, which is characterized in that the MCU chip passes through lead
Bonding is connected to the HVIC chips, and the HVIC chips are connected to the lead frame by wire bonding.
7. system according to claim 1 Integrated Smart Power module, which is characterized in that the MCU chip is pasted on institute
State chip bonding area.
8. system according to claim 1 Integrated Smart Power module, which is characterized in that the HVIC chips are pasted on institute
State lead frame.
9. system integration intelligent power module according to claim 8, which is characterized in that the HVIC chips pass through elargol
Or tin-lead solder is pasted on the lead frame.
10. system according to claim 1 Integrated Smart Power module, which is characterized in that the chip bonding area is located at
The intermediate region of the top layer metallic layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820419599.6U CN207637790U (en) | 2018-03-27 | 2018-03-27 | A kind of system integration intelligent power module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820419599.6U CN207637790U (en) | 2018-03-27 | 2018-03-27 | A kind of system integration intelligent power module |
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| Publication Number | Publication Date |
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| CN207637790U true CN207637790U (en) | 2018-07-20 |
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| CN201820419599.6U Active CN207637790U (en) | 2018-03-27 | 2018-03-27 | A kind of system integration intelligent power module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151521A (en) * | 2019-06-26 | 2020-12-29 | 珠海零边界集成电路有限公司 | Power module and electronic equipment |
-
2018
- 2018-03-27 CN CN201820419599.6U patent/CN207637790U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151521A (en) * | 2019-06-26 | 2020-12-29 | 珠海零边界集成电路有限公司 | Power module and electronic equipment |
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